168 lines
6.3 KiB
C
168 lines
6.3 KiB
C
/*********************************************************************************************************************
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* CH32V307VCT6 Opensourec Library 即（CH32V307VCT6 开源库）是一个基于官方 SDK 接口的第三方开源库
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* Copyright (c) 2022 SEEKFREE 逐飞科技
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*
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* 本文件是CH32V307VCT6 开源库的一部分
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*
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* CH32V307VCT6 开源库 是免费软件
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* 您可以根据自由软件基金会发布的 GPL（GNU General Public License，即 GNU通用公共许可证）的条款
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* 即 GPL 的第3版（即 GPL3.0）或（您选择的）任何后来的版本，重新发布和/或修改它
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*
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* 本开源库的发布是希望它能发挥作用，但并未对其作任何的保证
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* 甚至没有隐含的适销性或适合特定用途的保证
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* 更多细节请参见 GPL
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*
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* 您应该在收到本开源库的同时收到一份 GPL 的副本
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* 如果没有，请参阅<https://www.gnu.org/licenses/>
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*
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* 额外注明：
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* 本开源库使用 GPL3.0 开源许可证协议 以上许可申明为译文版本
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* 许可申明英文版在 libraries/doc 文件夹下的 GPL3_permission_statement.txt 文件中
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* 许可证副本在 libraries 文件夹下 即该文件夹下的 LICENSE 文件
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* 欢迎各位使用并传播本程序 但修改内容时必须保留逐飞科技的版权声明（即本声明）
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*
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* 文件名称 zf_common_clock
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* 公司名称 成都逐飞科技有限公司
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* 版本信息 查看 libraries/doc 文件夹内 version 文件 版本说明
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* 开发环境 MounRiver Studio V1.8.1
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* 适用平台 CH32V307VCT6
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* 店铺链接 https://seekfree.taobao.com/
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*
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* 修改记录
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* 日期 作者 备注
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* 2022-09-15 大W first version
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********************************************************************************************************************/
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#include "ch32v30x.h"
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#include "zf_common_function.h"
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#include "zf_common_interrupt.h"
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#include "zf_common_clock.h"
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uint32 system_clock = SYSTEM_CLOCK_144M; // 系统时钟信息
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//-------------------------------------------------------------------------------------------------------------------
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// 函数简介 核心时钟恢复初始设置 内部调用
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// 参数说明 void
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// 返回参数 void
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//-------------------------------------------------------------------------------------------------------------------
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void clock_reset(void)
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{
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RCC->CTLR |= (uint32) 0x00000001; //使能HSI振荡器
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RCC->CFGR0 &= (uint32) 0xF8FF0000;
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RCC->CTLR &= (uint32) 0xFEF6FFFF;
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RCC->CTLR &= (uint32) 0xFFFBFFFF;
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RCC->CFGR0 &= (uint32) 0xFF80FFFF;
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RCC->INTR = (uint32) 0x009F0000; // 禁用所有中断并清除挂起位
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}
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//-------------------------------------------------------------------------------------------------------------------
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// 函数简介 核心时钟设置
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// 参数说明 clock 时钟频率 推荐使用 zf_common_clock.h 中 system_clock_enum 定义的选项
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// 返回参数 void
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//-------------------------------------------------------------------------------------------------------------------
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void clock_set_freq(uint32 clock)
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{
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clock_reset();
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ((uint32_t) RCC_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do {
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if ((RCC->CTLR & RCC_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t) 0x01;
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}
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else
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{
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HSEStatus = (uint32_t) 0x00;
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}
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if (HSEStatus == (uint32_t) 0x01)
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{
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// /* Enable Prefetch Buffer */
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// FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; ((uint8_t)0x10)
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//
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// /* Flash 2 wait state */
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// FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); ((uint8_t)0x03)
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// FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; ((uint8_t)0x02)
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t) RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t) RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t) RCC_PPRE1_DIV1;
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/* PLL configuration: PLLCLK = HSE * ? = ? MHz */
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RCC->CFGR0 &= (uint32) ((uint32) ~(RCC_PLLSRC | RCC_PLLXTPRE
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| RCC_PLLMULL));
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if (clock == SYSTEM_CLOCK_144M)
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RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
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| RCC_PLLMULL18_EXTEN);
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else if (clock == SYSTEM_CLOCK_120M)
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RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
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| RCC_PLLMULL15_EXTEN);
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else if (clock == SYSTEM_CLOCK_96M)
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RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
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| RCC_PLLMULL12_EXTEN);
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else if (clock == SYSTEM_CLOCK_72M)
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RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
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| RCC_PLLMULL9_EXTEN);
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else if (clock == SYSTEM_CLOCK_48M)
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RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
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| RCC_PLLMULL6_EXTEN);
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else if (clock == SYSTEM_CLOCK_24M)
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RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
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| RCC_PLLMULL3_EXTEN);
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CTLR & RCC_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= (uint32_t) ((uint32_t) ~(RCC_SW));
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RCC->CFGR0 |= (uint32_t) RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
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{
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}
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}
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else
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{
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while(1);
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// 外部晶振不稳定或缺失 时钟设置失败
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/*
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* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error
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*/
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}
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}
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//-------------------------------------------------------------------------------------------------------------------
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// 函数简介 核心时钟初始化
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// 参数说明 clock 时钟频率 推荐使用 zf_common_clock.h 中 system_clock_enum 定义的选项
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// 返回参数 void
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// 使用示例 clock_init(SYSTEM_CLOCK_144M); // 初始化核心时钟为 144MHz
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//-------------------------------------------------------------------------------------------------------------------
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void clock_init(uint32 clock)
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{
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system_clock = clock; // 记录核心时钟频率
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clock_reset();
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clock_set_freq(clock);
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interrupt_init();
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}
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