btl143/QD4C-firmware
4
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

first commit

Browse Source
This commit is contained in:
CaoWangrenbo
2023-12-11 21:45:06 +08:00
commit eaa7cc0eea
180 changed files with 60911 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5243
libraries/sdk/Peripheral/ch32v30x.h Normal file
View File

File diff suppressed because it is too large Load Diff

1180
libraries/sdk/Peripheral/ch32v30x_adc.c Normal file
View File

File diff suppressed because it is too large Load Diff

228
libraries/sdk/Peripheral/ch32v30x_adc.h Normal file
View File

@@ -0,0 +1,228 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_adc.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* ADC firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_ADC_H
#define __CH32V30x_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* ADC Init structure definition */
typedef struct
{
uint32_t ADC_Mode; /* Configures the ADC to operate in independent or
dual mode.
This parameter can be a value of @ref ADC_mode */
FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in
Scan (multichannels) or Single (one channel) mode.
This parameter can be set to ENABLE or DISABLE */
FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog
to digital conversion of regular channels. This parameter
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right.
This parameter can be a value of @ref ADC_data_align */
uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted
using the sequencer for regular channel group.
This parameter must range from 1 to 16. */
uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled.
This parameter can be a value of @ref ADC_OutputBuffer */
uint32_t ADC_Pga; /* Specifies the PGA gain multiple.
This parameter can be a value of @ref ADC_Pga */
}ADC_InitTypeDef;
/* ADC_mode */
#define ADC_Mode_Independent ((uint32_t)0x00000000)
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
/* ADC_external_trigger_sources_for_regular_channels_conversion */
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000)
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000)
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000)
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000)
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000)
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000)
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000)
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000)
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000)
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000)
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000)
/* ADC_data_align */
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
/* ADC_channels */
#define ADC_Channel_0 ((uint8_t)0x00)
#define ADC_Channel_1 ((uint8_t)0x01)
#define ADC_Channel_2 ((uint8_t)0x02)
#define ADC_Channel_3 ((uint8_t)0x03)
#define ADC_Channel_4 ((uint8_t)0x04)
#define ADC_Channel_5 ((uint8_t)0x05)
#define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_9 ((uint8_t)0x09)
#define ADC_Channel_10 ((uint8_t)0x0A)
#define ADC_Channel_11 ((uint8_t)0x0B)
#define ADC_Channel_12 ((uint8_t)0x0C)
#define ADC_Channel_13 ((uint8_t)0x0D)
#define ADC_Channel_14 ((uint8_t)0x0E)
#define ADC_Channel_15 ((uint8_t)0x0F)
#define ADC_Channel_16 ((uint8_t)0x10)
#define ADC_Channel_17 ((uint8_t)0x11)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
/*ADC_output_buffer*/
#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000)
#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000)
/*ADC_pga*/
#define ADC_Pga_1 ((uint32_t)0x00000000)
#define ADC_Pga_4 ((uint32_t)0x08000000)
#define ADC_Pga_16 ((uint32_t)0x10000000)
#define ADC_Pga_64 ((uint32_t)0x18000000)
/* ADC_sampling_time */
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
/* ADC_external_trigger_sources_for_injected_channels_conversion */
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000)
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000)
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000)
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000)
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000)
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000)
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000)
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000)
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000)
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000)
/* ADC_injected_channel_selection */
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
/* ADC_analog_watchdog_selection */
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
/* ADC_interrupts_definition */
#define ADC_IT_EOC ((uint16_t)0x0220)
#define ADC_IT_AWD ((uint16_t)0x0140)
#define ADC_IT_JEOC ((uint16_t)0x0480)
/* ADC_flags_definition */
#define ADC_FLAG_AWD ((uint8_t)0x01)
#define ADC_FLAG_EOC ((uint8_t)0x02)
#define ADC_FLAG_JEOC ((uint8_t)0x04)
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
#define ADC_FLAG_STRT ((uint8_t)0x10)
void ADC_DeInit(ADC_TypeDef* ADCx);
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
void ADC_ResetCalibration(ADC_TypeDef* ADCx);
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_StartCalibration(ADC_TypeDef* ADCx);
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
uint32_t ADC_GetDualModeConversionValue(void);
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
s32 TempSensor_Volt_To_Temper(s32 Value);
void ADC_BufferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
int16_t Get_CalibrationValue(ADC_TypeDef* ADCx);
#ifdef __cplusplus
}
#endif
#endif

242
libraries/sdk/Peripheral/ch32v30x_bkp.c Normal file
View File

@@ -0,0 +1,242 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_bkp.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the BKP firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v30x_bkp.h"
#include "ch32v30x_rcc.h"
/* BKP registers bit mask */
/* OCTLR register bit mask */
#define OCTLR_CAL_MASK ((uint16_t)0xFF80)
#define OCTLR_MASK ((uint16_t)0xFC7F)
/*********************************************************************
* @fn BKP_DeInit
*
* @brief Deinitializes the BKP peripheral registers to their default reset values.
*
* @return none
*/
void BKP_DeInit(void)
{
RCC_BackupResetCmd(ENABLE);
RCC_BackupResetCmd(DISABLE);
}
/*********************************************************************
* @fn BKP_TamperPinLevelConfig
*
* @brief Configures the Tamper Pin active level.
*
* @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
* BKP_TamperPinLevel_High - Tamper pin active on high level.
* BKP_TamperPinLevel_Low - Tamper pin active on low level.
*
* @return none
*/
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
{
if(BKP_TamperPinLevel)
{
BKP->TPCTLR |= (1 << 1);
}
else
{
BKP->TPCTLR &= ~(1 << 1);
}
}
/*********************************************************************
* @fn BKP_TamperPinCmd
*
* @brief Enables or disables the Tamper Pin activation.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void BKP_TamperPinCmd(FunctionalState NewState)
{
if(NewState)
{
BKP->TPCTLR |= (1 << 0);
}
else
{
BKP->TPCTLR &= ~(1 << 0);
}
}
/*********************************************************************
* @fn BKP_ITConfig
*
* @brief Enables or disables the Tamper Pin Interrupt.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void BKP_ITConfig(FunctionalState NewState)
{
if(NewState)
{
BKP->TPCSR |= (1 << 2);
}
else
{
BKP->TPCSR &= ~(1 << 2);
}
}
/*********************************************************************
* @fn BKP_RTCOutputConfig
*
* @brief Select the RTC output source to output on the Tamper pin.
*
* @param BKP_RTCOutputSource - specifies the RTC output source.
* BKP_RTCOutputSource_None - no RTC output on the Tamper pin.
* BKP_RTCOutputSource_CalibClock - output the RTC clock with
* frequency divided by 64 on the Tamper pin.
* BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal
* on the Tamper pin.
* BKP_RTCOutputSource_Second - output the RTC Second pulse
* signal on the Tamper pin.
*
* @return none
*/
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
{
uint16_t tmpreg = 0;
tmpreg = BKP->OCTLR;
tmpreg &= OCTLR_MASK;
tmpreg |= BKP_RTCOutputSource;
BKP->OCTLR = tmpreg;
}
/*********************************************************************
* @fn BKP_SetRTCCalibrationValue
*
* @brief Sets RTC Clock Calibration value.
*
* @param CalibrationValue - specifies the RTC Clock Calibration value.
* This parameter must be a number between 0 and 0x1F.
*
* @return none
*/
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
{
uint16_t tmpreg = 0;
tmpreg = BKP->OCTLR;
tmpreg &= OCTLR_CAL_MASK;
tmpreg |= CalibrationValue;
BKP->OCTLR = tmpreg;
}
/*********************************************************************
* @fn BKP_WriteBackupRegister
*
* @brief Writes user data to the specified Data Backup Register.
*
* @param BKP_DR - specifies the Data Backup Register.
* Data - data to write.
*
* @return none
*/
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)BKP_BASE;
tmp += BKP_DR;
*(__IO uint32_t *)tmp = Data;
}
/*********************************************************************
* @fn BKP_ReadBackupRegister
*
* @brief Reads data from the specified Data Backup Register.
*
* @param BKP_DR - specifies the Data Backup Register.
* This parameter can be BKP_DRx where x=[1, 42].
*
* @return none
*/
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)BKP_BASE;
tmp += BKP_DR;
return (*(__IO uint16_t *)tmp);
}
/*********************************************************************
* @fn BKP_GetFlagStatus
*
* @brief Checks whether the Tamper Pin Event flag is set or not.
*
* @return FlagStatus - SET or RESET.
*/
FlagStatus BKP_GetFlagStatus(void)
{
if(BKP->TPCSR & (1 << 8))
{
return SET;
}
else
{
return RESET;
}
}
/*********************************************************************
* @fn BKP_ClearFlag
*
* @brief Clears Tamper Pin Event pending flag.
*
* @return none
*/
void BKP_ClearFlag(void)
{
BKP->TPCSR |= BKP_CTE;
}
/*********************************************************************
* @fn BKP_GetITStatus
*
* @brief Checks whether the Tamper Pin Interrupt has occurred or not.
*
* @return ITStatus - SET or RESET.
*/
ITStatus BKP_GetITStatus(void)
{
if(BKP->TPCSR & (1 << 9))
{
return SET;
}
else
{
return RESET;
}
}
/*********************************************************************
* @fn BKP_ClearITPendingBit
*
* @brief Clears Tamper Pin Interrupt pending bit.
*
* @return none
*/
void BKP_ClearITPendingBit(void)
{
BKP->TPCSR |= BKP_CTI;
}

97
libraries/sdk/Peripheral/ch32v30x_bkp.h Normal file
View File

@@ -0,0 +1,97 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_bkp.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* BKP firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_BKP_H
#define __CH32V30x_BKP_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* Tamper_Pin_active_level */
#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
/* RTC_output_source_to_output_on_the_Tamper_pin */
#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
/* Data_Backup_Register */
#define BKP_DR1 ((uint16_t)0x0004)
#define BKP_DR2 ((uint16_t)0x0008)
#define BKP_DR3 ((uint16_t)0x000C)
#define BKP_DR4 ((uint16_t)0x0010)
#define BKP_DR5 ((uint16_t)0x0014)
#define BKP_DR6 ((uint16_t)0x0018)
#define BKP_DR7 ((uint16_t)0x001C)
#define BKP_DR8 ((uint16_t)0x0020)
#define BKP_DR9 ((uint16_t)0x0024)
#define BKP_DR10 ((uint16_t)0x0028)
#define BKP_DR11 ((uint16_t)0x0040)
#define BKP_DR12 ((uint16_t)0x0044)
#define BKP_DR13 ((uint16_t)0x0048)
#define BKP_DR14 ((uint16_t)0x004C)
#define BKP_DR15 ((uint16_t)0x0050)
#define BKP_DR16 ((uint16_t)0x0054)
#define BKP_DR17 ((uint16_t)0x0058)
#define BKP_DR18 ((uint16_t)0x005C)
#define BKP_DR19 ((uint16_t)0x0060)
#define BKP_DR20 ((uint16_t)0x0064)
#define BKP_DR21 ((uint16_t)0x0068)
#define BKP_DR22 ((uint16_t)0x006C)
#define BKP_DR23 ((uint16_t)0x0070)
#define BKP_DR24 ((uint16_t)0x0074)
#define BKP_DR25 ((uint16_t)0x0078)
#define BKP_DR26 ((uint16_t)0x007C)
#define BKP_DR27 ((uint16_t)0x0080)
#define BKP_DR28 ((uint16_t)0x0084)
#define BKP_DR29 ((uint16_t)0x0088)
#define BKP_DR30 ((uint16_t)0x008C)
#define BKP_DR31 ((uint16_t)0x0090)
#define BKP_DR32 ((uint16_t)0x0094)
#define BKP_DR33 ((uint16_t)0x0098)
#define BKP_DR34 ((uint16_t)0x009C)
#define BKP_DR35 ((uint16_t)0x00A0)
#define BKP_DR36 ((uint16_t)0x00A4)
#define BKP_DR37 ((uint16_t)0x00A8)
#define BKP_DR38 ((uint16_t)0x00AC)
#define BKP_DR39 ((uint16_t)0x00B0)
#define BKP_DR40 ((uint16_t)0x00B4)
#define BKP_DR41 ((uint16_t)0x00B8)
#define BKP_DR42 ((uint16_t)0x00BC)
void BKP_DeInit(void);
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
void BKP_TamperPinCmd(FunctionalState NewState);
void BKP_ITConfig(FunctionalState NewState);
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
FlagStatus BKP_GetFlagStatus(void);
void BKP_ClearFlag(void);
ITStatus BKP_GetITStatus(void);
void BKP_ClearITPendingBit(void);
#ifdef __cplusplus
}
#endif
#endif

1207
libraries/sdk/Peripheral/ch32v30x_can.c Normal file
View File

File diff suppressed because it is too large Load Diff

366
libraries/sdk/Peripheral/ch32v30x_can.h Normal file
View File

@@ -0,0 +1,366 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_can.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* CAN firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_CAN_H
#define __CH32V30x_CAN_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* CAN init structure definition */
typedef struct
{
uint16_t CAN_Prescaler; /* Specifies the length of a time quantum.
It ranges from 1 to 1024. */
uint8_t CAN_Mode; /* Specifies the CAN operating mode.
This parameter can be a value of
@ref CAN_operating_mode */
uint8_t CAN_SJW; /* Specifies the maximum number of time quanta
the CAN hardware is allowed to lengthen or
shorten a bit to perform resynchronization.
This parameter can be a value of
@ref CAN_synchronisation_jump_width */
uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit
Segment 1. This parameter can be a value of
@ref CAN_time_quantum_in_bit_segment_1 */
uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit
Segment 2.
This parameter can be a value of
@ref CAN_time_quantum_in_bit_segment_2 */
FunctionalState CAN_TTCM; /* Enable or disable the time triggered
communication mode. This parameter can be set
either to ENABLE or DISABLE. */
FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off
management. This parameter can be set either
to ENABLE or DISABLE. */
FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode.
This parameter can be set either to ENABLE or
DISABLE. */
FunctionalState CAN_NART; /* Enable or disable the no-automatic
retransmission mode. This parameter can be
set either to ENABLE or DISABLE. */
FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode.
This parameter can be set either to ENABLE
or DISABLE. */
FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority.
This parameter can be set either to ENABLE
or DISABLE. */
} CAN_InitTypeDef;
/* CAN filter init structure definition */
typedef struct
{
uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */
uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
uint8_t CAN_FilterScale; /* Specifies the filter scale.
This parameter can be a value of @ref CAN_filter_scale */
FunctionalState CAN_FilterActivation; /* Enable or disable the filter.
This parameter can be set either to ENABLE or DISABLE. */
} CAN_FilterInitTypeDef;
/* CAN Tx message structure definition */
typedef struct
{
uint32_t StdId; /* Specifies the standard identifier.
This parameter can be a value between 0 to 0x7FF. */
uint32_t ExtId; /* Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
uint8_t IDE; /* Specifies the type of identifier for the message that
will be transmitted. This parameter can be a value
of @ref CAN_identifier_type */
uint8_t RTR; /* Specifies the type of frame for the message that will
be transmitted. This parameter can be a value of
@ref CAN_remote_transmission_request */
uint8_t DLC; /* Specifies the length of the frame that will be
transmitted. This parameter can be a value between
0 to 8 */
uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0
to 0xFF. */
} CanTxMsg;
/* CAN Rx message structure definition */
typedef struct
{
uint32_t StdId; /* Specifies the standard identifier.
This parameter can be a value between 0 to 0x7FF. */
uint32_t ExtId; /* Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
uint8_t IDE; /* Specifies the type of identifier for the message that
will be received. This parameter can be a value of
@ref CAN_identifier_type */
uint8_t RTR; /* Specifies the type of frame for the received message.
This parameter can be a value of
@ref CAN_remote_transmission_request */
uint8_t DLC; /* Specifies the length of the frame that will be received.
This parameter can be a value between 0 to 8 */
uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to
0xFF. */
uint8_t FMI; /* Specifies the index of the filter the message stored in
the mailbox passes through. This parameter can be a
value between 0 to 0xFF */
} CanRxMsg;
/* CAN_sleep_constants */
#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */
#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */
/* CAN_Mode */
#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */
#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */
#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */
/* CAN_Operating_Mode */
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */
/* CAN_Mode_Status */
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */
/* CAN_synchronisation_jump_width */
#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */
#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */
#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */
#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */
/* CAN_time_quantum_in_bit_segment_1 */
#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */
#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */
#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */
#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */
#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */
#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */
#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */
#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */
#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */
#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */
#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */
#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */
#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */
#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */
#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */
#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */
/* CAN_time_quantum_in_bit_segment_2 */
#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */
#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */
#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */
#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */
#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */
#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */
#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */
#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */
/* CAN_filter_mode */
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */
#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */
/* CAN_filter_scale */
#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */
#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */
/* CAN_filter_FIFO */
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */
/* CAN_identifier_type */
#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */
#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */
/* CAN_remote_transmission_request */
#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */
#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */
/* CAN_transmit_constants */
#define CAN_TxStatus_Failed ((uint8_t)0x00)/* CAN transmission failed */
#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */
#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */
/* CAN_receive_FIFO_number_constants */
#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */
/* CAN_sleep_constants */
#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */
#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */
/* CAN_wake_up_constants */
#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */
#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */
/* CAN_Error_Code_constants */
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */
/* CAN_flags */
/* Transmit Flags */
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */
/* Receive Flags */
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */
/* Operating Mode Flags */
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */
/* Error Flags */
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */
/* CAN_interrupts */
#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/
/* Receive Interrupts */
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/
#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/
#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/
/* Operating Mode Interrupts */
#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/
#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/
/* Error Interrupts */
#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/
#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/
#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/
#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/
#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/
/* Flags named as Interrupts : kept only for FW compatibility */
#define CAN_IT_RQCP0 CAN_IT_TME
#define CAN_IT_RQCP1 CAN_IT_TME
#define CAN_IT_RQCP2 CAN_IT_TME
/* CAN_Legacy */
#define CANINITFAILED CAN_InitStatus_Failed
#define CANINITOK CAN_InitStatus_Success
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
#define CAN_ID_STD CAN_Id_Standard
#define CAN_ID_EXT CAN_Id_Extended
#define CAN_RTR_DATA CAN_RTR_Data
#define CAN_RTR_REMOTE CAN_RTR_Remote
#define CANTXFAILE CAN_TxStatus_Failed
#define CANTXOK CAN_TxStatus_Ok
#define CANTXPENDING CAN_TxStatus_Pending
#define CAN_NO_MB CAN_TxStatus_NoMailBox
#define CANSLEEPFAILED CAN_Sleep_Failed
#define CANSLEEPOK CAN_Sleep_Ok
#define CANWAKEUPFAILED CAN_WakeUp_Failed
#define CANWAKEUPOK CAN_WakeUp_Ok
void CAN_DeInit(CAN_TypeDef* CANx);
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
#ifdef __cplusplus
}
#endif
#endif

98
libraries/sdk/Peripheral/ch32v30x_crc.c Normal file
View File

@@ -0,0 +1,98 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_crc.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the CRC firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v30x_crc.h"
/*********************************************************************
* @fn CRC_ResetDR
*
* @brief Resets the CRC Data register (DR).
*
* @return none
*/
void CRC_ResetDR(void)
{
CRC->CTLR = CRC_CTLR_RESET;
}
/*********************************************************************
* @fn CRC_CalcCRC
*
* @brief Computes the 32-bit CRC of a given data word(32-bit).
*
* @param Data - data word(32-bit) to compute its CRC.
*
* @return 32-bit CRC.
*/
uint32_t CRC_CalcCRC(uint32_t Data)
{
CRC->DATAR = Data;
return (CRC->DATAR);
}
/*********************************************************************
* @fn CRC_CalcBlockCRC
*
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
*
* @param pBuffer - pointer to the buffer containing the data to be computed.
* BufferLength - length of the buffer to be computed.
*
* @return 32-bit CRC.
*/
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0;
for(index = 0; index < BufferLength; index++)
{
CRC->DATAR = pBuffer[index];
}
return (CRC->DATAR);
}
/*********************************************************************
* @fn CRC_GetCRC
*
* @brief Returns the current CRC value.
*
* @return 32-bit CRC.
*/
uint32_t CRC_GetCRC(void)
{
return (CRC->DATAR);
}
/*********************************************************************
* @fn CRC_SetIDRegister
*
* @brief Stores a 8-bit data in the Independent Data(ID) register.
*
* @param IDValue - 8-bit value to be stored in the ID register.
*
* @return none
*/
void CRC_SetIDRegister(uint8_t IDValue)
{
CRC->IDATAR = IDValue;
}
/*********************************************************************
* @fn CRC_GetIDRegister
*
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.
*
* @return 8-bit value of the ID register.
*/
uint8_t CRC_GetIDRegister(void)
{
return (CRC->IDATAR);
}

37
libraries/sdk/Peripheral/ch32v30x_crc.h Normal file
View File

@@ -0,0 +1,37 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_crc.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* CRC firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_CRC_H
#define __CH32V30x_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
void CRC_ResetDR(void);
uint32_t CRC_CalcCRC(uint32_t Data);
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
uint32_t CRC_GetCRC(void);
void CRC_SetIDRegister(uint8_t IDValue);
uint8_t CRC_GetIDRegister(void);
#ifdef __cplusplus
}
#endif
#endif

302
libraries/sdk/Peripheral/ch32v30x_dac.c Normal file
View File

@@ -0,0 +1,302 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_dac.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the DAC firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
****************************************************************************************/
#include "ch32v30x_dac.h"
#include "ch32v30x_rcc.h"
/* CTLR register Mask */
#define CTLR_CLEAR_MASK ((uint32_t)0x00000FFE)
/* DAC Dual Channels SWTR masks */
#define DUAL_SWTR_SET ((uint32_t)0x00000003)
#define DUAL_SWTR_RESET ((uint32_t)0xFFFFFFFC)
/* DHR registers offsets */
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
/* DOR register offset */
#define DOR_OFFSET ((uint32_t)0x0000002C)
/*********************************************************************
* @fn DAC_DeInit
*
* @brief Deinitializes the DAC peripheral registers to their default reset values.
*
* @return none
*/
void DAC_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
}
/*********************************************************************
* @fn DAC_Init
*
* @brief Initializes the DAC peripheral according to the specified parameters in
* the DAC_InitStruct.
*
* @param DAC_Channel - the selected DAC channel.
* DAC_Channel_1 - DAC Channel1 selected
* DAC_Channel_2 - DAC Channel2 selected
* DAC_InitStruct - pointer to a DAC_InitTypeDef structure.
*
* @return none
*/
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
tmpreg1 = DAC->CTLR;
tmpreg1 &= ~(CTLR_CLEAR_MASK << DAC_Channel);
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
tmpreg1 |= tmpreg2 << DAC_Channel;
DAC->CTLR = tmpreg1;
}
/*********************************************************************
* @fn DAC_StructInit
*
* @brief Fills each DAC_InitStruct member with its default value.
*
* @param DAC_InitStruct - pointer to a DAC_InitTypeDef structure which will be initialized.
*
* @return none
*/
void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct)
{
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
}
/*********************************************************************
* @fn DAC_Cmd
*
* @brief Enables or disables the specified DAC channel.
*
* @param DAC_Channel - the selected DAC channel.
* DAC_Channel_1 - DAC Channel1 selected
* DAC_Channel_2 - DAC Channel2 selected
* NewState - new state of the DAC channel(ENABLE or DISABLE).
*
* @return none
*/
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
{
if(NewState != DISABLE)
{
DAC->CTLR |= (DAC_EN1 << DAC_Channel);
}
else
{
DAC->CTLR &= ~(DAC_EN1 << DAC_Channel);
}
}
/*********************************************************************
* @fn DAC_DMACmd
*
* @brief Enables or disables the specified DAC channel DMA request.
*
* @param DAC_Channel - the selected DAC channel.
* DAC_Channel_1 - DAC Channel1 selected
* DAC_Channel_2 - DAC Channel2 selected
* NewState - new state of the DAC channel(ENABLE or DISABLE).
*
* @return none
*/
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
{
if(NewState != DISABLE)
{
DAC->CTLR |= (DAC_DMAEN1 << DAC_Channel);
}
else
{
DAC->CTLR &= ~(DAC_DMAEN1 << DAC_Channel);
}
}
/*********************************************************************
* @fn DAC_SoftwareTriggerCmd
*
* @brief Enables or disables the selected DAC channel software trigger.
*
* @param DAC_Channel - the selected DAC channel.
* DAC_Channel_1 - DAC Channel1 selected
* DAC_Channel_2 - DAC Channel2 selected
* NewState - new state of the DAC channel(ENABLE or DISABLE).
*
* @return none
*/
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
{
if(NewState != DISABLE)
{
DAC->SWTR |= (uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4);
}
else
{
DAC->SWTR &= ~((uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4));
}
}
/*********************************************************************
* @fn DAC_DualSoftwareTriggerCmd
*
* @brief Enables or disables the two DAC channel software trigger.
*
* @param NewState - new state of the DAC channel(ENABLE or DISABLE).
*
* @return none
*/
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
{
if(NewState != DISABLE)
{
DAC->SWTR |= DUAL_SWTR_SET;
}
else
{
DAC->SWTR &= DUAL_SWTR_RESET;
}
}
/*********************************************************************
* @fn DAC_WaveGenerationCmd
*
* @brief Enables or disables the selected DAC channel wave generation.
*
* @param DAC_Channel - the selected DAC channel.
* DAC_Channel_1 - DAC Channel1 selected
* DAC_Channel_2 - DAC Channel2 selected
* DAC_Wave - Specifies the wave type to enable or disable.
* DAC_Wave_Noise - noise wave generation
* DAC_Wave_Triangle - triangle wave generation
* NewState - new state of the DAC channel(ENABLE or DISABLE).
*
* @return none
*/
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
{
if(NewState != DISABLE)
{
DAC->CTLR |= DAC_Wave << DAC_Channel;
}
else
{
DAC->CTLR &= ~(DAC_Wave << DAC_Channel);
}
}
/*********************************************************************
* @fn DAC_SetChannel1Data
*
* @brief Set the specified data holding register value for DAC channel1.
*
* @param DAC_Align - Specifies the data alignment for DAC channel1.
* DAC_Align_8b_R - 8bit right data alignment selected
* DAC_Align_12b_L - 12bit left data alignment selected
* DAC_Align_12b_R - 12bit right data alignment selected
* Data - Data to be loaded in the selected data holding register.
*
* @return none
*/
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R1_OFFSET + DAC_Align;
*(__IO uint32_t *)tmp = Data;
}
/*********************************************************************
* @fn DAC_SetChannel2Data
*
* @brief Set the specified data holding register value for DAC channel2.
*
* @param DAC_Align - Specifies the data alignment for DAC channel1.
* DAC_Align_8b_R - 8bit right data alignment selected
* DAC_Align_12b_L - 12bit left data alignment selected
* DAC_Align_12b_R - 12bit right data alignment selected
* Data - Data to be loaded in the selected data holding register.
*
* @return none
*/
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R2_OFFSET + DAC_Align;
*(__IO uint32_t *)tmp = Data;
}
/*********************************************************************
* @fn DAC_SetDualChannelData
*
* @brief Set the specified data holding register value for two DAC.
*
* @param DAC_Align - Specifies the data alignment for DAC channel1.
* DAC_Align_8b_R - 8bit right data alignment selected
* DAC_Align_12b_L - 12bit left data alignment selected
* DAC_Align_12b_R - 12bit right data alignment selected
* Data - Data to be loaded in the selected data holding register.
* Data1 - Data for DAC Channel1.
* Data2 - Data for DAC Channel2
*
* @return none
*/
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
{
uint32_t data = 0, tmp = 0;
if(DAC_Align == DAC_Align_8b_R)
{
data = ((uint32_t)Data2 << 8) | Data1;
}
else
{
data = ((uint32_t)Data2 << 16) | Data1;
}
tmp = (uint32_t)DAC_BASE;
tmp += DHR12RD_OFFSET + DAC_Align;
*(__IO uint32_t *)tmp = data;
}
/*********************************************************************
* @fn DAC_GetDataOutputValue
*
* @brief Returns the last data output value of the selected DAC channel.
*
* @param DAC_Channel - the selected DAC channel.
* DAC_Channel_1 - DAC Channel1 selected
* DAC_Channel_2 - DAC Channel2 selected
*
* @return none
*/
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)DAC_BASE;
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
return (uint16_t)(*(__IO uint32_t *)tmp);
}

120
libraries/sdk/Peripheral/ch32v30x_dac.h Normal file
View File

@@ -0,0 +1,120 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_dac.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* DAC firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_DAC_H
#define __CH32V30x_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* DAC Init structure definition */
typedef struct
{
uint32_t DAC_Trigger; /* Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
uint32_t DAC_WaveGeneration; /* Specifies whether DAC channel noise waves or triangle waves
are generated, or whether no wave is generated.
This parameter can be a value of @ref DAC_wave_generation */
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /* Specifies the LFSR mask for noise wave generation or
the maximum amplitude triangle generation for the DAC channel.
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
uint32_t DAC_OutputBuffer; /* Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
}DAC_InitTypeDef;
/* DAC_trigger_selection */
#define DAC_Trigger_None ((uint32_t)0x00000000) /* Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /* TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel
only in High-density devices*/
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /* TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /* TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /* TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /* TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /* EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /* Conversion started by software trigger for DAC channel */
/* DAC_wave_generation */
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
/* DAC_lfsrunmask_triangleamplitude */
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /* Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /* Select max triangle amplitude of 1 */
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /* Select max triangle amplitude of 3 */
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /* Select max triangle amplitude of 7 */
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /* Select max triangle amplitude of 15 */
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /* Select max triangle amplitude of 31 */
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /* Select max triangle amplitude of 63 */
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /* Select max triangle amplitude of 127 */
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /* Select max triangle amplitude of 255 */
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /* Select max triangle amplitude of 511 */
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /* Select max triangle amplitude of 1023 */
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /* Select max triangle amplitude of 2047 */
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /* Select max triangle amplitude of 4095 */
/* DAC_output_buffer */
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
/* DAC_Channel_selection */
#define DAC_Channel_1 ((uint32_t)0x00000000)
#define DAC_Channel_2 ((uint32_t)0x00000010)
/* DAC_data_alignment */
#define DAC_Align_12b_R ((uint32_t)0x00000000)
#define DAC_Align_12b_L ((uint32_t)0x00000004)
#define DAC_Align_8b_R ((uint32_t)0x00000008)
/* DAC_wave_generation */
#define DAC_Wave_Noise ((uint32_t)0x00000040)
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
void DAC_DeInit(void);
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
#ifdef __cplusplus
}
#endif
#endif

36
libraries/sdk/Peripheral/ch32v30x_dbgmcu.c Normal file
View File

@@ -0,0 +1,36 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_dbgmcu.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the DBGMCU firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
****************************************************************************************/
#include "ch32v30x_dbgmcu.h"
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
/*********************************************************************
* @fn DBGMCU_GetREVID
*
* @brief Returns the device revision identifier.
*
* @return Revision identifier.
*/
uint32_t DBGMCU_GetREVID(void)
{
return ((*(uint32_t *)0x1FFFF704) >> 16);
}
/*********************************************************************
* @fn DBGMCU_GetDEVID
*
* @brief Returns the device identifier.
*
* @return Device identifier.
*/
uint32_t DBGMCU_GetDEVID(void)
{
return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
}

35
libraries/sdk/Peripheral/ch32v30x_dbgmcu.h Normal file
View File

@@ -0,0 +1,35 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_dbgmcu.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* DBGMCU firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_DBGMCU_H
#define __CH32V30x_DBGMCU_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
uint32_t DBGMCU_GetREVID(void);
uint32_t DBGMCU_GetDEVID(void);
#ifdef __cplusplus
}
#endif
#endif

690
libraries/sdk/Peripheral/ch32v30x_dma.c Normal file
View File

@@ -0,0 +1,690 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_dma.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the DMA firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v30x_dma.h"
#include "ch32v30x_rcc.h"
/* DMA1 Channelx interrupt pending bit masks */
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
/* DMA2 Channelx interrupt pending bit masks */
#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
#define DMA2_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
#define DMA2_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
#define DMA2_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8))
#define DMA2_Channel9_IT_Mask ((uint32_t)(DMA_GIF9 | DMA_TCIF9 | DMA_HTIF9 | DMA_TEIF9))
#define DMA2_Channel10_IT_Mask ((uint32_t)(DMA_GIF10 | DMA_TCIF10 | DMA_HTIF10 | DMA_TEIF10))
#define DMA2_Channel11_IT_Mask ((uint32_t)(DMA_GIF11 | DMA_TCIF11 | DMA_HTIF11 | DMA_TEIF11))
/* DMA2 FLAG mask */
#define FLAG_Mask ((uint32_t)0x10000000)
#define DMA2_EXTEN_FLAG_Mask ((uint32_t)0x20000000)
/* DMA registers Masks */
#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
/*********************************************************************
* @fn DMA_DeInit
*
* @brief Deinitializes the DMAy Channelx registers to their default
* reset values.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
*
* @return none
*/
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
{
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
DMAy_Channelx->CFGR = 0;
DMAy_Channelx->CNTR = 0;
DMAy_Channelx->PADDR = 0;
DMAy_Channelx->MADDR = 0;
if(DMAy_Channelx == DMA1_Channel1)
{
DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel2)
{
DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel3)
{
DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel4)
{
DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel5)
{
DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel6)
{
DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel7)
{
DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
}
else if(DMAy_Channelx == DMA2_Channel1)
{
DMA2->INTFCR |= DMA2_Channel1_IT_Mask;
}
else if(DMAy_Channelx == DMA2_Channel2)
{
DMA2->INTFCR |= DMA2_Channel2_IT_Mask;
}
else if(DMAy_Channelx == DMA2_Channel3)
{
DMA2->INTFCR |= DMA2_Channel3_IT_Mask;
}
else if(DMAy_Channelx == DMA2_Channel4)
{
DMA2->INTFCR |= DMA2_Channel4_IT_Mask;
}
else if(DMAy_Channelx == DMA2_Channel5)
{
DMA2->INTFCR |= DMA2_Channel5_IT_Mask;
}
else if(DMAy_Channelx == DMA2_Channel6)
{
DMA2->INTFCR |= DMA2_Channel6_IT_Mask;
}
else if(DMAy_Channelx == DMA2_Channel7)
{
DMA2->INTFCR |= DMA2_Channel7_IT_Mask;
}
else if(DMAy_Channelx == DMA2_Channel8)
{
DMA2_EXTEN->INTFCR |= DMA2_Channel8_IT_Mask;
}
else if(DMAy_Channelx == DMA2_Channel9)
{
DMA2_EXTEN->INTFCR |= DMA2_Channel9_IT_Mask;
}
else if(DMAy_Channelx == DMA2_Channel10)
{
DMA2_EXTEN->INTFCR |= DMA2_Channel10_IT_Mask;
}
else if(DMAy_Channelx == DMA2_Channel11)
{
DMA2_EXTEN->INTFCR |= DMA2_Channel11_IT_Mask;
}
}
/*********************************************************************
* @fn DMA_Init
*
* @brief Initializes the DMAy Channelx according to the specified
* parameters in the DMA_InitStruct.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
* contains the configuration information for the specified DMA Channel.
*
* @return none
*/
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
{
uint32_t tmpreg = 0;
tmpreg = DMAy_Channelx->CFGR;
tmpreg &= CFGR_CLEAR_Mask;
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
DMAy_Channelx->CFGR = tmpreg;
DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
}
/*********************************************************************
* @fn DMA_StructInit
*
* @brief Fills each DMA_InitStruct member with its default value.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
* contains the configuration information for the specified DMA Channel.
*
* @return none
*/
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
{
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStruct->DMA_BufferSize = 0;
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
}
/*********************************************************************
* @fn DMA_Cmd
*
* @brief Enables or disables the specified DMAy Channelx.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
*
* @return none
*/
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
}
else
{
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
}
}
/*********************************************************************
* @fn DMA_ITConfig
*
* @brief Enables or disables the specified DMAy Channelx interrupts.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* DMA_IT - specifies the DMA interrupts sources to be enabled
* or disabled.
* DMA_IT_TC - Transfer complete interrupt mask
* DMA_IT_HT - Half transfer interrupt mask
* DMA_IT_TE - Transfer error interrupt mask
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
*
* @return none
*/
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
{
if(NewState != DISABLE)
{
DMAy_Channelx->CFGR |= DMA_IT;
}
else
{
DMAy_Channelx->CFGR &= ~DMA_IT;
}
}
/*********************************************************************
* @fn DMA_SetCurrDataCounter
*
* @brief Sets the number of data units in the current DMAy Channelx transfer.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* DataNumber - The number of data units in the current DMAy Channelx
* transfer.
*
* @return none
*/
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
{
DMAy_Channelx->CNTR = DataNumber;
}
/*********************************************************************
* @fn DMA_GetCurrDataCounter
*
* @brief Returns the number of remaining data units in the current
* DMAy Channelx transfer.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
*
* @return DataNumber - The number of remaining data units in the current
* DMAy Channelx transfer.
*/
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
{
return ((uint16_t)(DMAy_Channelx->CNTR));
}
/*********************************************************************
* @fn DMA_GetFlagStatus
*
* @brief Checks whether the specified DMAy Channelx flag is set or not.
*
* @param DMAy_FLAG - specifies the flag to check.
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
* DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
* DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
* DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
* DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
* DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
* DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
* DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
* DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
* DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
* DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
* DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
* DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
* DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
* DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
* DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
* DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
* DMA2_FLAG_GL6 - DMA2 Channel6 global flag.
* DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag.
* DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag.
* DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag.
* DMA2_FLAG_GL7 - DMA2 Channel7 global flag.
* DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag.
* DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag.
* DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag.
* DMA2_FLAG_GL8 - DMA2 Channel8 global flag.
* DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag.
* DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag.
* DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag.
* DMA2_FLAG_GL9 - DMA2 Channel9 global flag.
* DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag.
* DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag.
* DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag.
* DMA2_FLAG_GL10 - DMA2 Channel10 global flag.
* DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag.
* DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag.
* DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag.
* DMA2_FLAG_GL11 - DMA2 Channel11 global flag.
* DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag.
* DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag.
* DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag.
*
* @return The new state of DMAy_FLAG (SET or RESET).
*/
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpreg = 0;
if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask)
{
tmpreg = DMA2->INTFR;
}
else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
{
tmpreg = DMA2_EXTEN->INTFR;
}
else
{
tmpreg = DMA1->INTFR;
}
if((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn DMA_ClearFlag
*
* @brief Clears the DMAy Channelx's pending flags.
*
* @param DMAy_FLAG - specifies the flag to check.
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
* DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
* DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
* DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
* DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
* DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
* DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
* DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
* DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
* DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
* DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
* DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
* DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
* DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
* DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
* DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
* DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
* DMA2_FLAG_GL6 - DMA2 Channel6 global flag.
* DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag.
* DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag.
* DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag.
* DMA2_FLAG_GL7 - DMA2 Channel7 global flag.
* DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag.
* DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag.
* DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag.
* DMA2_FLAG_GL8 - DMA2 Channel8 global flag.
* DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag.
* DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag.
* DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag.
* DMA2_FLAG_GL9 - DMA2 Channel9 global flag.
* DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag.
* DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag.
* DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag.
* DMA2_FLAG_GL10 - DMA2 Channel10 global flag.
* DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag.
* DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag.
* DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag.
* DMA2_FLAG_GL11 - DMA2 Channel11 global flag.
* DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag.
* DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag.
* DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag.
*
* @return none
*/
void DMA_ClearFlag(uint32_t DMAy_FLAG)
{
if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask)
{
DMA2->INTFCR = DMAy_FLAG;
}
else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
{
DMA2_EXTEN->INTFCR = DMAy_FLAG;
}
else
{
DMA1->INTFCR = DMAy_FLAG;
}
}
/*********************************************************************
* @fn DMA_GetITStatus
*
* @brief Checks whether the specified DMAy Channelx interrupt has
* occurred or not.
*
* @param DMAy_IT - specifies the DMAy interrupt source to check.
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
* DMA2_IT_GL2 - DMA2 Channel2 global flag.
* DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
* DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
* DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
* DMA2_IT_GL3 - DMA2 Channel3 global flag.
* DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
* DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
* DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
* DMA2_IT_GL4 - DMA2 Channel4 global flag.
* DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
* DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
* DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
* DMA2_IT_GL5 - DMA2 Channel5 global flag.
* DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
* DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
* DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
* DMA2_IT_GL6 - DMA2 Channel6 global flag.
* DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag.
* DMA2_IT_HT6 - DMA2 Channel6 half transfer flag.
* DMA2_IT_TE6 - DMA2 Channel6 transfer error flag.
* DMA2_IT_GL7 - DMA2 Channel7 global flag.
* DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag.
* DMA2_IT_HT7 - DMA2 Channel7 half transfer flag.
* DMA2_IT_TE7 - DMA2 Channel7 transfer error flag.
* DMA2_IT_GL8 - DMA2 Channel8 global flag.
* DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag.
* DMA2_IT_HT8 - DMA2 Channel8 half transfer flag.
* DMA2_IT_TE8 - DMA2 Channel8 transfer error flag.
* DMA2_IT_GL9 - DMA2 Channel9 global flag.
* DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag.
* DMA2_IT_HT9 - DMA2 Channel9 half transfer flag.
* DMA2_IT_TE9 - DMA2 Channel9 transfer error flag.
* DMA2_IT_GL10 - DMA2 Channel10 global flag.
* DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag.
* DMA2_IT_HT10 - DMA2 Channel10 half transfer flag.
* DMA2_IT_TE10 - DMA2 Channel10 transfer error flag.
* DMA2_IT_GL11 - DMA2 Channel11 global flag.
* DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag.
* DMA2_IT_HT11 - DMA2 Channel11 half transfer flag.
* DMA2_IT_TE11 - DMA2 Channel11 transfer error flag.
*
* @return The new state of DMAy_IT (SET or RESET).
*/
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpreg = 0;
if((DMAy_IT & FLAG_Mask) == FLAG_Mask)
{
tmpreg = DMA2->INTFR;
}
else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
{
tmpreg = DMA2_EXTEN->INTFR;
}
else
{
tmpreg = DMA1->INTFR;
}
if((tmpreg & DMAy_IT) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn DMA_ClearITPendingBit
*
* @brief Clears the DMAy Channelx's interrupt pending bits.
*
* @param DMAy_IT - specifies the DMAy interrupt source to check.
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
* DMA2_IT_GL2 - DMA2 Channel2 global flag.
* DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
* DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
* DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
* DMA2_IT_GL3 - DMA2 Channel3 global flag.
* DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
* DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
* DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
* DMA2_IT_GL4 - DMA2 Channel4 global flag.
* DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
* DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
* DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
* DMA2_IT_GL5 - DMA2 Channel5 global flag.
* DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
* DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
* DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
* DMA2_IT_GL6 - DMA2 Channel6 global flag.
* DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag.
* DMA2_IT_HT6 - DMA2 Channel6 half transfer flag.
* DMA2_IT_TE6 - DMA2 Channel6 transfer error flag.
* DMA2_IT_GL7 - DMA2 Channel7 global flag.
* DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag.
* DMA2_IT_HT7 - DMA2 Channel7 half transfer flag.
* DMA2_IT_TE7 - DMA2 Channel7 transfer error flag.
* DMA2_IT_GL8 - DMA2 Channel8 global flag.
* DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag.
* DMA2_IT_HT8 - DMA2 Channel8 half transfer flag.
* DMA2_IT_TE8 - DMA2 Channel8 transfer error flag.
* DMA2_IT_GL9 - DMA2 Channel9 global flag.
* DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag.
* DMA2_IT_HT9 - DMA2 Channel9 half transfer flag.
* DMA2_IT_TE9 - DMA2 Channel9 transfer error flag.
* DMA2_IT_GL10 - DMA2 Channel10 global flag.
* DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag.
* DMA2_IT_HT10 - DMA2 Channel10 half transfer flag.
* DMA2_IT_TE10 - DMA2 Channel10 transfer error flag.
* DMA2_IT_GL11 - DMA2 Channel11 global flag.
* DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag.
* DMA2_IT_HT11 - DMA2 Channel11 half transfer flag.
* DMA2_IT_TE11 - DMA2 Channel11 transfer error flag.
*
* @return none
*/
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
{
if((DMAy_IT & FLAG_Mask) == FLAG_Mask)
{
DMA2->INTFCR = DMAy_IT;
}
else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
{
DMA2_EXTEN->INTFCR = DMAy_IT;
}
else
{
DMA1->INTFCR = DMAy_IT;
}
}

268
libraries/sdk/Peripheral/ch32v30x_dma.h Normal file
View File

@@ -0,0 +1,268 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_dma.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* DMA firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_DMA_H
#define __CH32V30x_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* DMA Init structure definition */
typedef struct
{
uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */
uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination.
This parameter can be a value of @ref DMA_data_transfer_direction */
uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel.
The data unit is equal to the configuration set in DMA_PeripheralDataSize
or DMA_MemoryDataSize members depending in the transfer direction. */
uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not.
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not.
This parameter can be a value of @ref DMA_memory_incremented_mode */
uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_peripheral_data_size */
uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width.
This parameter can be a value of @ref DMA_memory_data_size */
uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_circular_normal_mode.
@note: The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_priority_level */
uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
This parameter can be a value of @ref DMA_memory_to_memory */
}DMA_InitTypeDef;
/* DMA_data_transfer_direction */
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
/* DMA_peripheral_incremented_mode */
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
/* DMA_memory_incremented_mode */
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
/* DMA_peripheral_data_size */
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
/* DMA_memory_data_size */
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
/* DMA_circular_normal_mode */
#define DMA_Mode_Circular ((uint32_t)0x00000020)
#define DMA_Mode_Normal ((uint32_t)0x00000000)
/* DMA_priority_level */
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define DMA_Priority_High ((uint32_t)0x00002000)
#define DMA_Priority_Medium ((uint32_t)0x00001000)
#define DMA_Priority_Low ((uint32_t)0x00000000)
/* DMA_memory_to_memory */
#define DMA_M2M_Enable ((uint32_t)0x00004000)
#define DMA_M2M_Disable ((uint32_t)0x00000000)
/* DMA_interrupts_definition */
#define DMA_IT_TC ((uint32_t)0x00000002)
#define DMA_IT_HT ((uint32_t)0x00000004)
#define DMA_IT_TE ((uint32_t)0x00000008)
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
#define DMA2_IT_GL6 ((uint32_t)0x10100000)
#define DMA2_IT_TC6 ((uint32_t)0x10200000)
#define DMA2_IT_HT6 ((uint32_t)0x10400000)
#define DMA2_IT_TE6 ((uint32_t)0x10800000)
#define DMA2_IT_GL7 ((uint32_t)0x11000000)
#define DMA2_IT_TC7 ((uint32_t)0x12000000)
#define DMA2_IT_HT7 ((uint32_t)0x14000000)
#define DMA2_IT_TE7 ((uint32_t)0x18000000)
#define DMA2_IT_GL8 ((uint32_t)0x20000001)
#define DMA2_IT_TC8 ((uint32_t)0x20000002)
#define DMA2_IT_HT8 ((uint32_t)0x20000004)
#define DMA2_IT_TE8 ((uint32_t)0x20000008)
#define DMA2_IT_GL9 ((uint32_t)0x20000010)
#define DMA2_IT_TC9 ((uint32_t)0x20000020)
#define DMA2_IT_HT9 ((uint32_t)0x20000040)
#define DMA2_IT_TE9 ((uint32_t)0x20000080)
#define DMA2_IT_GL10 ((uint32_t)0x20000100)
#define DMA2_IT_TC10 ((uint32_t)0x20000200)
#define DMA2_IT_HT10 ((uint32_t)0x20000400)
#define DMA2_IT_TE10 ((uint32_t)0x20000800)
#define DMA2_IT_GL11 ((uint32_t)0x20001000)
#define DMA2_IT_TC11 ((uint32_t)0x20002000)
#define DMA2_IT_HT11 ((uint32_t)0x20004000)
#define DMA2_IT_TE11 ((uint32_t)0x20008000)
/* DMA_flags_definition */
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
#define DMA2_FLAG_GL6 ((uint32_t)0x10100000)
#define DMA2_FLAG_TC6 ((uint32_t)0x10200000)
#define DMA2_FLAG_HT6 ((uint32_t)0x10400000)
#define DMA2_FLAG_TE6 ((uint32_t)0x10800000)
#define DMA2_FLAG_GL7 ((uint32_t)0x11000000)
#define DMA2_FLAG_TC7 ((uint32_t)0x12000000)
#define DMA2_FLAG_HT7 ((uint32_t)0x14000000)
#define DMA2_FLAG_TE7 ((uint32_t)0x18000000)
#define DMA2_FLAG_GL8 ((uint32_t)0x20000001)
#define DMA2_FLAG_TC8 ((uint32_t)0x20000002)
#define DMA2_FLAG_HT8 ((uint32_t)0x20000004)
#define DMA2_FLAG_TE8 ((uint32_t)0x20000008)
#define DMA2_FLAG_GL9 ((uint32_t)0x20000010)
#define DMA2_FLAG_TC9 ((uint32_t)0x20000020)
#define DMA2_FLAG_HT9 ((uint32_t)0x20000040)
#define DMA2_FLAG_TE9 ((uint32_t)0x20000080)
#define DMA2_FLAG_GL10 ((uint32_t)0x20000100)
#define DMA2_FLAG_TC10 ((uint32_t)0x20000200)
#define DMA2_FLAG_HT10 ((uint32_t)0x20000400)
#define DMA2_FLAG_TE10 ((uint32_t)0x20000800)
#define DMA2_FLAG_GL11 ((uint32_t)0x20001000)
#define DMA2_FLAG_TC11 ((uint32_t)0x20002000)
#define DMA2_FLAG_HT11 ((uint32_t)0x20004000)
#define DMA2_FLAG_TE11 ((uint32_t)0x20008000)
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
void DMA_ClearFlag(uint32_t DMAy_FLAG);
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
#ifdef __cplusplus
}
#endif
#endif

133
libraries/sdk/Peripheral/ch32v30x_dvp.c Normal file
View File

@@ -0,0 +1,133 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_dvp.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the DVP firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v30x_dvp.h"
/*********************************************************************
* @fn DVP_INTCfg
*
* @brief DVP interrupt configuration
*
* @param s - interrupt enable
* ENABLE
* DISABLE
* i - interrupt type
* RB_DVP_IE_STP_FRM
* RB_DVP_IE_FIFO_OV
* RB_DVP_IE_FRM_DONE
* RB_DVP_IE_ROW_DONE
* RB_DVP_IE_STR_FRM
*
* @return none
*/
void DVP_INTCfg(uint8_t s, uint8_t i)
{
if(s)
{
DVP->IER |= i;
}
else
{
DVP->IER &= ~i;
}
}
/*********************************************************************
* @fn DVP_Mode
*
* @brief DVP mode
*
* @param s - data bit width
* RB_DVP_D8_MOD
* RB_DVP_D10_MOD
* RB_DVP_D12_MOD
* i - interrupt type
* Video_Mode
* JPEG_Mode
*
* @return none
*/
void DVP_Mode(uint8_t s, DVP_Data_ModeTypeDef i)
{
DVP->CR0 &= ~RB_DVP_MSK_DAT_MOD;
if(s)
{
DVP->CR0 |= s;
}
else
{
DVP->CR0 &= ~(3 << 4);
}
if(i)
{
DVP->CR0 |= RB_DVP_JPEG;
}
else
{
DVP->CR0 &= ~RB_DVP_JPEG;
}
}
/*********************************************************************
* @fn DVP_Cfg
*
* @brief DVP configuration
*
* @param s - DMA enable control
* DVP_DMA_Enable
* DVP_DMA_Disable
* i - DVP all clear
* DVP_FLAG_FIFO_RESET_Enable
* DVP_FLAG_FIFO_RESET_Disable
* j - receive reset enable
* DVP_RX_RESET_Enable
* DVP_RX_RESET_Disable
*
* @return none
*/
void DVP_Cfg(DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j)
{
switch(s)
{
case DVP_DMA_Enable:
DVP->CR1 |= RB_DVP_DMA_EN;
break;
case DVP_DMA_Disable:
DVP->CR1 &= ~RB_DVP_DMA_EN;
break;
default:
break;
}
switch(i)
{
case DVP_RX_RESET_Enable:
DVP->CR1 |= RB_DVP_ALL_CLR;
break;
case DVP_RX_RESET_Disable:
DVP->CR1 &= ~RB_DVP_ALL_CLR;
break;
default:
break;
}
switch(j)
{
case DVP_RX_RESET_Enable:
DVP->CR1 |= RB_DVP_RCV_CLR;
break;
case DVP_RX_RESET_Disable:
DVP->CR1 &= ~RB_DVP_RCV_CLR;
break;
default:
break;
}
}

67
libraries/sdk/Peripheral/ch32v30x_dvp.h Normal file
View File

@@ -0,0 +1,67 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_dvp.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* DVP firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_DVP_H
#define __CH32V30x_DVP_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* DVP Data Mode */
typedef enum
{
Video_Mode = 0,
JPEG_Mode,
}DVP_Data_ModeTypeDef;
/* DVP DMA */
typedef enum
{
DVP_DMA_Disable = 0,
DVP_DMA_Enable,
}DVP_DMATypeDef;
/* DVP FLAG and FIFO Reset */
typedef enum
{
DVP_FLAG_FIFO_RESET_Disable = 0,
DVP_FLAG_FIFO_RESET_Enable,
}DVP_FLAG_FIFO_RESETTypeDef;
/* DVP RX Reset */
typedef enum
{
DVP_RX_RESET_Disable = 0,
DVP_RX_RESET_Enable,
}DVP_RX_RESETTypeDef;
void DVP_INTCfg( uint8_t s, uint8_t i );
void DVP_Mode( uint8_t s, DVP_Data_ModeTypeDef i);
void DVP_Cfg( DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j);
#ifdef __cplusplus
}
#endif
#endif

2522
libraries/sdk/Peripheral/ch32v30x_eth.c Normal file
View File

File diff suppressed because it is too large Load Diff

1332
libraries/sdk/Peripheral/ch32v30x_eth.h Normal file
View File

File diff suppressed because it is too large Load Diff

180
libraries/sdk/Peripheral/ch32v30x_exti.c Normal file
View File

@@ -0,0 +1,180 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_exti.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the EXTI firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
***************************************************************************************/
#include "ch32v30x_exti.h"
/* No interrupt selected */
#define EXTI_LINENONE ((uint32_t)0x00000)
/*********************************************************************
* @fn EXTI_DeInit
*
* @brief Deinitializes the EXTI peripheral registers to their default
* reset values.
*
* @return none.
*/
void EXTI_DeInit(void)
{
EXTI->INTENR = 0x00000000;
EXTI->EVENR = 0x00000000;
EXTI->RTENR = 0x00000000;
EXTI->FTENR = 0x00000000;
EXTI->INTFR = 0x000FFFFF;
}
/*********************************************************************
* @fn EXTI_Init
*
* @brief Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
*
* @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
*
* @return none.
*/
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
{
uint32_t tmp = 0;
tmp = (uint32_t)EXTI_BASE;
if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{
EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
{
EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
}
else
{
tmp = (uint32_t)EXTI_BASE;
tmp += EXTI_InitStruct->EXTI_Trigger;
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
}
}
else
{
tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
}
}
/*********************************************************************
* @fn EXTI_StructInit
*
* @brief Fills each EXTI_InitStruct member with its reset value.
*
* @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
*
* @return none.
*/
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
}
/*********************************************************************
* @fn EXTI_GenerateSWInterrupt
*
* @brief Generates a Software interrupt.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return none.
*/
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
{
EXTI->SWIEVR |= EXTI_Line;
}
/*********************************************************************
* @fn EXTI_GetFlagStatus
*
* @brief Checks whether the specified EXTI line flag is set or not.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return The new state of EXTI_Line (SET or RESET).
*/
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
{
FlagStatus bitstatus = RESET;
if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn EXTI_ClearFlag
*
* @brief Clears the EXTI's line pending flags.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return None
*/
void EXTI_ClearFlag(uint32_t EXTI_Line)
{
EXTI->INTFR = EXTI_Line;
}
/*********************************************************************
* @fn EXTI_GetITStatus
*
* @brief Checks whether the specified EXTI line is asserted or not.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return The new state of EXTI_Line (SET or RESET).
*/
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
enablestatus = EXTI->INTENR & EXTI_Line;
if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn EXTI_ClearITPendingBit
*
* @brief Clears the EXTI's line pending bits.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return none
*/
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
{
EXTI->INTFR = EXTI_Line;
}

90
libraries/sdk/Peripheral/ch32v30x_exti.h Normal file
View File

@@ -0,0 +1,90 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_exti.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* EXTI firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_EXTI_H
#define __CH32V30x_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* EXTI mode enumeration */
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
}EXTIMode_TypeDef;
/* EXTI Trigger enumeration */
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
}EXTITrigger_TypeDef;
/* EXTI Init Structure definition */
typedef struct
{
uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled.
This parameter can be any combination of @ref EXTI_Lines */
EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
}EXTI_InitTypeDef;
/* EXTI_Lines */
#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */
#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */
#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */
#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */
#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */
#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */
#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */
#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */
#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */
#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */
#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */
#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */
#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */
#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */
#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */
#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */
#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */
#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */
#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD/USBFS OTG
Wakeup from suspend event */
#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */
#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBHS Wakeup event */
void EXTI_DeInit(void);
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
void EXTI_ClearFlag(uint32_t EXTI_Line);
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
#ifdef __cplusplus
}
#endif
#endif

981
libraries/sdk/Peripheral/ch32v30x_flash.c Normal file
View File

@@ -0,0 +1,981 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_flash.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the FLASH firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
***************************************************************************************/
#include "ch32v30x_flash.h"
/* Flash Control Register bits */
#define CR_PG_Set ((uint32_t)0x00000001)
#define CR_PG_Reset ((uint32_t)0xFFFFFFFE)
#define CR_PER_Set ((uint32_t)0x00000002)
#define CR_PER_Reset ((uint32_t)0xFFFFFFFD)
#define CR_MER_Set ((uint32_t)0x00000004)
#define CR_MER_Reset ((uint32_t)0xFFFFFFFB)
#define CR_OPTPG_Set ((uint32_t)0x00000010)
#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF)
#define CR_OPTER_Set ((uint32_t)0x00000020)
#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF)
#define CR_STRT_Set ((uint32_t)0x00000040)
#define CR_LOCK_Set ((uint32_t)0x00000080)
#define CR_FAST_LOCK_Set ((uint32_t)0x00008000)
#define CR_PAGE_PG ((uint32_t)0x00010000)
#define CR_PAGE_ER ((uint32_t)0x00020000)
#define CR_BER32 ((uint32_t)0x00040000)
#define CR_BER64 ((uint32_t)0x00080000)
#define CR_PG_STRT ((uint32_t)0x00200000)
/* FLASH Status Register bits */
#define SR_BSY ((uint32_t)0x00000001)
#define SR_WR_BSY ((uint32_t)0x00000002)
#define SR_WRPRTERR ((uint32_t)0x00000010)
#define SR_EOP ((uint32_t)0x00000020)
/* FLASH Mask */
#define RDPRT_Mask ((uint32_t)0x00000002)
#define WRP0_Mask ((uint32_t)0x000000FF)
#define WRP1_Mask ((uint32_t)0x0000FF00)
#define WRP2_Mask ((uint32_t)0x00FF0000)
#define WRP3_Mask ((uint32_t)0xFF000000)
#define OB_USER_BFB2 ((uint16_t)0x0008)
/* FLASH Keys */
#define RDP_Key ((uint16_t)0x00A5)
#define FLASH_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
/* FLASH BANK address */
#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
/* Delay definition */
#define EraseTimeout ((uint32_t)0x000B0000)
#define ProgramTimeout ((uint32_t)0x00005000)
/*********************************************************************
* @fn FLASH_Unlock
*
* @brief Unlocks the FLASH Program Erase Controller.
*
* @return none
*/
void FLASH_Unlock(void)
{
/* Authorize the FPEC of Bank1 Access */
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
}
/*********************************************************************
* @fn FLASH_UnlockBank1
*
* @brief Unlocks the FLASH Bank1 Program Erase Controller.
* equivalent to FLASH_Unlock function.
*
* @return none
*/
void FLASH_UnlockBank1(void)
{
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
}
/*********************************************************************
* @fn FLASH_Lock
*
* @brief Locks the FLASH Program Erase Controller.
*
* @return none
*/
void FLASH_Lock(void)
{
FLASH->CTLR |= CR_LOCK_Set;
}
/*********************************************************************
* @fn FLASH_LockBank1
*
* @brief Locks the FLASH Bank1 Program Erase Controller.
*
* @return none
*/
void FLASH_LockBank1(void)
{
FLASH->CTLR |= CR_LOCK_Set;
}
/*********************************************************************
* @fn FLASH_ErasePage
*
* @brief Erases a specified FLASH page(page size 4KB).
*
* @param Page_Address - The page address to be erased.
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
{
FLASH_Status status = FLASH_COMPLETE;
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR |= CR_PER_Set;
FLASH->ADDR = Page_Address;
FLASH->CTLR |= CR_STRT_Set;
status = FLASH_WaitForLastOperation(EraseTimeout);
FLASH->CTLR &= CR_PER_Reset;
}
return status;
}
/*********************************************************************
* @fn FLASH_EraseAllPages
*
* @brief Erases all FLASH pages.
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EraseAllPages(void)
{
FLASH_Status status = FLASH_COMPLETE;
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR |= CR_MER_Set;
FLASH->CTLR |= CR_STRT_Set;
status = FLASH_WaitForLastOperation(EraseTimeout);
FLASH->CTLR &= CR_MER_Reset;
}
return status;
}
/*********************************************************************
* @fn FLASH_EraseAllBank1Pages
*
* @brief Erases all Bank1 FLASH pages.
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EraseAllBank1Pages(void)
{
FLASH_Status status = FLASH_COMPLETE;
status = FLASH_WaitForLastBank1Operation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR |= CR_MER_Set;
FLASH->CTLR |= CR_STRT_Set;
status = FLASH_WaitForLastBank1Operation(EraseTimeout);
FLASH->CTLR &= CR_MER_Reset;
}
return status;
}
/*********************************************************************
* @fn FLASH_EraseOptionBytes
*
* @brief Erases the FLASH option bytes.
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EraseOptionBytes(void)
{
uint16_t rdptmp = RDP_Key;
uint32_t Address = 0x1FFFF800;
__IO uint8_t i;
FLASH_Status status = FLASH_COMPLETE;
if(FLASH_GetReadOutProtectionStatus() != RESET)
{
rdptmp = 0x00;
}
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->OBKEYR = FLASH_KEY1;
FLASH->OBKEYR = FLASH_KEY2;
FLASH->CTLR |= CR_OPTER_Set;
FLASH->CTLR |= CR_STRT_Set;
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR &= CR_OPTER_Reset;
FLASH->CTLR |= CR_OPTPG_Set;
OB->RDPR = (uint16_t)rdptmp;
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_TIMEOUT)
{
FLASH->CTLR &= CR_OPTPG_Reset;
}
}
else
{
if(status != FLASH_TIMEOUT)
{
FLASH->CTLR &= CR_OPTPG_Reset;
}
}
/* Write 0xFF */
FLASH->CTLR |= CR_OPTPG_Set;
for(i = 0; i < 8; i++)
{
*(uint16_t *)(Address + 2 * i) = 0x00FF;
while(FLASH->STATR & SR_BSY)
;
}
FLASH->CTLR &= ~CR_OPTPG_Set;
}
return status;
}
/*********************************************************************
* @fn FLASH_ProgramWord
*
* @brief Programs a word at a specified address.
*
* @param Address - specifies the address to be programmed.
* Data - specifies the data to be programmed.
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
{
FLASH_Status status = FLASH_COMPLETE;
__IO uint32_t tmp = 0;
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR |= CR_PG_Set;
*(__IO uint16_t *)Address = (uint16_t)Data;
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
tmp = Address + 2;
*(__IO uint16_t *)tmp = Data >> 16;
status = FLASH_WaitForLastOperation(ProgramTimeout);
FLASH->CTLR &= CR_PG_Reset;
}
else
{
FLASH->CTLR &= CR_PG_Reset;
}
}
return status;
}
/*********************************************************************
* @fn FLASH_ProgramHalfWord
*
* @brief Programs a half word at a specified address.
*
* @param Address - specifies the address to be programmed.
* Data - specifies the data to be programmed.
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
{
FLASH_Status status = FLASH_COMPLETE;
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR |= CR_PG_Set;
*(__IO uint16_t *)Address = Data;
status = FLASH_WaitForLastOperation(ProgramTimeout);
FLASH->CTLR &= CR_PG_Reset;
}
return status;
}
/*********************************************************************
* @fn FLASH_ProgramOptionByteData
*
* @brief Programs a half word at a specified Option Byte Data address.
*
* @param Address - specifies the address to be programmed.
* Data - specifies the data to be programmed.
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
{
FLASH_Status status = FLASH_COMPLETE;
uint32_t Addr = 0x1FFFF800;
__IO uint8_t i;
uint16_t pbuf[8];
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->OBKEYR = FLASH_KEY1;
FLASH->OBKEYR = FLASH_KEY2;
/* Read optionbytes */
for(i = 0; i < 8; i++)
{
pbuf[i] = *(uint16_t *)(Addr + 2 * i);
}
/* Erase optionbytes */
FLASH->CTLR |= CR_OPTER_Set;
FLASH->CTLR |= CR_STRT_Set;
while(FLASH->STATR & SR_BSY)
;
FLASH->CTLR &= ~CR_OPTER_Set;
/* Write optionbytes */
pbuf[((Address - 0x1FFFF800) / 2)] = ((((uint16_t) ~(Data)) << 8) | ((uint16_t)Data));
FLASH->CTLR |= CR_OPTPG_Set;
for(i = 0; i < 8; i++)
{
*(uint16_t *)(Addr + 2 * i) = pbuf[i];
while(FLASH->STATR & SR_BSY)
;
}
FLASH->CTLR &= ~CR_OPTPG_Set;
}
return status;
}
/*********************************************************************
* @fn FLASH_EnableWriteProtection
*
* @brief Write protects the desired sectors
*
* @param FLASH_Sectors - specifies the address of the pages to be write protected.
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors)
{
uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
FLASH_Status status = FLASH_COMPLETE;
uint32_t Addr = 0x1FFFF800;
__IO uint8_t i;
uint16_t pbuf[8];
FLASH_Sectors = (uint32_t)(~FLASH_Sectors);
WRP0_Data = (uint16_t)(FLASH_Sectors & WRP0_Mask);
WRP1_Data = (uint16_t)((FLASH_Sectors & WRP1_Mask) >> 8);
WRP2_Data = (uint16_t)((FLASH_Sectors & WRP2_Mask) >> 16);
WRP3_Data = (uint16_t)((FLASH_Sectors & WRP3_Mask) >> 24);
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->OBKEYR = FLASH_KEY1;
FLASH->OBKEYR = FLASH_KEY2;
/* Read optionbytes */
for(i = 0; i < 8; i++)
{
pbuf[i] = *(uint16_t *)(Addr + 2 * i);
}
/* Erase optionbytes */
FLASH->CTLR |= CR_OPTER_Set;
FLASH->CTLR |= CR_STRT_Set;
while(FLASH->STATR & SR_BSY)
;
FLASH->CTLR &= ~CR_OPTER_Set;
/* Write optionbytes */
pbuf[4] = WRP0_Data;
pbuf[5] = WRP1_Data;
pbuf[6] = WRP2_Data;
pbuf[7] = WRP3_Data;
FLASH->CTLR |= CR_OPTPG_Set;
for(i = 0; i < 8; i++)
{
*(uint16_t *)(Addr + 2 * i) = pbuf[i];
while(FLASH->STATR & SR_BSY)
;
}
FLASH->CTLR &= ~CR_OPTPG_Set;
}
return status;
}
/*********************************************************************
* @fn FLASH_ReadOutProtection
*
* @brief Enables or disables the read out protection.
*
* @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE).
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
{
FLASH_Status status = FLASH_COMPLETE;
uint32_t Addr = 0x1FFFF800;
__IO uint8_t i;
uint16_t pbuf[8];
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->OBKEYR = FLASH_KEY1;
FLASH->OBKEYR = FLASH_KEY2;
/* Read optionbytes */
for(i = 0; i < 8; i++)
{
pbuf[i] = *(uint16_t *)(Addr + 2 * i);
}
/* Erase optionbytes */
FLASH->CTLR |= CR_OPTER_Set;
FLASH->CTLR |= CR_STRT_Set;
while(FLASH->STATR & SR_BSY)
;
FLASH->CTLR &= ~CR_OPTER_Set;
/* Write optionbytes */
if(NewState == DISABLE)
pbuf[0] = 0x5AA5;
else
pbuf[0] = 0x00FF;
FLASH->CTLR |= CR_OPTPG_Set;
for(i = 0; i < 8; i++)
{
*(uint16_t *)(Addr + 2 * i) = pbuf[i];
while(FLASH->STATR & SR_BSY)
;
}
FLASH->CTLR &= ~CR_OPTPG_Set;
}
return status;
}
/*********************************************************************
* @fn FLASH_UserOptionByteConfig
*
* @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY.
*
* @param OB_IWDG - Selects the IWDG mode
* OB_IWDG_SW - Software IWDG selected
* OB_IWDG_HW - Hardware IWDG selected
* OB_STOP - Reset event when entering STOP mode.
* OB_STOP_NoRST - No reset generated when entering in STOP
* OB_STOP_RST - Reset generated when entering in STOP
* OB_STDBY - Reset event when entering Standby mode.
* OB_STDBY_NoRST - No reset generated when entering in STANDBY
* OB_STDBY_RST - Reset generated when entering in STANDBY
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
{
FLASH_Status status = FLASH_COMPLETE;
uint32_t Addr = 0x1FFFF800;
__IO uint8_t i;
uint16_t pbuf[8];
FLASH->OBKEYR = FLASH_KEY1;
FLASH->OBKEYR = FLASH_KEY2;
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* Read optionbytes */
for(i = 0; i < 8; i++)
{
pbuf[i] = *(uint16_t *)(Addr + 2 * i);
}
/* Erase optionbytes */
FLASH->CTLR |= CR_OPTER_Set;
FLASH->CTLR |= CR_STRT_Set;
while(FLASH->STATR & SR_BSY)
;
FLASH->CTLR &= ~CR_OPTER_Set;
/* Write optionbytes */
pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
FLASH->CTLR |= CR_OPTPG_Set;
for(i = 0; i < 8; i++)
{
*(uint16_t *)(Addr + 2 * i) = pbuf[i];
while(FLASH->STATR & SR_BSY)
;
}
FLASH->CTLR &= ~CR_OPTPG_Set;
}
return status;
}
/*********************************************************************
* @fn FLASH_GetUserOptionByte
*
* @brief Returns the FLASH User Option Bytes values.
*
* @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
* and RST_STDBY(Bit2).
*/
uint32_t FLASH_GetUserOptionByte(void)
{
return (uint32_t)(FLASH->OBR >> 2);
}
/*********************************************************************
* @fn FLASH_GetWriteProtectionOptionByte
*
* @brief Returns the FLASH Write Protection Option Bytes Register value.
*
* @return The FLASH Write Protection Option Bytes Register value.
*/
uint32_t FLASH_GetWriteProtectionOptionByte(void)
{
return (uint32_t)(FLASH->WPR);
}
/*********************************************************************
* @fn FLASH_GetReadOutProtectionStatus
*
* @brief Checks whether the FLASH Read Out Protection Status is set or not.
*
* @return FLASH ReadOut Protection Status(SET or RESET)
*/
FlagStatus FLASH_GetReadOutProtectionStatus(void)
{
FlagStatus readoutstatus = RESET;
if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
{
readoutstatus = SET;
}
else
{
readoutstatus = RESET;
}
return readoutstatus;
}
/*********************************************************************
* @fn FLASH_ITConfig
*
* @brief Enables or disables the specified FLASH interrupts.
*
* @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled.
* FLASH_IT_ERROR - FLASH Error Interrupt
* FLASH_IT_EOP - FLASH end of operation Interrupt
* NewState - new state of the specified Flash interrupts(ENABLE or DISABLE).
*
* @return FLASH Prefetch Buffer Status (SET or RESET).
*/
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
{
if(NewState != DISABLE)
{
FLASH->CTLR |= FLASH_IT;
}
else
{
FLASH->CTLR &= ~(uint32_t)FLASH_IT;
}
}
/*********************************************************************
* @fn FLASH_GetFlagStatus
*
* @brief Checks whether the specified FLASH flag is set or not.
*
* @param FLASH_FLAG - specifies the FLASH flag to check.
* FLASH_FLAG_BSY - FLASH Busy flag
* FLASH_FLAG_PGERR - FLASH Program error flag
* FLASH_FLAG_WRPRTERR - FLASH Write protected error flag
* FLASH_FLAG_EOP - FLASH End of Operation flag
* FLASH_FLAG_OPTERR - FLASH Option Byte error flag
*
* @return The new state of FLASH_FLAG (SET or RESET).
*/
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
{
FlagStatus bitstatus = RESET;
if(FLASH_FLAG == FLASH_FLAG_OPTERR)
{
if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
else
{
if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
return bitstatus;
}
/*********************************************************************
* @fn FLASH_ClearFlag
*
* @brief Clears the FLASH's pending flags.
*
* @param FLASH_FLAG - specifies the FLASH flags to clear.
* FLASH_FLAG_PGERR - FLASH Program error flag
* FLASH_FLAG_WRPRTERR - FLASH Write protected error flag
* FLASH_FLAG_EOP - FLASH End of Operation flag
*
* @return none
*/
void FLASH_ClearFlag(uint32_t FLASH_FLAG)
{
FLASH->STATR = FLASH_FLAG;
}
/*********************************************************************
* @fn FLASH_GetStatus
*
* @brief Returns the FLASH Status.
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP or FLASH_COMPLETE.
*/
FLASH_Status FLASH_GetStatus(void)
{
FLASH_Status flashstatus = FLASH_COMPLETE;
if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
{
flashstatus = FLASH_BUSY;
}
else
{
if((FLASH->STATR & FLASH_FLAG_PGERR) != 0)
{
flashstatus = FLASH_ERROR_PG;
}
else
{
if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0)
{
flashstatus = FLASH_ERROR_WRP;
}
else
{
flashstatus = FLASH_COMPLETE;
}
}
}
return flashstatus;
}
/*********************************************************************
* @fn FLASH_GetBank1Status
*
* @brief Returns the FLASH Bank1 Status.
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP or FLASH_COMPLETE.
*/
FLASH_Status FLASH_GetBank1Status(void)
{
FLASH_Status flashstatus = FLASH_COMPLETE;
if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY)
{
flashstatus = FLASH_BUSY;
}
else
{
if((FLASH->STATR & FLASH_FLAG_BANK1_PGERR) != 0)
{
flashstatus = FLASH_ERROR_PG;
}
else
{
if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0)
{
flashstatus = FLASH_ERROR_WRP;
}
else
{
flashstatus = FLASH_COMPLETE;
}
}
}
return flashstatus;
}
/*********************************************************************
* @fn FLASH_WaitForLastOperation
*
* @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
*
* @param Timeout - FLASH programming Timeout
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP or FLASH_COMPLETE.
*/
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
{
FLASH_Status status = FLASH_COMPLETE;
status = FLASH_GetBank1Status();
while((status == FLASH_BUSY) && (Timeout != 0x00))
{
status = FLASH_GetBank1Status();
Timeout--;
}
if(Timeout == 0x00)
{
status = FLASH_TIMEOUT;
}
return status;
}
/*********************************************************************
* @fn FLASH_WaitForLastBank1Operation
*
* @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
*
* @param Timeout - FLASH programming Timeout
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP or FLASH_COMPLETE.
*/
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
{
FLASH_Status status = FLASH_COMPLETE;
status = FLASH_GetBank1Status();
while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
{
status = FLASH_GetBank1Status();
Timeout--;
}
if(Timeout == 0x00)
{
status = FLASH_TIMEOUT;
}
return status;
}
/*********************************************************************
* @fn FLASH_Unlock_Fast
*
* @brief Unlocks the Fast Program Erase Mode.
*
* @return none
*/
void FLASH_Unlock_Fast(void)
{
/* Authorize the FPEC of Bank1 Access */
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
/* Fast program mode unlock */
FLASH->MODEKEYR = FLASH_KEY1;
FLASH->MODEKEYR = FLASH_KEY2;
}
/*********************************************************************
* @fn FLASH_Lock_Fast
*
* @brief Locks the Fast Program Erase Mode.
*
* @return none
*/
void FLASH_Lock_Fast(void)
{
FLASH->CTLR |= CR_LOCK_Set;
}
/*********************************************************************
* @fn FLASH_ErasePage_Fast
*
* @brief Erases a specified FLASH page (1page = 256Byte).
*
* @param Page_Address - The page address to be erased.
*
* @return none
*/
void FLASH_ErasePage_Fast(uint32_t Page_Address)
{
Page_Address &= 0xFFFFFF00;
FLASH->CTLR |= CR_PAGE_ER;
FLASH->ADDR = Page_Address;
FLASH->CTLR |= CR_STRT_Set;
while(FLASH->STATR & SR_BSY)
;
FLASH->CTLR &= ~CR_PAGE_ER;
}
/*********************************************************************
* @fn FLASH_EraseBlock_32K_Fast
*
* @brief Erases a specified FLASH Block (1Block = 32KByte).
*
* @param Block_Address - The block address to be erased.
*
* @return none
*/
void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address)
{
Block_Address &= 0xFFFF8000;
FLASH->CTLR |= CR_BER32;
FLASH->ADDR = Block_Address;
FLASH->CTLR |= CR_STRT_Set;
while(FLASH->STATR & SR_BSY)
;
FLASH->CTLR &= ~CR_BER32;
}
/*********************************************************************
* @fn FLASH_EraseBlock_64K_Fast
*
* @brief Erases a specified FLASH Block (1Block = 64KByte).
*
* @param Block_Address - The block address to be erased.
*
* @return none
*/
void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address)
{
Block_Address &= 0xFFFF0000;
FLASH->CTLR |= CR_BER64;
FLASH->ADDR = Block_Address;
FLASH->CTLR |= CR_STRT_Set;
while(FLASH->STATR & SR_BSY)
;
FLASH->CTLR &= ~CR_BER64;
}
/*********************************************************************
* @fn FLASH_ProgramPage_Fast
*
* @brief Program a specified FLASH page (1page = 256Byte).
*
* @param Page_Address - The page address to be programed.
*
* @return none
*/
void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf)
{
uint8_t size = 64;
Page_Address &= 0xFFFFFF00;
FLASH->CTLR |= CR_PAGE_PG;
while(FLASH->STATR & SR_BSY)
;
while(FLASH->STATR & SR_WR_BSY)
;
while(size)
{
*(uint32_t *)Page_Address = *(uint32_t *)pbuf;
Page_Address += 4;
pbuf += 1;
size -= 1;
while(FLASH->STATR & SR_WR_BSY)
;
}
FLASH->CTLR |= CR_PG_STRT;
while(FLASH->STATR & SR_BSY)
;
FLASH->CTLR &= ~CR_PAGE_PG;
}
/*********************************************************************
* @fn FLASH_Access_Clock_Cfg
*
* @brief Config FLASH Access Clock(Need to unlock )
*
* @param FLASH_Access_CLK -
* FLASH_Access_SYSTEM_HALF - System clock/2
* FLASH_Access_SYSTEM - System clock
*
* @return none
*/
void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK)
{
FLASH->CTLR &= ~(1 << 25);
FLASH->CTLR |= FLASH_Access_CLK;
}
/*********************************************************************
* @fn FLASH_Enhance_Mode
*
* @brief Read FLASH Enhance Mode
*
* @param
* Newstate - new state of the ReadOut Protection(ENABLE or DISABLE).
*
* @return none
*/
void FLASH_Enhance_Mode(FunctionalState NewState)
{
if(NewState)
{
FLASH->CTLR |= (1 << 24);
}
else
{
FLASH->CTLR &= ~(1 << 24);
FLASH->CTLR |= (1 << 22);
}
}

144
libraries/sdk/Peripheral/ch32v30x_flash.h Normal file
View File

@@ -0,0 +1,144 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_flash.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the FLASH
* firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_FLASH_H
#define __CH32V30x_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* FLASH Status */
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_PG,
FLASH_ERROR_WRP,
FLASH_COMPLETE,
FLASH_TIMEOUT
}FLASH_Status;
/* Write Protect */
#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */
#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */
/* Option_Bytes_IWatchdog */
#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
/* Option_Bytes_nRST_STOP */
#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */
#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */
/* Option_Bytes_nRST_STDBY */
#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
/* FLASH_Interrupts */
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */
/* FLASH_Flags */
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /* FLASH BANK1 Program error flag */
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
/* FLASH_Access_CLK */
#define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Access Clock = SYSTEM/2 */
#define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* FLASH Access Clock = SYSTEM */
/*Functions used for all devices*/
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_EraseOptionBytes(void);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors);
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
uint32_t FLASH_GetUserOptionByte(void);
uint32_t FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void);
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
void FLASH_Unlock_Fast(void);
void FLASH_Lock_Fast(void);
void FLASH_ErasePage_Fast(uint32_t Page_Address);
void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address);
void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address);
void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t* pbuf);
void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK);
void FLASH_Enhance_Mode(FunctionalState NewState);
/* New function used for all devices */
void FLASH_UnlockBank1(void);
void FLASH_LockBank1(void);
FLASH_Status FLASH_EraseAllBank1Pages(void);
FLASH_Status FLASH_GetBank1Status(void);
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
#ifdef __cplusplus
}
#endif
#endif

501
libraries/sdk/Peripheral/ch32v30x_fsmc.c Normal file
View File

@@ -0,0 +1,501 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_fsmc.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the FSMC firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v30x_fsmc.h"
#include "ch32v30x_rcc.h"
/* FSMC BCRx Mask */
#define BCR_MBKEN_Set ((uint32_t)0x00000001)
#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
#define BCR_FACCEN_Set ((uint32_t)0x00000040)
/* FSMC PCRx Mask */
#define PCR_PBKEN_Set ((uint32_t)0x00000004)
#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
#define PCR_ECCEN_Set ((uint32_t)0x00000040)
#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
/*********************************************************************
* @fn FSMC_NORSRAMDeInit
*
* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
* reset values.
*
* @param FSMC_Bank-
* FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1.
*
* @return none
*/
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
{
if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
{
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
}
else
{
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
}
FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
}
/*********************************************************************
* @fn FSMC_NANDDeInit
*
* @brief Deinitializes the FSMC NAND Banks registers to their default
* reset values.
*
* @param FSMC_Bank -
* FSMC_Bank2_NAND - FSMC Bank2 NAND.
*
* @return none
*/
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
{
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 = 0x00000018;
FSMC_Bank2->SR2 = 0x00000040;
FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
FSMC_Bank2->PATT2 = 0xFCFCFCFC;
}
}
/*********************************************************************
* @fn FSMC_NORSRAMInit
*
* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
* parameters in the FSMC_NORSRAMInitStruct.
*
* @param SMC_NORSRAMInitStruct:pointer to a FSMC_NORSRAMInitTypeDef
* structure that contains the configuration information for the FSMC NOR/SRAM
* specified Banks.
*
* @return none
*/
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
{
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
FSMC_NORSRAMInitStruct->FSMC_WrapMode |
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
{
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
}
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank + 1] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
{
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
}
else
{
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
}
}
/*********************************************************************
* @fn FSMC_NANDInit
*
* @brief Initializes the FSMC NAND Banks according to the specified
* parameters in the FSMC_NANDInitStruct.
*
* @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef
* structure that contains the configuration information for the FSMC
* NAND specified Banks.
*
* @return none
*/
void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
{
uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
PCR_MemoryType_NAND |
FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
FSMC_NANDInitStruct->FSMC_ECC |
FSMC_NANDInitStruct->FSMC_ECCPageSize |
(FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9) |
(FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 = tmppcr;
FSMC_Bank2->PMEM2 = tmppmem;
FSMC_Bank2->PATT2 = tmppatt;
}
}
/*********************************************************************
* @fn FSMC_NORSRAMStructInit
*
* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
*
* @param FSMC_NORSRAMInitStruct - pointer to a FSMC_NORSRAMInitTypeDef
* structure which will be initialized.
*
* @return none
*/
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
{
FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
}
/*********************************************************************
* @fn FSMC_NANDStructInit
*
* @brief Fills each FSMC_NANDInitStruct member with its default value.
*
* @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef
* structure which will be initialized.
*
* @return none
*/
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
{
FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
}
/*********************************************************************
* @fn FSMC_NORSRAMCmd
*
* @brief Enables or disables the specified NOR/SRAM Memory Bank.
*
* @param FSMC_Bank - specifies the FSMC Bank to be used
* FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1
* FSMC_Bank1_NORSRAM2 - FSMC Bank1 NOR/SRAM2
* FSMC_Bank1_NORSRAM3 - FSMC Bank1 NOR/SRAM3
* FSMC_Bank1_NORSRAM4 - FSMC Bank1 NOR/SRAM4
* NewState<74><65>ENABLE or DISABLE.
*
* @return none
*/
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
{
if(NewState != DISABLE)
{
FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
}
else
{
FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
}
}
/*********************************************************************
* @fn FSMC_NANDCmd
*
* @brief Enables or disables the specified NAND Memory Bank.
*
* @param FSMC_Bank - specifies the FSMC Bank to be used
* FSMC_Bank2_NAND - FSMC Bank2 NAND
* FSMC_Bank3_NAND - FSMC Bank3 NAND
* NewStat - ENABLE or DISABLE.
*
* @return none
*/
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
{
if(NewState != DISABLE)
{
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
}
}
else
{
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
}
}
}
/*********************************************************************
* @fn FSMC_NANDECCCmd
*
* @brief Enables or disables the FSMC NAND ECC feature.
*
* @param FSMC_Bank - specifies the FSMC Bank to be used
* FSMC_Bank2_NAND - FSMC Bank2 NAND
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
{
if(NewState != DISABLE)
{
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
}
}
else
{
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
}
}
}
/*********************************************************************
* @fn FSMC_GetECC
*
* @brief Returns the error correction code register value.
*
* @param FSMC_Bank - specifies the FSMC Bank to be used
* FSMC_Bank2_NAND - FSMC Bank2 NAND
* NewState - ENABLE or DISABLE.
*
* @return eccval - The Error Correction Code (ECC) value.
*/
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
{
uint32_t eccval = 0x00000000;
if(FSMC_Bank == FSMC_Bank2_NAND)
{
eccval = FSMC_Bank2->ECCR2;
}
return (eccval);
}
/*********************************************************************
* @fn FSMC_ITConfig
*
* @brief Enables or disables the specified FSMC interrupts.
*
* @param FSMC_Bank - specifies the FSMC Bank to be used
* FSMC_Bank2_NAND - FSMC Bank2 NAND
* FSMC_IT - specifies the FSMC interrupt sources to be enabled or disabled.
* FSMC_IT_RisingEdge - Rising edge detection interrupt.
* FSMC_IT_Level - Level edge detection interrupt.
* FSMC_IT_FallingEdge - Falling edge detection interrupt.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
{
if(NewState != DISABLE)
{
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 |= FSMC_IT;
}
}
else
{
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
}
}
}
/*********************************************************************
* @fn FSMC_GetFlagStatus
*
* @brief Checks whether the specified FSMC flag is set or not.
*
* @param FSMC_Bank - specifies the FSMC Bank to be used
* FSMC_Bank2_NAND - FSMC Bank2 NAND
* FSMC_FLAG - specifies the flag to check.
* FSMC_FLAG_RisingEdge - Rising egde detection Flag.
* FSMC_FLAG_Level - Level detection Flag.
* FSMC_FLAG_FallingEdge - Falling egde detection Flag.
* FSMC_FLAG_FEMPT - Fifo empty Flag.
* NewState - ENABLE or DISABLE.
*
* @return FlagStatus - The new state of FSMC_FLAG (SET or RESET).
*/
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpsr = 0x00000000;
if(FSMC_Bank == FSMC_Bank2_NAND)
{
tmpsr = FSMC_Bank2->SR2;
}
if((tmpsr & FSMC_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn FSMC_ClearFlag
*
* @brief Clears the FSMC's pending flags.
*
* @param FSMC_Bank - specifies the FSMC Bank to be used
* FSMC_Bank2_NAND - FSMC Bank2 NAND
* FSMC_FLAG - specifies the flag to check.
* FSMC_FLAG_RisingEdge - Rising egde detection Flag.
* FSMC_FLAG_Level - Level detection Flag.
* FSMC_FLAG_FallingEdge - Falling egde detection Flag.
*
* @return none
*/
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
{
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 &= ~FSMC_FLAG;
}
}
/*********************************************************************
* @fn FSMC_GetITStatus
*
* @brief Checks whether the specified FSMC interrupt has occurred or not.
*
* @param FSMC_Bank - specifies the FSMC Bank to be used
* FSMC_Bank2_NAND - FSMC Bank2 NAND
* FSMC_IT - specifies the FSMC interrupt source to check.
* FSMC_IT_RisingEdge - Rising edge detection interrupt.
* FSMC_IT_Level - Level edge detection interrupt.
* FSMC_IT_FallingEdge - Falling edge detection interrupt.
*
* @return ITStatus - The new state of FSMC_IT (SET or RESET).
*/
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
if(FSMC_Bank == FSMC_Bank2_NAND)
{
tmpsr = FSMC_Bank2->SR2;
}
itstatus = tmpsr & FSMC_IT;
itenable = tmpsr & (FSMC_IT >> 3);
if((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn FSMC_ClearITPendingBit
*
* @brief Clears the FSMC's interrupt pending bits.
*
* @param FSMC_Bank - specifies the FSMC Bank to be used
* FSMC_Bank2_NAND - FSMC Bank2 NAND
* FSMC_IT - specifies the FSMC interrupt source to check.
* FSMC_IT_RisingEdge - Rising edge detection interrupt.
* FSMC_IT_Level - Level edge detection interrupt.
* FSMC_IT_FallingEdge - Falling edge detection interrupt.
*
* @return none
*/
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
{
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
}
}

287
libraries/sdk/Peripheral/ch32v30x_fsmc.h Normal file
View File

@@ -0,0 +1,287 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_fsmc.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the FSMC
* firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_FSMC_H
#define __CH32V30x_FSMC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* FSMC Init structure definition */
typedef struct
{
uint32_t FSMC_AddressSetupTime; /* Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between 0 and 0xF.
@note: It is not used with synchronous NOR Flash memories. */
uint32_t FSMC_AddressHoldTime; /* Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between 0 and 0xF.
@note: It is not used with synchronous NOR Flash memories.*/
uint32_t FSMC_DataSetupTime; /* Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between 0 and 0xFF.
@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
uint32_t FSMC_BusTurnAroundDuration; /* Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between 0 and 0xF.
@note: It is only used for multiplexed NOR Flash memories. */
uint32_t FSMC_CLKDivision; /* Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
This parameter can be a value between 1 and 0xF.
@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
uint32_t FSMC_DataLatency; /* Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The value of this parameter depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between 0 and 0xF in NOR Flash memories
with synchronous burst mode enable */
uint32_t FSMC_AccessMode; /* Specifies the asynchronous access mode.
This parameter can be a value of @ref FSMC_Access_Mode */
}FSMC_NORSRAMTimingInitTypeDef;
typedef struct
{
uint32_t FSMC_Bank; /* Specifies the NOR/SRAM memory bank that will be used.
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
uint32_t FSMC_DataAddressMux; /* Specifies whether the address and data values are
multiplexed on the databus or not.
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
uint32_t FSMC_MemoryType; /* Specifies the type of external memory attached to
the corresponding memory bank.
This parameter can be a value of @ref FSMC_Memory_Type */
uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width.
This parameter can be a value of @ref FSMC_Data_Width */
uint32_t FSMC_BurstAccessMode; /* Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
uint32_t FSMC_AsynchronousWait; /* Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FSMC_AsynchronousWait */
uint32_t FSMC_WaitSignalPolarity; /* Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
uint32_t FSMC_WrapMode; /* Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FSMC_Wrap_Mode */
uint32_t FSMC_WaitSignalActive; /* Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FSMC_Wait_Timing */
uint32_t FSMC_WriteOperation; /* Enables or disables the write operation in the selected bank by the FSMC.
This parameter can be a value of @ref FSMC_Write_Operation */
uint32_t FSMC_WaitSignal; /* Enables or disables the wait-state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal */
uint32_t FSMC_ExtendedMode; /* Enables or disables the extended mode.
This parameter can be a value of @ref FSMC_Extended_Mode */
uint32_t FSMC_WriteBurst; /* Enables or disables the write burst operation.
This parameter can be a value of @ref FSMC_Write_Burst */
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /* Timing Parameters for write and read access if the ExtendedMode is not used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /* Timing Parameters for write access if the ExtendedMode is used*/
}FSMC_NORSRAMInitTypeDef;
typedef struct
{
uint32_t FSMC_SetupTime; /* Defines the number of HCLK cycles to setup address before
the command assertion for NAND-Flash read or write access
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between 0 and 0xFF.*/
uint32_t FSMC_WaitSetupTime; /* Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
This parameter can be a number between 0x00 and 0xFF */
uint32_t FSMC_HoldSetupTime; /* Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command deassertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between 0x00 and 0xFF */
uint32_t FSMC_HiZSetupTime; /* Defines the number of HCLK clock cycles during which the
databus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between 0x00 and 0xFF */
}FSMC_NAND_PCCARDTimingInitTypeDef;
typedef struct
{
uint32_t FSMC_Bank; /* Specifies the NAND memory bank that will be used.
This parameter can be a value of @ref FSMC_NAND_Bank */
uint32_t FSMC_Waitfeature; /* Enables or disables the Wait feature for the NAND Memory Bank.
This parameter can be any value of @ref FSMC_Wait_feature */
uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width.
This parameter can be any value of @ref FSMC_Data_Width */
uint32_t FSMC_ECC; /* Enables or disables the ECC computation.
This parameter can be any value of @ref FSMC_ECC */
uint32_t FSMC_ECCPageSize; /* Defines the page size for the extended ECC.
This parameter can be any value of @ref FSMC_ECC_Page_Size */
uint32_t FSMC_TCLRSetupTime; /* Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between 0 and 0xFF. */
uint32_t FSMC_TARSetupTime; /* Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between 0x0 and 0xFF */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /* FSMC Common Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */
}FSMC_NANDInitTypeDef;
/* FSMC_NORSRAM_Bank */
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
/* FSMC_NAND_Bank */
#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
/* FSMC_Data_Address_Bus_Multiplexing */
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
/* FSMC_Memory_Type */
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
/* FSMC_Data_Width */
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
/* FSMC_Burst_Access_Mode */
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
/* FSMC_AsynchronousWait */
#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
/* FSMC_Wait_Signal_Polarity */
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
/* FSMC_Wrap_Mode */
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
/* FSMC_Wait_Timing */
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
/* FSMC_Write_Operation */
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
/* FSMC_Wait_Signal */
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
/* FSMC_Extended_Mode */
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
/* FSMC_Write_Burst */
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
/* FSMC_Access_Mode */
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
/* FSMC_Wait_feature */
#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
/* FSMC_ECC */
#define FSMC_ECC_Disable ((uint32_t)0x00000000)
#define FSMC_ECC_Enable ((uint32_t)0x00000040)
/* FSMC_ECC_Page_Size */
#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
/* FSMC_Interrupt_sources */
#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
#define FSMC_IT_Level ((uint32_t)0x00000010)
#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
/* FSMC_Flags */
#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
#define FSMC_FLAG_Level ((uint32_t)0x00000002)
#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
void FSMC_NANDDeInit(uint32_t FSMC_Bank);
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
#ifdef __cplusplus
}
#endif
#endif

566
libraries/sdk/Peripheral/ch32v30x_gpio.c Normal file
View File

@@ -0,0 +1,566 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_gpio.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the GPIO firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v30x_gpio.h"
#include "ch32v30x_rcc.h"
/* MASK */
#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
#define LSB_MASK ((uint16_t)0xFFFF)
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
/*********************************************************************
* @fn GPIO_DeInit
*
* @brief Deinitializes the GPIOx peripheral registers to their default
* reset values.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
*
* @return none
*/
void GPIO_DeInit(GPIO_TypeDef *GPIOx)
{
if(GPIOx == GPIOA)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
}
else if(GPIOx == GPIOB)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
}
else if(GPIOx == GPIOC)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
}
else if(GPIOx == GPIOD)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
}
else if(GPIOx == GPIOE)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
}
}
/*********************************************************************
* @fn GPIO_AFIODeInit
*
* @brief Deinitializes the Alternate Functions (remap, event control
* and EXTI configuration) registers to their default reset values.
*
* @return none
*/
void GPIO_AFIODeInit(void)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
}
/*********************************************************************
* @fn GPIO_Init
*
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
*
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that
* contains the configuration information for the specified GPIO peripheral.
*
* @return none
*/
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
{
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
uint32_t tmpreg = 0x00, pinmask = 0x00;
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
{
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
}
if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
{
tmpreg = GPIOx->CFGLR;
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if(currentpin == pos)
{
pos = pinpos << 2;
pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
tmpreg |= (currentmode << pos);
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BCR = (((uint32_t)0x01) << pinpos);
}
else
{
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSHR = (((uint32_t)0x01) << pinpos);
}
}
}
}
GPIOx->CFGLR = tmpreg;
}
if(GPIO_InitStruct->GPIO_Pin > 0x00FF)
{
tmpreg = GPIOx->CFGHR;
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = (((uint32_t)0x01) << (pinpos + 0x08));
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
if(currentpin == pos)
{
pos = pinpos << 2;
pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
tmpreg |= (currentmode << pos);
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08));
}
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08));
}
}
}
GPIOx->CFGHR = tmpreg;
}
}
/*********************************************************************
* @fn GPIO_StructInit
*
* @brief Fills each GPIO_InitStruct member with its default
*
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure
* which will be initialized.
*
* @return none
*/
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
{
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
}
/*********************************************************************
* @fn GPIO_ReadInputDataBit
*
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
*
* @param GPIO_Pin - specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
*
* @return The input port pin value.
*/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn GPIO_ReadInputData
*
* @brief Reads the specified GPIO input data port.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
*
* @return The output port pin value.
*/
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
{
return ((uint16_t)GPIOx->INDR);
}
/*********************************************************************
* @fn GPIO_ReadOutputDataBit
*
* @brief Reads the specified output data port bit.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* GPIO_Pin - specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
*
* @return none
*/
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn GPIO_ReadOutputData
*
* @brief Reads the specified GPIO output data port.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
*
* @return GPIO output port pin value.
*/
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
{
return ((uint16_t)GPIOx->OUTDR);
}
/*********************************************************************
* @fn GPIO_SetBits
*
* @brief Sets the selected data port bits.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* GPIO_Pin - specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
*
* @return none
*/
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
GPIOx->BSHR = GPIO_Pin;
}
/*********************************************************************
* @fn GPIO_ResetBits
*
* @brief Clears the selected data port bits.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* GPIO_Pin - specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
*
* @return none
*/
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
GPIOx->BCR = GPIO_Pin;
}
/*********************************************************************
* @fn GPIO_WriteBit
*
* @brief Sets or clears the selected data port bit.
*
* @param GPIO_Pin - specifies the port bit to be written.
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
* BitVal - specifies the value to be written to the selected bit.
* Bit_SetL - to clear the port pin.
* Bit_SetH - to set the port pin.
*
* @return none
*/
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
{
if(BitVal != Bit_RESET)
{
GPIOx->BSHR = GPIO_Pin;
}
else
{
GPIOx->BCR = GPIO_Pin;
}
}
/*********************************************************************
* @fn GPIO_Write
*
* @brief Writes data to the specified GPIO data port.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* PortVal - specifies the value to be written to the port output data register.
*
* @return none
*/
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal)
{
GPIOx->OUTDR = PortVal;
}
/*********************************************************************
* @fn GPIO_PinLockConfig
*
* @brief Locks GPIO Pins configuration registers.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* GPIO_Pin - specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
*
* @return none
*/
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t tmp = 0x00010000;
tmp |= GPIO_Pin;
GPIOx->LCKR = tmp;
GPIOx->LCKR = GPIO_Pin;
GPIOx->LCKR = tmp;
tmp = GPIOx->LCKR;
tmp = GPIOx->LCKR;
}
/*********************************************************************
* @fn GPIO_EventOutputConfig
*
* @brief Selects the GPIO pin used as Event output.
*
* @param GPIO_PortSource - selects the GPIO port to be used as source
* for Event output.
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
* GPIO_PinSource - specifies the pin for the Event output.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
*
* @return none
*/
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
{
uint32_t tmpreg = 0x00;
tmpreg = AFIO->ECR;
tmpreg &= ECR_PORTPINCONFIG_MASK;
tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
tmpreg |= GPIO_PinSource;
AFIO->ECR = tmpreg;
}
/*********************************************************************
* @fn GPIO_EventOutputCmd
*
* @brief Enables or disables the Event Output.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void GPIO_EventOutputCmd(FunctionalState NewState)
{
if(NewState)
{
AFIO->ECR |= (1 << 7);
}
else
{
AFIO->ECR &= ~(1 << 7);
}
}
/*********************************************************************
* @fn GPIO_PinRemapConfig
*
* @brief Changes the mapping of the specified pin.
*
* @param GPIO_Remap - selects the pin to remap.
* GPIO_Remap_SPI1 - SPI1 Alternate Function mapping
* GPIO_Remap_I2C1 - I2C1 Alternate Function mapping
* GPIO_Remap_USART1 - USART1 Alternate Function mapping
* GPIO_Remap_USART2 - USART2 Alternate Function mapping
* GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping
* GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping
* GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping
* GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping
* GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping
* GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping
* GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping
* GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping
* GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping
* GPIO_Remap_TIM4 - TIM4 Alternate Function mapping
* GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping
* GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping
* GPIO_Remap_PD01 - PD01 Alternate Function mapping
* GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping
* GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping
* GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping
* GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping
* GPIO_Remap_ETH - Ethernet remapping
* GPIO_Remap_CAN2 - CAN2 remapping
* GPIO_Remap_MII_RMII_SEL - MII or RMII selection
* GPIO_Remap_SWJ_NoJTRST - Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
* GPIO_Remap_SWJ_JTAGDisable - JTAG-DP Disabled and SW-DP Enabled
* GPIO_Remap_SWJ_Disable - Full SWJ Disabled (JTAG-DP + SW-DP)
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected
* to TIM2 Internal Trigger 1 for calibration
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame)
* GPIO_Remap_TIM8 - TIM8 Alternate Function mapping
* GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping
* GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping
* GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping
* GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping
* GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping
* GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping
* GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping
* GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping
* GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping
* GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping
* GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping
* GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping
* GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping
* GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping
* GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping
* GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
{
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
if((GPIO_Remap & 0x80000000) == 0x80000000)
{
tmpreg = AFIO->PCFR2;
}
else
{
tmpreg = AFIO->PCFR1;
}
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
tmp = GPIO_Remap & LSB_MASK;
/* Clear bit */
if((GPIO_Remap & 0x80000000) == 0x80000000)
{ /* PCFR2 */
if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */
{
tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10);
tmpreg &= ~tmp1;
}
else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
{
tmp1 = ((uint32_t)0x03) << tmpmask;
tmpreg &= ~tmp1;
}
else /* [31:0] 1bit */
{
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10));
}
}
else
{ /* PCFR1 */
if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */
{
tmpreg &= DBGAFR_SWJCFG_MASK;
AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK;
}
else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
{
tmp1 = ((uint32_t)0x03) << tmpmask;
tmpreg &= ~tmp1;
tmpreg |= ~DBGAFR_SWJCFG_MASK;
}
else /* [31:0] 1bit */
{
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10));
tmpreg |= ~DBGAFR_SWJCFG_MASK;
}
}
/* Set bit */
if(NewState != DISABLE)
{
tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10));
}
if((GPIO_Remap & 0x80000000) == 0x80000000)
{
AFIO->PCFR2 = tmpreg;
}
else
{
AFIO->PCFR1 = tmpreg;
}
}
/*********************************************************************
* @fn GPIO_EXTILineConfig
*
* @brief Selects the GPIO pin used as EXTI Line.
*
* @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines.
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
* GPIO_PinSource - specifies the EXTI line to be configured.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
*
* @return none
*/
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
{
uint32_t tmp = 0x00;
tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
}
/*********************************************************************
* @fn GPIO_ETH_MediaInterfaceConfig
*
* @brief Selects the Ethernet media interface.
*
* @param GPIO_ETH_MediaInterface - specifies the Media Interface mode.
* GPIO_ETH_MediaInterface_MII - MII mode
* GPIO_ETH_MediaInterface_RMII - RMII mode
*
* @return none
*/
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
{
if(GPIO_ETH_MediaInterface)
{
AFIO->PCFR1 |= (1 << 23);
}
else
{
AFIO->PCFR1 &= ~(1 << 23);
}
}

197
libraries/sdk/Peripheral/ch32v30x_gpio.h Normal file
View File

@@ -0,0 +1,197 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_gpio.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* GPIO firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_GPIO_H
#define __CH32V30x_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* Output Maximum frequency selection */
typedef enum
{
GPIO_Speed_10MHz = 1,
GPIO_Speed_2MHz,
GPIO_Speed_50MHz
}GPIOSpeed_TypeDef;
/* Configuration Mode enumeration */
typedef enum
{ GPIO_Mode_AIN = 0x0,
GPIO_Mode_IN_FLOATING = 0x04,
GPIO_Mode_IPD = 0x28,
GPIO_Mode_IPU = 0x48,
GPIO_Mode_Out_OD = 0x14,
GPIO_Mode_Out_PP = 0x10,
GPIO_Mode_AF_OD = 0x1C,
GPIO_Mode_AF_PP = 0x18
}GPIOMode_TypeDef;
/* GPIO Init structure definition */
typedef struct
{
uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIOSpeed_TypeDef */
GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIOMode_TypeDef */
}GPIO_InitTypeDef;
/* Bit_SET and Bit_RESET enumeration */
typedef enum
{
Bit_RESET = 0,
Bit_SET
}BitAction;
/* GPIO_pins_define */
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
/* GPIO_Remap_define */
/* PCFR1 */
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */
#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */
#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */
#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */
#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected
to TIM2 Internal Trigger 1 for calibration
(only for Connectivity line devices) */
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
/* PCFR2 */
#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */
#define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */
#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */
#define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */
#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */
/* GPIO_Port_Sources */
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
/* GPIO_Pin_sources */
#define GPIO_PinSource0 ((uint8_t)0x00)
#define GPIO_PinSource1 ((uint8_t)0x01)
#define GPIO_PinSource2 ((uint8_t)0x02)
#define GPIO_PinSource3 ((uint8_t)0x03)
#define GPIO_PinSource4 ((uint8_t)0x04)
#define GPIO_PinSource5 ((uint8_t)0x05)
#define GPIO_PinSource6 ((uint8_t)0x06)
#define GPIO_PinSource7 ((uint8_t)0x07)
#define GPIO_PinSource8 ((uint8_t)0x08)
#define GPIO_PinSource9 ((uint8_t)0x09)
#define GPIO_PinSource10 ((uint8_t)0x0A)
#define GPIO_PinSource11 ((uint8_t)0x0B)
#define GPIO_PinSource12 ((uint8_t)0x0C)
#define GPIO_PinSource13 ((uint8_t)0x0D)
#define GPIO_PinSource14 ((uint8_t)0x0E)
#define GPIO_PinSource15 ((uint8_t)0x0F)
/* Ethernet_Media_Interface */
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
void GPIO_AFIODeInit(void);
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_EventOutputCmd(FunctionalState NewState);
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
#ifdef __cplusplus
}
#endif
#endif

972
libraries/sdk/Peripheral/ch32v30x_i2c.c Normal file
View File

@@ -0,0 +1,972 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_i2c.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the I2C firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v30x_i2c.h"
#include "ch32v30x_rcc.h"
/* I2C SPE mask */
#define CTLR1_PE_Set ((uint16_t)0x0001)
#define CTLR1_PE_Reset ((uint16_t)0xFFFE)
/* I2C START mask */
#define CTLR1_START_Set ((uint16_t)0x0100)
#define CTLR1_START_Reset ((uint16_t)0xFEFF)
/* I2C STOP mask */
#define CTLR1_STOP_Set ((uint16_t)0x0200)
#define CTLR1_STOP_Reset ((uint16_t)0xFDFF)
/* I2C ACK mask */
#define CTLR1_ACK_Set ((uint16_t)0x0400)
#define CTLR1_ACK_Reset ((uint16_t)0xFBFF)
/* I2C ENGC mask */
#define CTLR1_ENGC_Set ((uint16_t)0x0040)
#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF)
/* I2C SWRST mask */
#define CTLR1_SWRST_Set ((uint16_t)0x8000)
#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF)
/* I2C PEC mask */
#define CTLR1_PEC_Set ((uint16_t)0x1000)
#define CTLR1_PEC_Reset ((uint16_t)0xEFFF)
/* I2C ENPEC mask */
#define CTLR1_ENPEC_Set ((uint16_t)0x0020)
#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF)
/* I2C ENARP mask */
#define CTLR1_ENARP_Set ((uint16_t)0x0010)
#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF)
/* I2C NOSTRETCH mask */
#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080)
#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
/* I2C registers Masks */
#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5)
/* I2C DMAEN mask */
#define CTLR2_DMAEN_Set ((uint16_t)0x0800)
#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF)
/* I2C LAST mask */
#define CTLR2_LAST_Set ((uint16_t)0x1000)
#define CTLR2_LAST_Reset ((uint16_t)0xEFFF)
/* I2C FREQ mask */
#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0)
/* I2C ADD0 mask */
#define OADDR1_ADD0_Set ((uint16_t)0x0001)
#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE)
/* I2C ENDUAL mask */
#define OADDR2_ENDUAL_Set ((uint16_t)0x0001)
#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE)
/* I2C ADD2 mask */
#define OADDR2_ADD2_Reset ((uint16_t)0xFF01)
/* I2C F/S mask */
#define CKCFGR_FS_Set ((uint16_t)0x8000)
/* I2C CCR mask */
#define CKCFGR_CCR_Set ((uint16_t)0x0FFF)
/* I2C FLAG mask */
#define FLAG_Mask ((uint32_t)0x00FFFFFF)
/* I2C Interrupt Enable mask */
#define ITEN_Mask ((uint32_t)0x07000000)
/*********************************************************************
* @fn I2C_DeInit
*
* @brief Deinitializes the I2Cx peripheral registers to their default
* reset values.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
*
* @return none
*/
void I2C_DeInit(I2C_TypeDef *I2Cx)
{
if(I2Cx == I2C1)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
}
else
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
}
}
/*********************************************************************
* @fn I2C_Init
*
* @brief Initializes the I2Cx peripheral according to the specified
* parameters in the I2C_InitStruct.
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* I2C_InitStruct - pointer to a I2C_InitTypeDef structure that
* contains the configuration information for the specified I2C peripheral.
*
* @return none
*/
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
{
uint16_t tmpreg = 0, freqrange = 0;
uint16_t result = 0x04;
uint32_t pclk1 = 8000000;
RCC_ClocksTypeDef rcc_clocks;
tmpreg = I2Cx->CTLR2;
tmpreg &= CTLR2_FREQ_Reset;
RCC_GetClocksFreq(&rcc_clocks);
pclk1 = rcc_clocks.PCLK1_Frequency;
freqrange = (uint16_t)(pclk1 / 1000000);
tmpreg |= freqrange;
I2Cx->CTLR2 = tmpreg;
I2Cx->CTLR1 &= CTLR1_PE_Reset;
tmpreg = 0;
if(I2C_InitStruct->I2C_ClockSpeed <= 100000)
{
result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
if(result < 0x04)
{
result = 0x04;
}
tmpreg |= result;
I2Cx->RTR = freqrange + 1;
}
else
{
if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
{
result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
}
else
{
result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
result |= I2C_DutyCycle_16_9;
}
if((result & CKCFGR_CCR_Set) == 0)
{
result |= (uint16_t)0x0001;
}
tmpreg |= (uint16_t)(result | CKCFGR_FS_Set);
I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
}
I2Cx->CKCFGR = tmpreg;
I2Cx->CTLR1 |= CTLR1_PE_Set;
tmpreg = I2Cx->CTLR1;
tmpreg &= CTLR1_CLEAR_Mask;
tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
I2Cx->CTLR1 = tmpreg;
I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
}
/*********************************************************************
* @fn I2C_StructInit
*
* @brief Fills each I2C_InitStruct member with its default value.
*
* @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which
* will be initialized.
*
* @return none
*/
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct)
{
I2C_InitStruct->I2C_ClockSpeed = 5000;
I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
I2C_InitStruct->I2C_OwnAddress1 = 0;
I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
}
/*********************************************************************
* @fn I2C_Cmd
*
* @brief Enables or disables the specified I2C peripheral.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_PE_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_PE_Reset;
}
}
/*********************************************************************
* @fn I2C_DMACmd
*
* @brief Enables or disables the specified I2C DMA requests.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
I2Cx->CTLR2 |= CTLR2_DMAEN_Set;
}
else
{
I2Cx->CTLR2 &= CTLR2_DMAEN_Reset;
}
}
/*********************************************************************
* @fn I2C_DMALastTransferCmd
*
* @brief Specifies if the next DMA transfer will be the last one.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
I2Cx->CTLR2 |= CTLR2_LAST_Set;
}
else
{
I2Cx->CTLR2 &= CTLR2_LAST_Reset;
}
}
/*********************************************************************
* @fn I2C_GenerateSTART
*
* @brief Generates I2Cx communication START condition.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_START_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_START_Reset;
}
}
/*********************************************************************
* @fn I2C_GenerateSTOP
*
* @brief Generates I2Cx communication STOP condition.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_STOP_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_STOP_Reset;
}
}
/*********************************************************************
* @fn I2C_AcknowledgeConfig
*
* @brief Enables or disables the specified I2C acknowledge feature.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_ACK_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_ACK_Reset;
}
}
/*********************************************************************
* @fn I2C_OwnAddress2Config
*
* @brief Configures the specified I2C own address2.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* Address - specifies the 7bit I2C own address2.
*
* @return none
*/
void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address)
{
uint16_t tmpreg = 0;
tmpreg = I2Cx->OADDR2;
tmpreg &= OADDR2_ADD2_Reset;
tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
I2Cx->OADDR2 = tmpreg;
}
/*********************************************************************
* @fn I2C_DualAddressCmd
*
* @brief Enables or disables the specified I2C dual addressing mode.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
I2Cx->OADDR2 |= OADDR2_ENDUAL_Set;
}
else
{
I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset;
}
}
/*********************************************************************
* @fn I2C_GeneralCallCmd
*
* @brief Enables or disables the specified I2C general call feature.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_ENGC_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_ENGC_Reset;
}
}
/*********************************************************************
* @fn I2C_ITConfig
*
* @brief Enables or disables the specified I2C interrupts.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* I2C_IT - specifies the I2C interrupts sources to be enabled or disabled.
* I2C_IT_BUF - Buffer interrupt mask.
* I2C_IT_EVT - Event interrupt mask.
* I2C_IT_ERR - Error interrupt mask.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
{
if(NewState != DISABLE)
{
I2Cx->CTLR2 |= I2C_IT;
}
else
{
I2Cx->CTLR2 &= (uint16_t)~I2C_IT;
}
}
/*********************************************************************
* @fn I2C_SendData
*
* @brief Sends a data byte through the I2Cx peripheral.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* Data - Byte to be transmitted.
*
* @return none
*/
void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data)
{
I2Cx->DATAR = Data;
}
/*********************************************************************
* @fn I2C_ReceiveData
*
* @brief Returns the most recent received data by the I2Cx peripheral.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
*
* @return The value of the received data.
*/
uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx)
{
return (uint8_t)I2Cx->DATAR;
}
/*********************************************************************
* @fn I2C_Send7bitAddress
*
* @brief Transmits the address byte to select the slave device.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* Address - specifies the slave address which will be transmitted.
* I2C_Direction - specifies whether the I2C device will be a
* Transmitter or a Receiver.
* I2C_Direction_Transmitter - Transmitter mode.
* I2C_Direction_Receiver - Receiver mode.
*
* @return none
*/
void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
{
if(I2C_Direction != I2C_Direction_Transmitter)
{
Address |= OADDR1_ADD0_Set;
}
else
{
Address &= OADDR1_ADD0_Reset;
}
I2Cx->DATAR = Address;
}
/*********************************************************************
* @fn I2C_ReadRegister
*
* @brief Reads the specified I2C register and returns its value.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* I2C_Register - specifies the register to read.
* I2C_Register_CTLR1.
* I2C_Register_CTLR2.
* I2C_Register_OADDR1.
* I2C_Register_OADDR2.
* I2C_Register_DATAR.
* I2C_Register_STAR1.
* I2C_Register_STAR2.
* I2C_Register_CKCFGR.
* I2C_Register_RTR.
*
* @return none
*/
uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)I2Cx;
tmp += I2C_Register;
return (*(__IO uint16_t *)tmp);
}
/*********************************************************************
* @fn I2C_SoftwareResetCmd
*
* @brief Enables or disables the specified I2C software reset.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_SWRST_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_SWRST_Reset;
}
}
/*********************************************************************
* @fn I2C_NACKPositionConfig
*
* @brief Selects the specified I2C NACK position in master receiver mode.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* I2C_NACKPosition - specifies the NACK position.
* I2C_NACKPosition_Next - indicates that the next byte will be
* the last received byte.
* I2C_NACKPosition_Current - indicates that current byte is the
* last received byte.
*
* @return none
*/
void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
{
if(I2C_NACKPosition == I2C_NACKPosition_Next)
{
I2Cx->CTLR1 |= I2C_NACKPosition_Next;
}
else
{
I2Cx->CTLR1 &= I2C_NACKPosition_Current;
}
}
/*********************************************************************
* @fn I2C_SMBusAlertConfig
*
* @brief Drives the SMBusAlert pin high or low for the specified I2C.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* I2C_SMBusAlert - specifies SMBAlert pin level.
* I2C_SMBusAlert_Low - SMBAlert pin driven low.
* I2C_SMBusAlert_High - SMBAlert pin driven high.
*
* @return none
*/
void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
{
if(I2C_SMBusAlert == I2C_SMBusAlert_Low)
{
I2Cx->CTLR1 |= I2C_SMBusAlert_Low;
}
else
{
I2Cx->CTLR1 &= I2C_SMBusAlert_High;
}
}
/*********************************************************************
* @fn I2C_TransmitPEC
*
* @brief Enables or disables the specified I2C PEC transfer.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_PEC_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_PEC_Reset;
}
}
/*********************************************************************
* @fn I2C_PECPositionConfig
*
* @brief Selects the specified I2C PEC position.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* I2C_PECPosition - specifies the PEC position.
* I2C_PECPosition_Next - indicates that the next byte is PEC.
* I2C_PECPosition_Current - indicates that current byte is PEC.
*
* @return none
*/
void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
{
if(I2C_PECPosition == I2C_PECPosition_Next)
{
I2Cx->CTLR1 |= I2C_PECPosition_Next;
}
else
{
I2Cx->CTLR1 &= I2C_PECPosition_Current;
}
}
/*********************************************************************
* @fn I2C_CalculatePEC
*
* @brief Enables or disables the PEC value calculation of the transferred bytes.
*
* @param I2Cx- where x can be 1 or 2 to select the I2C peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_ENPEC_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_ENPEC_Reset;
}
}
/*********************************************************************
* @fn I2C_GetPEC
*
* @brief Returns the PEC value for the specified I2C.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
*
* @return The PEC value.
*/
uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx)
{
return ((I2Cx->STAR2) >> 8);
}
/*********************************************************************
* @fn I2C_ARPCmd
*
* @brief Enables or disables the specified I2C ARP.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* NewState - ENABLE or DISABLE.
*
* @return The PEC value.
*/
void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_ENARP_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_ENARP_Reset;
}
}
/*********************************************************************
* @fn I2C_StretchClockCmd
*
* @brief Enables or disables the specified I2C Clock stretching.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
{
if(NewState == DISABLE)
{
I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset;
}
}
/*********************************************************************
* @fn I2C_FastModeDutyCycleConfig
*
* @brief Selects the specified I2C fast mode duty cycle.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* I2C_DutyCycle - specifies the fast mode duty cycle.
* I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2.
* I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9.
*
* @return none
*/
void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
{
if(I2C_DutyCycle != I2C_DutyCycle_16_9)
{
I2Cx->CKCFGR &= I2C_DutyCycle_2;
}
else
{
I2Cx->CKCFGR |= I2C_DutyCycle_16_9;
}
}
/*********************************************************************
* @fn I2C_CheckEvent
*
* @brief Checks whether the last I2Cx Event is equal to the one passed
* as parameter.
*
* @param I2Cx- where x can be 1 or 2 to select the I2C peripheral.
* I2C_EVENT: specifies the event to be checked.
* I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EV1.
* I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EV1.
* I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EV1.
* I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EV1.
* I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EV1.
* I2C_EVENT_SLAVE_BYTE_RECEIVED - EV2.
* (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EV2.
* (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EV2.
* I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EV3.
* (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EV3.
* (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EV3.
* I2C_EVENT_SLAVE_ACK_FAILURE - EV3_2.
* I2C_EVENT_SLAVE_STOP_DETECTED - EV4.
* I2C_EVENT_MASTER_MODE_SELECT - EV5.
* I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EV6.
* I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EV6.
* I2C_EVENT_MASTER_BYTE_RECEIVED - EV7.
* I2C_EVENT_MASTER_BYTE_TRANSMITTING - EV8.
* I2C_EVENT_MASTER_BYTE_TRANSMITTED - EV8_2.
* I2C_EVENT_MASTER_MODE_ADDRESS10 - EV9.
*
* @return none
*/
ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
{
uint32_t lastevent = 0;
uint32_t flag1 = 0, flag2 = 0;
ErrorStatus status = ERROR;
flag1 = I2Cx->STAR1;
flag2 = I2Cx->STAR2;
flag2 = flag2 << 16;
lastevent = (flag1 | flag2) & FLAG_Mask;
if((lastevent & I2C_EVENT) == I2C_EVENT)
{
status = SUCCESS;
}
else
{
status = ERROR;
}
return status;
}
/*********************************************************************
* @fn I2C_GetLastEvent
*
* @brief Returns the last I2Cx Event.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
*
* @return none
*/
uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx)
{
uint32_t lastevent = 0;
uint32_t flag1 = 0, flag2 = 0;
flag1 = I2Cx->STAR1;
flag2 = I2Cx->STAR2;
flag2 = flag2 << 16;
lastevent = (flag1 | flag2) & FLAG_Mask;
return lastevent;
}
/*********************************************************************
* @fn I2C_GetFlagStatus
*
* @brief Checks whether the last I2Cx Event is equal to the one passed
* as parameter.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* I2C_FLAG - specifies the flag to check.
* I2C_FLAG_DUALF - Dual flag (Slave mode).
* I2C_FLAG_SMBHOST - SMBus host header (Slave mode).
* I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode).
* I2C_FLAG_GENCALL - General call header flag (Slave mode).
* I2C_FLAG_TRA - Transmitter/Receiver flag.
* I2C_FLAG_BUSY - Bus busy flag.
* I2C_FLAG_MSL - Master/Slave flag.
* I2C_FLAG_SMBALERT - SMBus Alert flag.
* I2C_FLAG_TIMEOUT - Timeout or Tlow error flag.
* I2C_FLAG_PECERR - PEC error in reception flag.
* I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode).
* I2C_FLAG_AF - Acknowledge failure flag.
* I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
* I2C_FLAG_BERR - Bus error flag.
* I2C_FLAG_TXE - Data register empty flag (Transmitter).
* I2C_FLAG_RXNE- Data register not empty (Receiver) flag.
* I2C_FLAG_STOPF - Stop detection flag (Slave mode).
* I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode).
* I2C_FLAG_BTF - Byte transfer finished flag.
* I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL"
* Address matched flag (Slave mode)"ENDA".
* I2C_FLAG_SB - Start bit flag (Master mode).
*
* @return none
*/
FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
{
FlagStatus bitstatus = RESET;
__IO uint32_t i2creg = 0, i2cxbase = 0;
i2cxbase = (uint32_t)I2Cx;
i2creg = I2C_FLAG >> 28;
I2C_FLAG &= FLAG_Mask;
if(i2creg != 0)
{
i2cxbase += 0x14;
}
else
{
I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
i2cxbase += 0x18;
}
if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn I2C_ClearFlag
*
* @brief Clears the I2Cx's pending flags.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* I2C_FLAG - specifies the flag to clear.
* I2C_FLAG_SMBALERT - SMBus Alert flag.
* I2C_FLAG_TIMEOUT - Timeout or Tlow error flag.
* I2C_FLAG_PECERR - PEC error in reception flag.
* I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode).
* I2C_FLAG_AF - Acknowledge failure flag.
* I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
* I2C_FLAG_BERR - Bus error flag.
*
* @return none
*/
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
{
uint32_t flagpos = 0;
flagpos = I2C_FLAG & FLAG_Mask;
I2Cx->STAR1 = (uint16_t)~flagpos;
}
/*********************************************************************
* @fn I2C_GetITStatus
*
* @brief Checks whether the specified I2C interrupt has occurred or not.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* II2C_IT - specifies the interrupt source to check.
* I2C_IT_SMBALERT - SMBus Alert flag.
* I2C_IT_TIMEOUT - Timeout or Tlow error flag.
* I2C_IT_PECERR - PEC error in reception flag.
* I2C_IT_OVR - Overrun/Underrun flag (Slave mode).
* I2C_IT_AF - Acknowledge failure flag.
* I2C_IT_ARLO - Arbitration lost flag (Master mode).
* I2C_IT_BERR - Bus error flag.
* I2C_IT_TXE - Data register empty flag (Transmitter).
* I2C_IT_RXNE - Data register not empty (Receiver) flag.
* I2C_IT_STOPF - Stop detection flag (Slave mode).
* I2C_IT_ADD10 - 10-bit header sent flag (Master mode).
* I2C_IT_BTF - Byte transfer finished flag.
* I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched
* flag (Slave mode)"ENDAD".
* I2C_IT_SB - Start bit flag (Master mode).
*
* @return none
*/
ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2));
I2C_IT &= FLAG_Mask;
if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn I2C_ClearITPendingBit
*
* @brief Clears the I2Cx interrupt pending bits.
*
* @param I2Cx - where x can be 1 or 2 to select the I2C peripheral.
* I2C_IT - specifies the interrupt pending bit to clear.
* I2C_IT_SMBALERT - SMBus Alert interrupt.
* I2C_IT_TIMEOUT - Timeout or Tlow error interrupt.
* I2C_IT_PECERR - PEC error in reception interrupt.
* I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode).
* I2C_IT_AF - Acknowledge failure interrupt.
* I2C_IT_ARLO - Arbitration lost interrupt (Master mode).
* I2C_IT_BERR - Bus error interrupt.
*
* @return none
*/
void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
{
uint32_t flagpos = 0;
flagpos = I2C_IT & FLAG_Mask;
I2Cx->STAR1 = (uint16_t)~flagpos;
}

211
libraries/sdk/Peripheral/ch32v30x_i2c.h Normal file
View File

@@ -0,0 +1,211 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_i2c.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* I2C firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_I2C_H
#define __CH32V30x_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* I2C Init structure definition */
typedef struct
{
uint32_t I2C_ClockSpeed; /* Specifies the clock frequency.
This parameter must be set to a value lower than 400kHz */
uint16_t I2C_Mode; /* Specifies the I2C mode.
This parameter can be a value of @ref I2C_mode */
uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle.
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
uint16_t I2C_OwnAddress1; /* Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint16_t I2C_Ack; /* Enables or disables the acknowledgement.
This parameter can be a value of @ref I2C_acknowledgement */
uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
This parameter can be a value of @ref I2C_acknowledged_address */
}I2C_InitTypeDef;
/* I2C_mode */
#define I2C_Mode_I2C ((uint16_t)0x0000)
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
/* I2C_duty_cycle_in_fast_mode */
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
/* I2C_acknowledgement */
#define I2C_Ack_Enable ((uint16_t)0x0400)
#define I2C_Ack_Disable ((uint16_t)0x0000)
/* I2C_transfer_direction */
#define I2C_Direction_Transmitter ((uint8_t)0x00)
#define I2C_Direction_Receiver ((uint8_t)0x01)
/* I2C_acknowledged_address */
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
/* I2C_registers */
#define I2C_Register_CTLR1 ((uint8_t)0x00)
#define I2C_Register_CTLR2 ((uint8_t)0x04)
#define I2C_Register_OADDR1 ((uint8_t)0x08)
#define I2C_Register_OADDR2 ((uint8_t)0x0C)
#define I2C_Register_DATAR ((uint8_t)0x10)
#define I2C_Register_STAR1 ((uint8_t)0x14)
#define I2C_Register_STAR2 ((uint8_t)0x18)
#define I2C_Register_CKCFGR ((uint8_t)0x1C)
#define I2C_Register_RTR ((uint8_t)0x20)
/* I2C_SMBus_alert_pin_level */
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
/* I2C_PEC_position */
#define I2C_PECPosition_Next ((uint16_t)0x0800)
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
/* I2C_NACK_position */
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
/* I2C_interrupts_definition */
#define I2C_IT_BUF ((uint16_t)0x0400)
#define I2C_IT_EVT ((uint16_t)0x0200)
#define I2C_IT_ERR ((uint16_t)0x0100)
/* I2C_interrupts_definition */
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
#define I2C_IT_PECERR ((uint32_t)0x01001000)
#define I2C_IT_OVR ((uint32_t)0x01000800)
#define I2C_IT_AF ((uint32_t)0x01000400)
#define I2C_IT_ARLO ((uint32_t)0x01000200)
#define I2C_IT_BERR ((uint32_t)0x01000100)
#define I2C_IT_TXE ((uint32_t)0x06000080)
#define I2C_IT_RXNE ((uint32_t)0x06000040)
#define I2C_IT_STOPF ((uint32_t)0x02000010)
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
#define I2C_IT_BTF ((uint32_t)0x02000004)
#define I2C_IT_ADDR ((uint32_t)0x02000002)
#define I2C_IT_SB ((uint32_t)0x02000001)
/* SR2 register flags */
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
/* SR1 register flags */
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
#define I2C_FLAG_AF ((uint32_t)0x10000400)
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
#define I2C_FLAG_SB ((uint32_t)0x10000001)
/****************I2C Master Events (Events grouped in order of communication)********************/
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/******************I2C Slave Events (Events grouped in order of communication)******************/
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
void I2C_DeInit(I2C_TypeDef* I2Cx);
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
/****************************************************************************************
* I2C State Monitoring Functions
****************************************************************************************/
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
#ifdef __cplusplus
}
#endif
#endif

120
libraries/sdk/Peripheral/ch32v30x_iwdg.c Normal file
View File

@@ -0,0 +1,120 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_iwdg.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the IWDG firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v30x_iwdg.h"
/* CTLR register bit mask */
#define CTLR_KEY_Reload ((uint16_t)0xAAAA)
#define CTLR_KEY_Enable ((uint16_t)0xCCCC)
/*********************************************************************
* @fn IWDG_WriteAccessCmd
*
* @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers.
*
* @param WDG_WriteAccess - new state of write access to IWDG_PSCR and
* IWDG_RLDR registers.
* IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and
* IWDG_RLDR registers.
* IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR
* and IWDG_RLDR registers.
*
* @return none
*/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
{
IWDG->CTLR = IWDG_WriteAccess;
}
/*********************************************************************
* @fn IWDG_SetPrescaler
*
* @brief Sets IWDG Prescaler value.
*
* @param IWDG_Prescaler - specifies the IWDG Prescaler value.
* IWDG_Prescaler_4 - IWDG prescaler set to 4.
* IWDG_Prescaler_8 - IWDG prescaler set to 8.
* IWDG_Prescaler_16 - IWDG prescaler set to 16.
* IWDG_Prescaler_32 - IWDG prescaler set to 32.
* IWDG_Prescaler_64 - IWDG prescaler set to 64.
* IWDG_Prescaler_128 - IWDG prescaler set to 128.
* IWDG_Prescaler_256 - IWDG prescaler set to 256.
*
* @return none
*/
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
{
IWDG->PSCR = IWDG_Prescaler;
}
/*********************************************************************
* @fn IWDG_SetReload
*
* @brief Sets IWDG Reload value.
*
* @param Reload - specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF.
*
* @return none
*/
void IWDG_SetReload(uint16_t Reload)
{
IWDG->RLDR = Reload;
}
/*********************************************************************
* @fn IWDG_ReloadCounter
*
* @brief Reloads IWDG counter with value defined in the reload register.
*
* @return none
*/
void IWDG_ReloadCounter(void)
{
IWDG->CTLR = CTLR_KEY_Reload;
}
/*********************************************************************
* @fn IWDG_Enable
*
* @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled).
*
* @return none
*/
void IWDG_Enable(void)
{
IWDG->CTLR = CTLR_KEY_Enable;
}
/*********************************************************************
* @fn IWDG_GetFlagStatus
*
* @brief Checks whether the specified IWDG flag is set or not.
*
* @param IWDG_FLAG - specifies the flag to check.
* IWDG_FLAG_PVU - Prescaler Value Update on going.
* IWDG_FLAG_RVU - Reload Value Update on going.
*
* @return none
*/
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
{
FlagStatus bitstatus = RESET;
if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}

56
libraries/sdk/Peripheral/ch32v30x_iwdg.h Normal file
View File

@@ -0,0 +1,56 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_iwdg.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* IWDG firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_IWDG_H
#define __CH32V30x_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* IWDG_WriteAccess */
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
/* IWDG_prescaler */
#define IWDG_Prescaler_4 ((uint8_t)0x00)
#define IWDG_Prescaler_8 ((uint8_t)0x01)
#define IWDG_Prescaler_16 ((uint8_t)0x02)
#define IWDG_Prescaler_32 ((uint8_t)0x03)
#define IWDG_Prescaler_64 ((uint8_t)0x04)
#define IWDG_Prescaler_128 ((uint8_t)0x05)
#define IWDG_Prescaler_256 ((uint8_t)0x06)
/* IWDG_Flag */
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
void IWDG_SetReload(uint16_t Reload);
void IWDG_ReloadCounter(void);
void IWDG_Enable(void);
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
#ifdef __cplusplus
}
#endif
#endif

84
libraries/sdk/Peripheral/ch32v30x_opa.c Normal file
View File

@@ -0,0 +1,84 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_opa.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the OPA firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
***************************************************************************************/
#include "ch32v30x_opa.h"
#define OPA_MASK ((uint32_t)0x000F)
#define OPA_Total_NUM 4
/*********************************************************************
* @fn OPA_DeInit
*
* @brief Deinitializes the OPA peripheral registers to their default
* reset values.
*
* @return none
*/
void OPA_DeInit(void)
{
OPA->CR = 0;
}
/*********************************************************************
* @fn OPA_Init
*
* @brief Initializes the OPA peripheral according to the specified
* parameters in the OPA_InitStruct.
*
* @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure
*
* @return none
*/
void OPA_Init(OPA_InitTypeDef *OPA_InitStruct)
{
uint32_t tmp = 0;
tmp = OPA->CR;
tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM));
tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM));
OPA->CR = tmp;
}
/*********************************************************************
* @fn OPA_StructInit
*
* @brief Fills each OPA_StructInit member with its reset value.
*
* @param OPA_StructInit - pointer to a OPA_InitTypeDef structure
*
* @return none
*/
void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct)
{
OPA_InitStruct->Mode = OUT_IO;
OPA_InitStruct->PSEL = CHP0;
OPA_InitStruct->NSEL = CHN0;
OPA_InitStruct->OPA_NUM = OPA1;
}
/*********************************************************************
* @fn OPA_Cmd
*
* @brief Enables or disables the specified OPA peripheral.
*
* @param OPA_NUM - Select OPA
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState)
{
if(NewState == ENABLE)
{
OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM));
}
else
{
OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM));
}
}

75
libraries/sdk/Peripheral/ch32v30x_opa.h Normal file
View File

@@ -0,0 +1,75 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_opa.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* OPA firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_OPA_H
#define __CH32V30x_OPA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
#define OPA_PSEL_OFFSET 3
#define OPA_NSEL_OFFSET 2
#define OPA_MODE_OFFSET 1
/* OPA member enumeration */
typedef enum
{
OPA1=0,
OPA2,
OPA3,
OPA4
}OPA_Num_TypeDef;
/* OPA PSEL enumeration */
typedef enum
{
CHP0=0,
CHP1
}OPA_PSEL_TypeDef;
/* OPA NSEL enumeration */
typedef enum
{
CHN0=0,
CHN1
}OPA_NSEL_TypeDef;
/* OPA Mode enumeration */
typedef enum
{
OUT_IO_ADC=0,
OUT_IO
}OPA_Mode_TypeDef;
/* OPA Init Structure definition */
typedef struct
{
OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */
OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */
OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */
OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */
}OPA_InitTypeDef;
void OPA_DeInit(void);
void OPA_Init(OPA_InitTypeDef* OPA_InitStruct);
void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct);
void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState);
#ifdef __cplusplus
}
#endif
#endif

321
libraries/sdk/Peripheral/ch32v30x_pwr.c Normal file
View File

@@ -0,0 +1,321 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_pwr.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the PWR firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
********************************************************************************/
#include "ch32v30x_pwr.h"
#include "ch32v30x_rcc.h"
/* PWR registers bit mask */
/* CTLR register bit mask */
#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC)
#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F)
/*********************************************************************
* @fn PWR_DeInit
*
* @brief Deinitializes the PWR peripheral registers to their default
* reset values.
*
* @return none
*/
void PWR_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
}
/*********************************************************************
* @fn PWR_BackupAccessCmd
*
* @brief Enables or disables access to the RTC and backup registers.
*
* @param NewState - new state of the access to the RTC and backup registers,
* This parameter can be: ENABLE or DISABLE.
*
* @return none
*/
void PWR_BackupAccessCmd(FunctionalState NewState)
{
if(NewState)
{
PWR->CTLR |= (1 << 8);
}
else
{
PWR->CTLR &= ~(1 << 8);
}
}
/*********************************************************************
* @fn PWR_PVDCmd
*
* @brief Enables or disables the Power Voltage Detector(PVD).
*
* @param NewState - new state of the PVD(ENABLE or DISABLE).
*
* @return none
*/
void PWR_PVDCmd(FunctionalState NewState)
{
if(NewState)
{
PWR->CTLR |= (1 << 4);
}
else
{
PWR->CTLR &= ~(1 << 4);
}
}
/*********************************************************************
* @fn PWR_PVDLevelConfig
*
* @brief Configures the voltage threshold detected by the Power Voltage
* Detector(PVD).
*
* @param PWR_PVDLevel - specifies the PVD detection level
* PWR_PVDLevel_2V2 - PVD detection level set to 2.2V
* PWR_PVDLevel_2V3 - PVD detection level set to 2.3V
* PWR_PVDLevel_2V4 - PVD detection level set to 2.4V
* PWR_PVDLevel_2V5 - PVD detection level set to 2.5V
* PWR_PVDLevel_2V6 - PVD detection level set to 2.6V
* PWR_PVDLevel_2V7 - PVD detection level set to 2.7V
* PWR_PVDLevel_2V8 - PVD detection level set to 2.8V
* PWR_PVDLevel_2V9 - PVD detection level set to 2.9V
*
* @return none
*/
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg &= CTLR_PLS_MASK;
tmpreg |= PWR_PVDLevel;
PWR->CTLR = tmpreg;
}
/*********************************************************************
* @fn PWR_WakeUpPinCmd
*
* @brief Enables or disables the WakeUp Pin functionality.
*
* @param NewState - new state of the WakeUp Pin functionality
* (ENABLE or DISABLE).
*
* @return none
*/
void PWR_WakeUpPinCmd(FunctionalState NewState)
{
if(NewState)
{
PWR->CSR |= (1 << 8);
}
else
{
PWR->CSR &= ~(1 << 8);
}
}
/*********************************************************************
* @fn PWR_EnterSTOPMode
*
* @brief Enters STOP mode.
*
* @param PWR_Regulator - specifies the regulator state in STOP mode.
* PWR_Regulator_ON - STOP mode with regulator ON
* PWR_Regulator_LowPower - STOP mode with regulator in low power mode
* PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
* PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
* PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
*
* @return none
*/
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg &= CTLR_DS_MASK;
tmpreg |= PWR_Regulator;
PWR->CTLR = tmpreg;
NVIC->SCTLR |= (1 << 2);
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
__WFI();
}
else
{
__WFE();
}
NVIC->SCTLR &= ~(1 << 2);
}
/*********************************************************************
* @fn PWR_EnterSTANDBYMode
*
* @brief Enters STANDBY mode.
*
* @return none
*/
void PWR_EnterSTANDBYMode(void)
{
PWR->CTLR |= PWR_CTLR_CWUF;
PWR->CTLR |= PWR_CTLR_PDDS;
NVIC->SCTLR |= (1 << 2);
__WFI();
}
/*********************************************************************
* @fn PWR_GetFlagStatus
*
* @brief Checks whether the specified PWR flag is set or not.
*
* @param PWR_FLAG - specifies the flag to check.
* PWR_FLAG_WU - Wake Up flag
* PWR_FLAG_SB - StandBy flag
* PWR_FLAG_PVDO - PVD Output
*
* @return none
*/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
{
FlagStatus bitstatus = RESET;
if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn PWR_ClearFlag
*
* @brief Clears the PWR's pending flags.
*
* @param PWR_FLAG - specifies the flag to clear.
* PWR_FLAG_WU - Wake Up flag
* PWR_FLAG_SB - StandBy flag
*
* @return none
*/
void PWR_ClearFlag(uint32_t PWR_FLAG)
{
PWR->CTLR |= PWR_FLAG << 2;
}
/*********************************************************************
* @fn PWR_EnterSTANDBYMode_RAM
*
* @brief Enters STANDBY mode with RAM data retention function on.
*
* @return none
*/
void PWR_EnterSTANDBYMode_RAM(void)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg |= PWR_CTLR_CWUF;
tmpreg |= PWR_CTLR_PDDS;
//2K+30K in standby w power.
tmpreg |= (0x1 << 16) | (0x1 << 17);
PWR->CTLR = tmpreg;
NVIC->SCTLR |= (1 << 2);
__WFI();
}
/*********************************************************************
* @fn PWR_EnterSTANDBYMode_RAM_LV
*
* @brief Enters STANDBY mode with RAM data retention function and LV mode on.
*
* @return none
*/
void PWR_EnterSTANDBYMode_RAM_LV(void)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg |= PWR_CTLR_CWUF;
tmpreg |= PWR_CTLR_PDDS;
//2K+30K in standby power.
tmpreg |= (0x1 << 16) | (0x1 << 17);
//2K+30K in standby LV .
tmpreg |= (0x1 << 20);
PWR->CTLR = tmpreg;
NVIC->SCTLR |= (1 << 2);
__WFI();
}
/*********************************************************************
* @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN
*
* @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable).
*
* @return none
*/
void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg |= PWR_CTLR_CWUF;
tmpreg |= PWR_CTLR_PDDS;
//2K+30K in standby power (VBAT Enable).
tmpreg |= (0x1 << 18) | (0x1 << 19);
PWR->CTLR = tmpreg;
NVIC->SCTLR |= (1 << 2);
__WFI();
}
/*********************************************************************
* @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN
*
* @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable).
*
* @return none
*/
void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg |= PWR_CTLR_CWUF;
tmpreg |= PWR_CTLR_PDDS;
//2K+30K in standby power (VBAT Enable).
tmpreg |= (0x1 << 18) | (0x1 << 19);
//2K+30K in standby LV .
tmpreg |= (0x1 << 20);
PWR->CTLR = tmpreg;
NVIC->SCTLR |= (1 << 2);
__WFI();
}

64
libraries/sdk/Peripheral/ch32v30x_pwr.h Normal file
View File

@@ -0,0 +1,64 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_pwr.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the PWR
* firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_PWR_H
#define __CH32V30x_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* PVD_detection_level */
#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
/* Regulator_state_is_STOP_mode */
#define PWR_Regulator_ON ((uint32_t)0x00000000)
#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
/* STOP_mode_entry */
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
/* PWR_Flag */
#define PWR_FLAG_WU ((uint32_t)0x00000001)
#define PWR_FLAG_SB ((uint32_t)0x00000002)
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
void PWR_DeInit(void);
void PWR_BackupAccessCmd(FunctionalState NewState);
void PWR_PVDCmd(FunctionalState NewState);
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_WakeUpPinCmd(FunctionalState NewState);
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
void PWR_ClearFlag(uint32_t PWR_FLAG);
void PWR_EnterSTANDBYMode_RAM(void);
void PWR_EnterSTANDBYMode_RAM_LV(void);
void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void);
void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void);
#ifdef __cplusplus
}
#endif
#endif

1424
libraries/sdk/Peripheral/ch32v30x_rcc.c Normal file
View File

File diff suppressed because it is too large Load Diff

456
libraries/sdk/Peripheral/ch32v30x_rcc.h Normal file
View File

@@ -0,0 +1,456 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_rcc.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the RCC firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_RCC_H
#define __CH32V30x_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* RCC_Exported_Types */
typedef struct
{
uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */
uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */
uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */
}RCC_ClocksTypeDef;
/* HSE_configuration */
#define RCC_HSE_OFF ((uint32_t)0x00000000)
#define RCC_HSE_ON ((uint32_t)0x00010000)
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
/* PLL_entry_clock_source */
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
#ifdef CH32V30x_D8
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
#else
#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
#endif
/* PLL_multiplication_factor */
#ifdef CH32V30x_D8
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
#define RCC_PLLMul_3 ((uint32_t)0x00040000)
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
#define RCC_PLLMul_10 ((uint32_t)0x00200000)
#define RCC_PLLMul_11 ((uint32_t)0x00240000)
#define RCC_PLLMul_12 ((uint32_t)0x00280000)
#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
#define RCC_PLLMul_18 ((uint32_t)0x003C0000)
#else
#define RCC_PLLMul_18_EXTEN ((uint32_t)0x00000000)
#define RCC_PLLMul_3_EXTEN ((uint32_t)0x00040000)
#define RCC_PLLMul_4_EXTEN ((uint32_t)0x00080000)
#define RCC_PLLMul_5_EXTEN ((uint32_t)0x000C0000)
#define RCC_PLLMul_6_EXTEN ((uint32_t)0x00100000)
#define RCC_PLLMul_7_EXTEN ((uint32_t)0x00140000)
#define RCC_PLLMul_8_EXTEN ((uint32_t)0x00180000)
#define RCC_PLLMul_9_EXTEN ((uint32_t)0x001C0000)
#define RCC_PLLMul_10_EXTEN ((uint32_t)0x00200000)
#define RCC_PLLMul_11_EXTEN ((uint32_t)0x00240000)
#define RCC_PLLMul_12_EXTEN ((uint32_t)0x00280000)
#define RCC_PLLMul_13_EXTEN ((uint32_t)0x002C0000)
#define RCC_PLLMul_14_EXTEN ((uint32_t)0x00300000)
#define RCC_PLLMul_6_5_EXTEN ((uint32_t)0x00340000)
#define RCC_PLLMul_15_EXTEN ((uint32_t)0x00380000)
#define RCC_PLLMul_16_EXTEN ((uint32_t)0x003C0000)
#endif
/* PREDIV1_division_factor */
#ifdef CH32V30x_D8C
#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
#endif
/* PREDIV1_clock_source */
#ifdef CH32V30x_D8C
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
#endif
/* PREDIV2_division_factor */
#ifdef CH32V30x_D8C
#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
#endif
/* PLL2_multiplication_factor */
#ifdef CH32V30x_D8C
#define RCC_PLL2Mul_2_5 ((uint32_t)0x00000000)
#define RCC_PLL2Mul_12_5 ((uint32_t)0x00000100)
#define RCC_PLL2Mul_4 ((uint32_t)0x00000200)
#define RCC_PLL2Mul_5 ((uint32_t)0x00000300)
#define RCC_PLL2Mul_6 ((uint32_t)0x00000400)
#define RCC_PLL2Mul_7 ((uint32_t)0x00000500)
#define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
#define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
#define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
#define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
#define RCC_PLL2Mul_15 ((uint32_t)0x00000D00)
#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
#endif
/* PLL3_multiplication_factor */
#ifdef CH32V30x_D8C
#define RCC_PLL3Mul_2_5 ((uint32_t)0x00000000)
#define RCC_PLL3Mul_12_5 ((uint32_t)0x00001000)
#define RCC_PLL3Mul_4 ((uint32_t)0x00002000)
#define RCC_PLL3Mul_5 ((uint32_t)0x00003000)
#define RCC_PLL3Mul_6 ((uint32_t)0x00004000)
#define RCC_PLL3Mul_7 ((uint32_t)0x00005000)
#define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
#define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
#define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
#define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
#define RCC_PLL3Mul_15 ((uint32_t)0x0000D000)
#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
#endif
/* System_clock_source */
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
/* AHB_clock_source */
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
/* APB1_APB2_clock_source */
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
/* RCC_Interrupt_source */
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_CSS ((uint8_t)0x80)
#ifdef CH32V30x_D8C
#define RCC_IT_PLL2RDY ((uint8_t)0x20)
#define RCC_IT_PLL3RDY ((uint8_t)0x40)
#endif
/* USB_OTG_FS_clock_source */
#define RCC_OTGFSCLKSource_PLLCLK_Div1 ((uint8_t)0x00)
#define RCC_OTGFSCLKSource_PLLCLK_Div2 ((uint8_t)0x01)
#define RCC_OTGFSCLKSource_PLLCLK_Div3 ((uint8_t)0x02)
/* I2S2_clock_source */
#ifdef CH32V30x_D8C
#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
#define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
#endif
/* I2S3_clock_source */
#ifdef CH32V30x_D8C
#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
#define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
#endif
/* ADC_clock_source */
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
/* LSE_configuration */
#define RCC_LSE_OFF ((uint8_t)0x00)
#define RCC_LSE_ON ((uint8_t)0x01)
#define RCC_LSE_Bypass ((uint8_t)0x04)
/* RTC_clock_source */
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
/* AHB_peripheral */
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200)
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800)
#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
#define RCC_AHBPeriph_DVP ((uint32_t)0x00002000)
#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
/* APB2_peripheral */
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
/* APB1_peripheral */
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040)
#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080)
#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100)
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
/* Clock_source_to_output_on_MCO_pin */
#define RCC_MCO_NoClock ((uint8_t)0x00)
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
#define RCC_MCO_HSI ((uint8_t)0x05)
#define RCC_MCO_HSE ((uint8_t)0x06)
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
#ifdef CH32V30x_D8C
#define RCC_MCO_PLL2CLK ((uint8_t)0x08)
#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
#define RCC_MCO_XT1 ((uint8_t)0x0A)
#define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
#endif
/* RCC_Flag */
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
#ifdef CH32V30x_D8C
#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
#endif
/* SysTick_clock_source */
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
/* RNG_clock_source */
#ifdef CH32V30x_D8C
#define RCC_RNGCLKSource_SYSCLK ((uint32_t)0x00)
#define RCC_RNGCLKSource_PLL3_VCO ((uint32_t)0x01)
#endif
/* ETH1G_clock_source */
#ifdef CH32V30x_D8C
#define RCC_ETH1GCLKSource_PLL2_VCO ((uint32_t)0x00)
#define RCC_ETH1GCLKSource_PLL3_VCO ((uint32_t)0x01)
#define RCC_ETH1GCLKSource_PB1_IN ((uint32_t)0x02)
#endif
/* USBFS_clock_source */
#ifdef CH32V30x_D8C
#define RCC_USBPLL_Div1 ((uint32_t)0x00)
#define RCC_USBPLL_Div2 ((uint32_t)0x01)
#define RCC_USBPLL_Div3 ((uint32_t)0x02)
#define RCC_USBPLL_Div4 ((uint32_t)0x03)
#define RCC_USBPLL_Div5 ((uint32_t)0x04)
#define RCC_USBPLL_Div6 ((uint32_t)0x05)
#define RCC_USBPLL_Div7 ((uint32_t)0x06)
#define RCC_USBPLL_Div8 ((uint32_t)0x07)
#endif
/* USBHSPLL_clock_source */
#ifdef CH32V30x_D8C
#define RCC_HSBHSPLLCLKSource_HSE ((uint32_t)0x00)
#define RCC_HSBHSPLLCLKSource_HSI ((uint32_t)0x01)
#endif
/* USBHSPLLCKREF_clock_select */
#ifdef CH32V30x_D8C
#define RCC_USBHSPLLCKREFCLK_3M ((uint32_t)0x00)
#define RCC_USBHSPLLCKREFCLK_4M ((uint32_t)0x01)
#define RCC_USBHSPLLCKREFCLK_8M ((uint32_t)0x02)
#define RCC_USBHSPLLCKREFCLK_5M ((uint32_t)0x03)
#endif
/* OTGUSBCLK48M_clock_source */
#define RCC_USBCLK48MCLKSource_PLLCLK ((uint32_t)0x00)
#define RCC_USBCLK48MCLKSource_USBPHY ((uint32_t)0x01)
void RCC_DeInit(void);
void RCC_HSEConfig(uint32_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(uint8_t RCC_MCO);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
void RCC_ADCCLKADJcmd(FunctionalState NewState);
void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource);
#ifdef CH32V30x_D8C
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
void RCC_PLL2Cmd(FunctionalState NewState);
void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
void RCC_PLL3Cmd(FunctionalState NewState);
void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource);
void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource);
void RCC_ETH1G_125Mcmd(FunctionalState NewState);
void RCC_USBHSConfig(uint32_t RCC_USBHS);
void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource);
void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource);
void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState);
#endif
#ifdef __cplusplus
}
#endif
#endif

152
libraries/sdk/Peripheral/ch32v30x_rng.c Normal file
View File

@@ -0,0 +1,152 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_rng.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the RNG firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
********************************************************************************/
#include "ch32v30x_rng.h"
#include "ch32v30x_rcc.h"
/*********************************************************************
* @fn RNG_Cmd
*
* @brief Enables or disables the RNG peripheral.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void RNG_Cmd(FunctionalState NewState)
{
if(NewState != DISABLE)
{
RNG->CR |= RNG_CR_RNGEN;
}
else
{
RNG->CR &= ~RNG_CR_RNGEN;
}
}
/*********************************************************************
* @fn RNG_GetRandomNumber
*
* @brief Returns a 32-bit random number.
*
* @return 32-bit random number.
*/
uint32_t RNG_GetRandomNumber(void)
{
return RNG->DR;
}
/*********************************************************************
* @fn RNG_ITConfig
*
* @brief Enables or disables the RNG interrupt.
*
* @param NewState - ENABLE or DISABLE.
*
* @return 32-bit random number.
*/
void RNG_ITConfig(FunctionalState NewState)
{
if(NewState != DISABLE)
{
RNG->CR |= RNG_CR_IE;
}
else
{
RNG->CR &= ~RNG_CR_IE;
}
}
/*********************************************************************
* @fn RNG_GetFlagStatus
*
* @brief Checks whether the specified RNG flag is set or not.
*
* @param RNG_FLAG - specifies the RNG flag to check.
* RNG_FLAG_DRDY - Data Ready flag.
* RNG_FLAG_CECS - Clock Error Current flag.
* RNG_FLAG_SECS - Seed Error Current flag.
*
* @return 32-bit random number.
*/
FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG)
{
FlagStatus bitstatus = RESET;
if((RNG->SR & RNG_FLAG) != (uint8_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn RNG_ClearFlag
*
* @brief Clears the RNG flags.
*
* @param RNG_FLAG - specifies the flag to clear.
* RNG_FLAG_CECS - Clock Error Current flag.
* RNG_FLAG_SECS - Seed Error Current flag.
*
* @return 32-bit random number.
*/
void RNG_ClearFlag(uint8_t RNG_FLAG)
{
RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4);
}
/*********************************************************************
* @fn RNG_GetFlagStatus
*
* @brief Checks whether the specified RNG interrupt has occurred or not.
*
* @param RNG_IT - specifies the RNG interrupt source to check.
* RNG_IT_CEI - Clock Error Interrupt.
* RNG_IT_SEI - Seed Error Interrupt.
*
* @return bitstatus<75><73>SET or RESET.
*/
ITStatus RNG_GetITStatus(uint8_t RNG_IT)
{
ITStatus bitstatus = RESET;
if((RNG->SR & RNG_IT) != (uint8_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn RNG_ClearITPendingBit
*
* @brief Clears the RNG interrupt pending bit(s).
*
* @param RNG_IT - specifies the RNG interrupt pending bit(s) to clear.
* RNG_IT_CEI - Clock Error Interrupt.
* RNG_IT_SEI - Seed Error Interrupt.
*
* @return None
*/
void RNG_ClearITPendingBit(uint8_t RNG_IT)
{
RNG->SR = (uint8_t)~RNG_IT;
}

41
libraries/sdk/Peripheral/ch32v30x_rng.h Normal file
View File

@@ -0,0 +1,41 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_rng.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* RNG firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_RNG_H
#define __CH32V30x_RNG_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* RNG_flags_definition*/
#define RNG_FLAG_DRDY ((uint8_t)0x0001) /* Data ready */
#define RNG_FLAG_CECS ((uint8_t)0x0002) /* Clock error current status */
#define RNG_FLAG_SECS ((uint8_t)0x0004) /* Seed error current status */
/* RNG_interrupts_definition */
#define RNG_IT_CEI ((uint8_t)0x20) /* Clock error interrupt */
#define RNG_IT_SEI ((uint8_t)0x40) /* Seed error interrupt */
void RNG_Cmd(FunctionalState NewState);
uint32_t RNG_GetRandomNumber(void);
void RNG_ITConfig(FunctionalState NewState);
FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
void RNG_ClearFlag(uint8_t RNG_FLAG);
ITStatus RNG_GetITStatus(uint8_t RNG_IT);
void RNG_ClearITPendingBit(uint8_t RNG_IT);
#ifdef __cplusplus
}
#endif
#endif

273
libraries/sdk/Peripheral/ch32v30x_rtc.c Normal file
View File

@@ -0,0 +1,273 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_rtc.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the RTC firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
********************************************************************************/
#include "ch32v30x_rtc.h"
/* RTC_Private_Defines */
#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */
#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */
/*********************************************************************
* @fn RTC_ITConfig
*
* @brief Enables or disables the specified RTC interrupts.
*
* @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled.
* RTC_IT_OW - Overflow interrupt
* RTC_IT_ALR - Alarm interrupt
* RTC_IT_SEC - Second interrupt
*
* @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE).
*/
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
{
if(NewState != DISABLE)
{
RTC->CTLRH |= RTC_IT;
}
else
{
RTC->CTLRH &= (uint16_t)~RTC_IT;
}
}
/*********************************************************************
* @fn RTC_EnterConfigMode
*
* @brief Enters the RTC configuration mode.
*
* @return none
*/
void RTC_EnterConfigMode(void)
{
RTC->CTLRL |= RTC_CTLRL_CNF;
}
/*********************************************************************
* @fn RTC_ExitConfigMode
*
* @brief Exits from the RTC configuration mode.
*
* @return none
*/
void RTC_ExitConfigMode(void)
{
RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF);
}
/*********************************************************************
* @fn RTC_GetCounter
*
* @brief Gets the RTC counter value
*
* @return RTC counter value
*/
uint32_t RTC_GetCounter(void)
{
uint16_t high1 = 0, high2 = 0, low = 0;
high1 = RTC->CNTH;
low = RTC->CNTL;
high2 = RTC->CNTH;
if(high1 != high2)
{
return (((uint32_t)high2 << 16) | RTC->CNTL);
}
else
{
return (((uint32_t)high1 << 16) | low);
}
}
/*********************************************************************
* @fn RTC_SetCounter
*
* @brief Sets the RTC counter value.
*
* @param CounterValue - RTC counter new value.
*
* @return RTC counter value
*/
void RTC_SetCounter(uint32_t CounterValue)
{
RTC_EnterConfigMode();
RTC->CNTH = CounterValue >> 16;
RTC->CNTL = (CounterValue & RTC_LSB_MASK);
RTC_ExitConfigMode();
}
/*********************************************************************
* @fn RTC_SetPrescaler
*
* @brief Sets the RTC prescaler value
*
* @param PrescalerValue - RTC prescaler new value
*
* @return none
*/
void RTC_SetPrescaler(uint32_t PrescalerValue)
{
RTC_EnterConfigMode();
RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK);
RTC_ExitConfigMode();
}
/*********************************************************************
* @fn RTC_SetAlarm
*
* @brief Sets the RTC alarm value
*
* @param AlarmValue - RTC alarm new value
*
* @return none
*/
void RTC_SetAlarm(uint32_t AlarmValue)
{
RTC_EnterConfigMode();
RTC->ALRMH = AlarmValue >> 16;
RTC->ALRML = (AlarmValue & RTC_LSB_MASK);
RTC_ExitConfigMode();
}
/*********************************************************************
* @fn RTC_GetDivider
*
* @brief Gets the RTC divider value
*
* @return RTC Divider value
*/
uint32_t RTC_GetDivider(void)
{
uint32_t tmp = 0x00;
tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
tmp |= RTC->DIVL;
return tmp;
}
/*********************************************************************
* @fn RTC_WaitForLastTask
*
* @brief Waits until last write operation on RTC registers has finished
*
* @return none
*/
void RTC_WaitForLastTask(void)
{
while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
{
}
}
/*********************************************************************
* @fn RTC_WaitForSynchro
*
* @brief Waits until the RTC registers are synchronized with RTC APB clock
*
* @return none
*/
void RTC_WaitForSynchro(void)
{
RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF;
while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET)
{
}
}
/*********************************************************************
* @fn RTC_GetFlagStatus
*
* @brief Checks whether the specified RTC flag is set or not
*
* @param RTC_FLAG- specifies the flag to check
* RTC_FLAG_RTOFF - RTC Operation OFF flag
* RTC_FLAG_RSF - Registers Synchronized flag
* RTC_FLAG_OW - Overflow flag
* RTC_FLAG_ALR - Alarm flag
* RTC_FLAG_SEC - Second flag
*
* @return none
*/
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
{
FlagStatus bitstatus = RESET;
if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn RTC_ClearFlag
*
* @brief Clears the RTC's pending flags
*
* @param RTC_FLAG - specifies the flag to clear
* RTC_FLAG_RSF - Registers Synchronized flag
* RTC_FLAG_OW - Overflow flag
* RTC_FLAG_ALR - Alarm flag
* RTC_FLAG_SEC - Second flag
*
* @return none
*/
void RTC_ClearFlag(uint16_t RTC_FLAG)
{
RTC->CTLRL &= (uint16_t)~RTC_FLAG;
}
/*********************************************************************
* @fn RTC_GetITStatus
*
* @brief Checks whether the specified RTC interrupt has occurred or not
*
* @param RTC_IT - specifies the RTC interrupts sources to check
* RTC_FLAG_OW - Overflow interrupt
* RTC_FLAG_ALR - Alarm interrupt
* RTC_FLAG_SEC - Second interrupt
*
* @return The new state of the RTC_IT (SET or RESET)
*/
ITStatus RTC_GetITStatus(uint16_t RTC_IT)
{
ITStatus bitstatus = RESET;
bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT);
if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn RTC_ClearITPendingBit
*
* @brief Clears the RTC's interrupt pending bits
*
* @param RTC_IT - specifies the interrupt pending bit to clear
* RTC_FLAG_OW - Overflow interrupt
* RTC_FLAG_ALR - Alarm interrupt
* RTC_FLAG_SEC - Second interrupt
*
* @return none
*/
void RTC_ClearITPendingBit(uint16_t RTC_IT)
{
RTC->CTLRL &= (uint16_t)~RTC_IT;
}

54
libraries/sdk/Peripheral/ch32v30x_rtc.h Normal file
View File

@@ -0,0 +1,54 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_rtc.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the RTC
* firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_RTC_H
#define __CH32V30x_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* RTC_interrupts_define */
#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */
#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */
#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */
/* RTC_interrupts_flags */
#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */
#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */
#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */
#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */
#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
void RTC_EnterConfigMode(void);
void RTC_ExitConfigMode(void);
uint32_t RTC_GetCounter(void);
void RTC_SetCounter(uint32_t CounterValue);
void RTC_SetPrescaler(uint32_t PrescalerValue);
void RTC_SetAlarm(uint32_t AlarmValue);
uint32_t RTC_GetDivider(void);
void RTC_WaitForLastTask(void);
void RTC_WaitForSynchro(void);
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
void RTC_ClearFlag(uint16_t RTC_FLAG);
ITStatus RTC_GetITStatus(uint16_t RTC_IT);
void RTC_ClearITPendingBit(uint16_t RTC_IT);
#ifdef __cplusplus
}
#endif
#endif

670
libraries/sdk/Peripheral/ch32v30x_sdio.c Normal file
View File

@@ -0,0 +1,670 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_SDIO.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the SDIO firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v30x_sdio.h"
#include "ch32v30x_rcc.h"
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
/* CLKCR register clear mask */
#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
/* SDIO PWRCTRL Mask */
#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
/* SDIO DCTRL Clear Mask */
#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
/* CMD Register clear mask */
#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
/* SDIO RESP Registers Address */
#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
/*********************************************************************
* @fn SDIO_DeInit
*
* @brief Deinitializes the SDIO peripheral registers to their default
* reset values.
*
* @return RTC counter value
*/
void SDIO_DeInit(void)
{
SDIO->POWER = 0x00000000;
SDIO->CLKCR = 0x00000000;
SDIO->ARG = 0x00000000;
SDIO->CMD = 0x00000000;
SDIO->DTIMER = 0x00000000;
SDIO->DLEN = 0x00000000;
SDIO->DCTRL = 0x00000000;
SDIO->ICR = 0x00C007FF;
SDIO->MASK = 0x00000000;
}
/*********************************************************************
* @fn SDIO_Init
*
* @brief Initializes the SDIO peripheral according to the specified
* parameters in the SDIO_InitStruct.
*
* @param SDIO_InitStruct - pointer to a SDIO_InitTypeDef structure
* that contains the configuration information for the SDIO peripheral.
*
* @return None
*/
void SDIO_Init(SDIO_InitTypeDef *SDIO_InitStruct)
{
uint32_t tmpreg = 0;
tmpreg = SDIO->CLKCR;
tmpreg &= CLKCR_CLEAR_MASK;
tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
SDIO->CLKCR = tmpreg;
}
/*********************************************************************
* @fn SDIO_StructInit
*
* @brief Fills each SDIO_InitStruct member with its default value.
*
* @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which
* will be initialized.
*
* @return none
*/
void SDIO_StructInit(SDIO_InitTypeDef *SDIO_InitStruct)
{
SDIO_InitStruct->SDIO_ClockDiv = 0x00;
SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
}
/*********************************************************************
* @fn SDIO_ClockCmd
*
* @brief Enables or disables the SDIO Clock.
*
* @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which
* will be initialized.
*
* @return none
*/
void SDIO_ClockCmd(FunctionalState NewState)
{
if(NewState)
SDIO->CLKCR |= (1 << 8);
else
SDIO->CLKCR &= ~(1 << 8);
}
/*********************************************************************
* @fn SDIO_SetPowerState
*
* @brief Sets the power status of the controller.
*
* @param SDIO_PowerState - new state of the Power state.
* SDIO_PowerState_OFF
* SDIO_PowerState_ON
*
* @return none
*/
void SDIO_SetPowerState(uint32_t SDIO_PowerState)
{
SDIO->POWER &= PWR_PWRCTRL_MASK;
SDIO->POWER |= SDIO_PowerState;
}
/*********************************************************************
* @fn SDIO_GetPowerState
*
* @brief Gets the power status of the controller.
*
* @param CounterValue - RTC counter new value.
*
* @return power state -
* 0x00 - Power OFF
* 0x02 - Power UP
* 0x03 - Power ON
*/
uint32_t SDIO_GetPowerState(void)
{
return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
}
/*********************************************************************
* @fn SDIO_ITConfig
*
* @brief Enables or disables the SDIO interrupts.
*
* @param DIO_IT - specifies the SDIO interrupt sources to be enabled or disabled.
* SDIO_IT_CCRCFAIL
* SDIO_IT_DCRCFAIL
* SDIO_IT_CTIMEOUT
* SDIO_IT_DTIMEOUT
* SDIO_IT_TXUNDERR
* SDIO_IT_RXOVERR
* SDIO_IT_CMDREND
* SDIO_IT_CMDSENT
* SDIO_IT_DATAEND
* SDIO_IT_STBITERR
* SDIO_IT_DBCKEND
* SDIO_IT_CMDACT
* SDIO_IT_TXACT
* SDIO_IT_RXACT
* SDIO_IT_TXFIFOHE
* SDIO_IT_RXFIFOHF
* SDIO_IT_TXFIFOF
* SDIO_IT_RXFIFOF
* SDIO_IT_TXFIFOE
* SDIO_IT_RXFIFOE
* SDIO_IT_TXDAVL
* SDIO_IT_RXDAVL
* SDIO_IT_SDIOIT
* SDIO_IT_CEATAEND
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
{
if(NewState != DISABLE)
{
SDIO->MASK |= SDIO_IT;
}
else
{
SDIO->MASK &= ~SDIO_IT;
}
}
/*********************************************************************
* @fn SDIO_DMACmd
*
* @brief Enables or disables the SDIO DMA request.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void SDIO_DMACmd(FunctionalState NewState)
{
if(NewState)
SDIO->DCTRL |= (1 << 3);
else
SDIO->DCTRL &= ~(1 << 3);
}
/*********************************************************************
* @fn SDIO_SendCommand
*
* @brief Initializes the SDIO Command according to the specified
* parameters in the SDIO_CmdInitStruct and send the command.
* @param SDIO_CmdInitStruct - pointer to a SDIO_CmdInitTypeDef
* structure that contains the configuration information for
* ddthe SDIO command.
*
* @return none
*/
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
{
uint32_t tmpreg = 0;
SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
tmpreg = SDIO->CMD;
tmpreg &= CMD_CLEAR_MASK;
tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
SDIO->CMD = tmpreg;
}
/*********************************************************************
* @fn SDIO_CmdStructInit
*
* @brief Fills each SDIO_CmdInitStruct member with its default value.
*
* @param SDIO_CmdInitStruct - pointer to an SDIO_CmdInitTypeDef
* structure which will be initialized.
*
* @return none
*/
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
{
SDIO_CmdInitStruct->SDIO_Argument = 0x00;
SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
}
/*********************************************************************
* @fn SDIO_GetCommandResponse
*
* @brief Returns command index of last command for which response received.
*
* @return Returns the command index of the last command response received.
*/
uint8_t SDIO_GetCommandResponse(void)
{
return (uint8_t)(SDIO->RESPCMD);
}
/*********************************************************************
* @fn SDIO_GetResponse
*
* @brief Returns response received from the card for the last command.
*
* @param SDIO_RESP - Specifies the SDIO response register.
* SDIO_RESP1 - Response Register 1
* SDIO_RESP2 - Response Register 2
* SDIO_RESP3 - Response Register 3
* SDIO_RESP4 - Response Register 4
*
* @return Returns the command index of the last command response received.
*/
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
{
__IO uint32_t tmp = 0;
tmp = SDIO_RESP_ADDR + SDIO_RESP;
return (*(__IO uint32_t *)tmp);
}
/*********************************************************************
* @fn SDIO_DataConfig
*
* @brief Initializes the SDIO data path according to the specified
*
* @param SDIO_DataInitStruct - pointer to a SDIO_DataInitTypeDef structure that
* contains the configuration information for the SDIO command.
*
* @return none
*/
void SDIO_DataConfig(SDIO_DataInitTypeDef *SDIO_DataInitStruct)
{
uint32_t tmpreg = 0;
SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
tmpreg = SDIO->DCTRL;
tmpreg &= DCTRL_CLEAR_MASK;
tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
SDIO->DCTRL = tmpreg;
}
/*********************************************************************
* @fn SDIO_DataStructInit
*
* @brief Fills each SDIO_DataInitStruct member with its default value.
*
* @param SDIO_DataInitStruct - pointer to an SDIO_DataInitTypeDef
* structure which will be initialized.
*
* @return RTC counter value
*/
void SDIO_DataStructInit(SDIO_DataInitTypeDef *SDIO_DataInitStruct)
{
SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
SDIO_DataInitStruct->SDIO_DataLength = 0x00;
SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
}
/*********************************************************************
* @fn SDIO_GetDataCounter
*
* @brief Returns number of remaining data bytes to be transferred.
*
* @return Number of remaining data bytes to be transferred
*/
uint32_t SDIO_GetDataCounter(void)
{
return SDIO->DCOUNT;
}
/*********************************************************************
* @fn SDIO_ReadData
*
* @brief Read one data word from Rx FIFO.
*
* @return Data received
*/
uint32_t SDIO_ReadData(void)
{
return SDIO->FIFO;
}
/*********************************************************************
* @fn SDIO_WriteData
*
* @brief Write one data word to Tx FIFO.
*
* @param Data - 32-bit data word to write.
*
* @return RTC counter value
*/
void SDIO_WriteData(uint32_t Data)
{
SDIO->FIFO = Data;
}
/*********************************************************************
* @fn SDIO_GetFIFOCount
*
* @brief Returns the number of words left to be written to or read from FIFO.
*
* @return Remaining number of words.
*/
uint32_t SDIO_GetFIFOCount(void)
{
return SDIO->FIFOCNT;
}
/*********************************************************************
* @fn SDIO_StartSDIOReadWait
*
* @brief Starts the SD I/O Read Wait operation.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void SDIO_StartSDIOReadWait(FunctionalState NewState)
{
if(NewState)
SDIO->DCTRL |= (1 << 8);
else
SDIO->DCTRL &= ~(1 << 8);
}
/*********************************************************************
* @fn SDIO_StopSDIOReadWait
*
* @brief Stops the SD I/O Read Wait operation.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void SDIO_StopSDIOReadWait(FunctionalState NewState)
{
if(NewState)
SDIO->DCTRL |= (1 << 9);
else
SDIO->DCTRL &= ~(1 << 9);
}
/*********************************************************************
* @fn SDIO_SetSDIOReadWaitMode
*
* @brief Sets one of the two options of inserting read wait interval.
*
* @param SDIO_ReadWaitMode - SD I/O Read Wait operation mode.
* SDIO_ReadWaitMode_CLK - Read Wait control by stopping SDIOCLK
* SDIO_ReadWaitMode_DATA2 - Read Wait control using SDIO_DATA2
*
* @return none
*/
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
{
if(SDIO_ReadWaitMode)
SDIO->DCTRL |= (1 << 10);
else
SDIO->DCTRL &= ~(1 << 10);
}
/*********************************************************************
* @fn SDIO_SetSDIOOperation
*
* @brief Enables or disables the SD I/O Mode Operation.
*
* @param NewState: ENABLE or DISABLE.
*
* @return none
*/
void SDIO_SetSDIOOperation(FunctionalState NewState)
{
if(NewState)
SDIO->DCTRL |= (1 << 11);
else
SDIO->DCTRL &= ~(1 << 11);
}
/*********************************************************************
* @fn SDIO_SendSDIOSuspendCmd
*
* @brief Enables or disables the SD I/O Mode suspend command sending.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
{
if(NewState)
SDIO->CMD |= (1 << 11);
else
SDIO->CMD &= ~(1 << 11);
}
/*********************************************************************
* @fn SDIO_CommandCompletionCmd
*
* @brief Enables or disables the command completion signal.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void SDIO_CommandCompletionCmd(FunctionalState NewState)
{
if(NewState)
SDIO->CMD |= (1 << 12);
else
SDIO->CMD &= ~(1 << 12);
}
/*********************************************************************
* @fn SDIO_CEATAITCmd
*
* @brief Enables or disables the CE-ATA interrupt.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void SDIO_CEATAITCmd(FunctionalState NewState)
{
if(NewState)
SDIO->CMD |= (1 << 13);
else
SDIO->CMD &= ~(1 << 13);
}
/*********************************************************************
* @fn SDIO_SendCEATACmd
*
* @brief Sends CE-ATA command (CMD61).
*
* @param NewState - ENABLE or DISABLE.
*
* @return RTC counter value
*/
void SDIO_SendCEATACmd(FunctionalState NewState)
{
if(NewState)
SDIO->CMD |= (1 << 14);
else
SDIO->CMD &= ~(1 << 14);
}
/*********************************************************************
* @fn SDIO_GetFlagStatus
*
* @brief Checks whether the specified SDIO flag is set or not.
*
* @param SDIO_FLAG - specifies the flag to check.
* SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed)
* SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed)
* SDIO_FLAG_CTIMEOUT - Command response timeout
* SDIO_FLAG_DTIMEOUT - Data timeout
* SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error
* SDIO_FLAG_RXOVERR - Received FIFO overrun error
* SDIO_FLAG_CMDREND - Command response received (CRC check passed)
* SDIO_FLAG_CMDSENT - Command sent (no response required)
* SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero)
* SDIO_FLAG_STBITERR - Start bit not detected on all data signals
* in wide bus mode.
* SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed)
* SDIO_FLAG_CMDACT - Command transfer in progress
* SDIO_FLAG_TXACT - Data transmit in progress
* SDIO_FLAG_RXACT - Data receive in progress
* SDIO_FLAG_TXFIFOHE - Transmit FIFO Half Empty
* SDIO_FLAG_RXFIFOHF - Receive FIFO Half Full
* SDIO_FLAG_TXFIFOF - Transmit FIFO full
* SDIO_FLAG_RXFIFOF - Receive FIFO full
* SDIO_FLAG_TXFIFOE - Transmit FIFO empty
* SDIO_FLAG_RXFIFOE - Receive FIFO empty
* SDIO_FLAG_TXDAVL - Data available in transmit FIFO
* SDIO_FLAG_RXDAVL - Data available in receive FIFO
* SDIO_FLAG_SDIOIT - SD I/O interrupt received
* SDIO_FLAG_CEATAEND - CE-ATA command completion signal received
* for CMD61
*
* @return ITStatus - SET or RESET
*/
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
{
FlagStatus bitstatus = RESET;
if((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn SDIO_ClearFlag
*
* @brief Clears the SDIO's pending flags.
*
* @param SDIO_FLAG - specifies the flag to clear.
* SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed)
* SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed)
* SDIO_FLAG_CTIMEOUT - Command response timeout
* SDIO_FLAG_DTIMEOUT - Data timeout
* SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error
* SDIO_FLAG_RXOVERR - Received FIFO overrun error
* SDIO_FLAG_CMDREND - Command response received (CRC check passed)
* SDIO_FLAG_CMDSENT - Command sent (no response required)
* SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero)
* SDIO_FLAG_STBITERR - Start bit not detected on all data signals
* in wide bus mode
* SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed)
* SDIO_FLAG_SDIOIT - SD I/O interrupt received
* SDIO_FLAG_CEATAEND - CE-ATA command completion signal received for CMD61
*
* @return none
*/
void SDIO_ClearFlag(uint32_t SDIO_FLAG)
{
SDIO->ICR = SDIO_FLAG;
}
/*********************************************************************
* @fn SDIO_GetITStatus
*
* @brief Checks whether the specified SDIO interrupt has occurred or not.
*
* @param SDIO_IT: specifies the SDIO interrupt source to check.
* SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt
* SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt
* SDIO_IT_CTIMEOUT - Command response timeout interrupt
* SDIO_IT_DTIMEOUT - Data timeout interrupt
* SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt
* SDIO_IT_RXOVERR - Received FIFO overrun error interrupt
* SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt
* SDIO_IT_CMDSENT - Command sent (no response required) interrupt
* SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt
* SDIO_IT_STBITERR - Start bit not detected on all data signals in wide
* bus mode interrupt
* SDIO_IT_DBCKEND - Data block sent/received (CRC check passed) interrupt
* SDIO_IT_CMDACT - Command transfer in progress interrupt
* SDIO_IT_TXACT - Data transmit in progress interrupt
* SDIO_IT_RXACT - Data receive in progress interrupt
* SDIO_IT_TXFIFOHE - Transmit FIFO Half Empty interrupt
* SDIO_IT_RXFIFOHF - Receive FIFO Half Full interrupt
* SDIO_IT_TXFIFOF - Transmit FIFO full interrupt
* SDIO_IT_RXFIFOF - Receive FIFO full interrupt
* SDIO_IT_TXFIFOE - Transmit FIFO empty interrupt
* SDIO_IT_RXFIFOE - Receive FIFO empty interrupt
* SDIO_IT_TXDAVL - Data available in transmit FIFO interrupt
* SDIO_IT_RXDAVL - Data available in receive FIFO interrupt
* SDIO_IT_SDIOIT - SD I/O interrupt received interrupt
* SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61 interrupt
*
* @return ITStatus<75><73>SET or RESET
*/
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
{
ITStatus bitstatus = RESET;
if((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn SDIO_ClearITPendingBit
*
* @brief Clears the SDIO's interrupt pending bits.
*
* @param SDIO_IT - specifies the interrupt pending bit to clear.
* SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt
* SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt
* SDIO_IT_CTIMEOUT - Command response timeout interrupt
* SDIO_IT_DTIMEOUT - Data timeout interrupt
* SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt
* SDIO_IT_RXOVERR - Received FIFO overrun error interrupt
* SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt
* SDIO_IT_CMDSENT - Command sent (no response required) interrupt
* SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt
* SDIO_IT_STBITERR - Start bit not detected on all data signals in wide
* bus mode interrupt
* SDIO_IT_SDIOIT - SD I/O interrupt received interrupt
* SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61
*
* @return RTC counter value
*/
void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
{
SDIO->ICR = SDIO_IT;
}

254
libraries/sdk/Peripheral/ch32v30x_sdio.h Normal file
View File

@@ -0,0 +1,254 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_sdio.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the SDIO
* firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_SDIO_H
#define __CH32V30x_SDIO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* SDIO Init structure definition */
typedef struct
{
uint32_t SDIO_ClockEdge; /* Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref SDIO_Clock_Edge */
uint32_t SDIO_ClockBypass; /* Specifies whether the SDIO Clock divider bypass is
enabled or disabled.
This parameter can be a value of @ref SDIO_Clock_Bypass */
uint32_t SDIO_ClockPowerSave; /* Specifies whether SDIO Clock output is enabled or
disabled when the bus is idle.
This parameter can be a value of @ref SDIO_Clock_Power_Save */
uint32_t SDIO_BusWide; /* Specifies the SDIO bus width.
This parameter can be a value of @ref SDIO_Bus_Wide */
uint32_t SDIO_HardwareFlowControl; /* Specifies whether the SDIO hardware flow control is enabled or disabled.
This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
uint8_t SDIO_ClockDiv; /* Specifies the clock frequency of the SDIO controller.
This parameter can be a value between 0x00 and 0xFF. */
} SDIO_InitTypeDef;
typedef struct
{
uint32_t SDIO_Argument; /* Specifies the SDIO command argument which is sent
to a card as part of a command message. If a command
contains an argument, it must be loaded into this register
before writing the command to the command register */
uint32_t SDIO_CmdIndex; /* Specifies the SDIO command index. It must be lower than 0x40. */
uint32_t SDIO_Response; /* Specifies the SDIO response type.
This parameter can be a value of @ref SDIO_Response_Type */
uint32_t SDIO_Wait; /* Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
uint32_t SDIO_CPSM; /* Specifies whether SDIO Command path state machine (CPSM)
is enabled or disabled.
This parameter can be a value of @ref SDIO_CPSM_State */
} SDIO_CmdInitTypeDef;
typedef struct
{
uint32_t SDIO_DataTimeOut; /* Specifies the data timeout period in card bus clock periods. */
uint32_t SDIO_DataLength; /* Specifies the number of data bytes to be transferred. */
uint32_t SDIO_DataBlockSize; /* Specifies the data block size for block transfer.
This parameter can be a value of @ref SDIO_Data_Block_Size */
uint32_t SDIO_TransferDir; /* Specifies the data transfer direction, whether the transfer
is a read or write.
This parameter can be a value of @ref SDIO_Transfer_Direction */
uint32_t SDIO_TransferMode; /* Specifies whether data transfer is in stream or block mode.
This parameter can be a value of @ref SDIO_Transfer_Type */
uint32_t SDIO_DPSM; /* Specifies whether SDIO Data path state machine (DPSM)
is enabled or disabled.
This parameter can be a value of @ref SDIO_DPSM_State */
} SDIO_DataInitTypeDef;
/* SDIO_Clock_Edge */
#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
/* SDIO_Clock_Bypass */
#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
/* SDIO_Clock_Power_Save */
#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
/* SDIO_Bus_Wide */
#define SDIO_BusWide_1b ((uint32_t)0x00000000)
#define SDIO_BusWide_4b ((uint32_t)0x00000800)
#define SDIO_BusWide_8b ((uint32_t)0x00001000)
/* SDIO_Hardware_Flow_Control */
#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
/* SDIO_Power_State */
#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
#define SDIO_PowerState_ON ((uint32_t)0x00000003)
/* SDIO_Interrupt_sources */
#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
#define SDIO_IT_TXACT ((uint32_t)0x00001000)
#define SDIO_IT_RXACT ((uint32_t)0x00002000)
#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
/* SDIO_Response_Type */
#define SDIO_Response_No ((uint32_t)0x00000000)
#define SDIO_Response_Short ((uint32_t)0x00000040)
#define SDIO_Response_Long ((uint32_t)0x000000C0)
/* SDIO_Wait_Interrupt_State */
#define SDIO_Wait_No ((uint32_t)0x00000000)
#define SDIO_Wait_IT ((uint32_t)0x00000100)
#define SDIO_Wait_Pend ((uint32_t)0x00000200)
/* SDIO_CPSM_State */
#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
/* SDIO_Response_Registers */
#define SDIO_RESP1 ((uint32_t)0x00000000)
#define SDIO_RESP2 ((uint32_t)0x00000004)
#define SDIO_RESP3 ((uint32_t)0x00000008)
#define SDIO_RESP4 ((uint32_t)0x0000000C)
/* SDIO_Data_Block_Size */
#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
/* SDIO_Transfer_Direction */
#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
/* SDIO_Transfer_Type */
#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
/* SDIO_DPSM_State */
#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
/* SDIO_Flags */
#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
/* SDIO_Read_Wait_Mode */
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
void SDIO_DeInit(void);
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_ClockCmd(FunctionalState NewState);
void SDIO_SetPowerState(uint32_t SDIO_PowerState);
uint32_t SDIO_GetPowerState(void);
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
void SDIO_DMACmd(FunctionalState NewState);
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
uint8_t SDIO_GetCommandResponse(void);
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
uint32_t SDIO_GetDataCounter(void);
uint32_t SDIO_ReadData(void);
void SDIO_WriteData(uint32_t Data);
uint32_t SDIO_GetFIFOCount(void);
void SDIO_StartSDIOReadWait(FunctionalState NewState);
void SDIO_StopSDIOReadWait(FunctionalState NewState);
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
void SDIO_SetSDIOOperation(FunctionalState NewState);
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
void SDIO_CommandCompletionCmd(FunctionalState NewState);
void SDIO_CEATAITCmd(FunctionalState NewState);
void SDIO_SendCEATACmd(FunctionalState NewState);
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
void SDIO_ClearFlag(uint32_t SDIO_FLAG);
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
#ifdef __cplusplus
}
#endif
#endif

646
libraries/sdk/Peripheral/ch32v30x_spi.c Normal file
View File

@@ -0,0 +1,646 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_spi.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the SPI firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*********************************************************************************/
#include "ch32v30x_spi.h"
#include "ch32v30x_rcc.h"
/* SPI SPE mask */
#define CTLR1_SPE_Set ((uint16_t)0x0040)
#define CTLR1_SPE_Reset ((uint16_t)0xFFBF)
/* I2S I2SE mask */
#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
/* SPI CRCNext mask */
#define CTLR1_CRCNext_Set ((uint16_t)0x1000)
/* SPI CRCEN mask */
#define CTLR1_CRCEN_Set ((uint16_t)0x2000)
#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF)
/* SPI SSOE mask */
#define CTLR2_SSOE_Set ((uint16_t)0x0004)
#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB)
/* SPI registers Masks */
#define CTLR1_CLEAR_Mask ((uint16_t)0x3040)
#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
/* SPI or I2S mode selection masks */
#define SPI_Mode_Select ((uint16_t)0xF7FF)
#define I2S_Mode_Select ((uint16_t)0x0800)
/* I2S clock source selection masks */
#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
/*********************************************************************
* @fn SPI_I2S_DeInit
*
* @brief Deinitializes the SPIx peripheral registers to their default
* reset values (Affects also the I2Ss).
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
*
* @return none
*/
void SPI_I2S_DeInit(SPI_TypeDef *SPIx)
{
if(SPIx == SPI1)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
}
else if(SPIx == SPI2)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
}
else
{
if(SPIx == SPI3)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
}
}
}
/*********************************************************************
* @fn SPI_Init
*
* @brief Initializes the SPIx peripheral according to the specified
* parameters in the SPI_InitStruct.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_InitStruct - pointer to a SPI_InitTypeDef structure that
* contains the configuration information for the specified SPI peripheral.
*
* @return none
*/
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
{
uint16_t tmpreg = 0;
tmpreg = SPIx->CTLR1;
tmpreg &= CTLR1_CLEAR_Mask;
tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
SPIx->CTLR1 = tmpreg;
SPIx->I2SCFGR &= SPI_Mode_Select;
SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial;
}
/*********************************************************************
* @fn I2S_Init
*
* @brief Initializes the SPIx peripheral according to the specified
* parameters in the I2S_InitStruct.
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* (configured in I2S mode).
* I2S_InitStruct - pointer to an I2S_InitTypeDef structure that
* contains the configuration information for the specified SPI peripheral
* configured in I2S mode.
* @return none
*/
void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
{
uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
uint32_t tmp = 0;
RCC_ClocksTypeDef RCC_Clocks;
uint32_t sourceclock = 0;
SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
SPIx->I2SPR = 0x0002;
tmpreg = SPIx->I2SCFGR;
if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
{
i2sodd = (uint16_t)0;
i2sdiv = (uint16_t)2;
}
else
{
if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
{
packetlength = 1;
}
else
{
packetlength = 2;
}
if(((uint32_t)SPIx) == SPI2_BASE)
{
tmp = I2S2_CLOCK_SRC;
}
else
{
tmp = I2S3_CLOCK_SRC;
}
RCC_GetClocksFreq(&RCC_Clocks);
sourceclock = RCC_Clocks.SYSCLK_Frequency;
if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
{
tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
}
else
{
tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
}
tmp = tmp / 10;
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
i2sodd = (uint16_t)(i2sodd << 8);
}
if((i2sdiv < 2) || (i2sdiv > 0xFF))
{
i2sdiv = 2;
i2sodd = 0;
}
SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode |
(uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat |
(uint16_t)I2S_InitStruct->I2S_CPOL))));
SPIx->I2SCFGR = tmpreg;
}
/*********************************************************************
* @fn SPI_StructInit
*
* @brief Fills each SPI_InitStruct member with its default value.
*
* @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which
* will be initialized.
*
* @return none
*/
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
{
SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStruct->SPI_CRCPolynomial = 7;
}
/*********************************************************************
* @fn I2S_StructInit
*
* @brief Fills each I2S_InitStruct member with its default value.
*
* @param I2S_InitStruct - pointer to a I2S_InitTypeDef structure which
* will be initialized.
*
* @return none
*/
void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
{
I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
}
/*********************************************************************
* @fn SPI_Cmd
*
* @brief Enables or disables the specified SPI peripheral.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
SPIx->CTLR1 |= CTLR1_SPE_Set;
}
else
{
SPIx->CTLR1 &= CTLR1_SPE_Reset;
}
}
/*********************************************************************
* @fn I2S_Cmd
*
* @brief Enables or disables the specified SPI peripheral (in I2S mode).
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
}
else
{
SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
}
}
/*********************************************************************
* @fn SPI_I2S_ITConfig
*
* @brief Enables or disables the specified SPI/I2S interrupts.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_IT - specifies the SPI/I2S interrupt source to be
* enabled or disabled.
* SPI_I2S_IT_TXE - Tx buffer empty interrupt mask.
* SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask.
* SPI_I2S_IT_ERR - Error interrupt mask.
* NewState: ENABLE or DISABLE.
* @return none
*/
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
{
uint16_t itpos = 0, itmask = 0;
itpos = SPI_I2S_IT >> 4;
itmask = (uint16_t)1 << (uint16_t)itpos;
if(NewState != DISABLE)
{
SPIx->CTLR2 |= itmask;
}
else
{
SPIx->CTLR2 &= (uint16_t)~itmask;
}
}
/*********************************************************************
* @fn SPI_I2S_DMACmd
*
* @brief Enables or disables the SPIx/I2Sx DMA interface.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to
* be enabled or disabled.
* SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request.
* SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
{
if(NewState != DISABLE)
{
SPIx->CTLR2 |= SPI_I2S_DMAReq;
}
else
{
SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq;
}
}
/*********************************************************************
* @fn SPI_I2S_SendData
*
* @brief Transmits a Data through the SPIx/I2Sx peripheral.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* Data - Data to be transmitted.
*
* @return none
*/
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data)
{
SPIx->DATAR = Data;
}
/*********************************************************************
* @fn SPI_I2S_ReceiveData
*
* @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* Data - Data to be transmitted.
*
* @return SPIx->DATAR - The value of the received data.
*/
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx)
{
return SPIx->DATAR;
}
/*********************************************************************
* @fn SPI_NSSInternalSoftwareConfig
*
* @brief Configures internally by software the NSS pin for the selected SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_NSSInternalSoft -
* SPI_NSSInternalSoft_Set - Set NSS pin internally.
* SPI_NSSInternalSoft_Reset - Reset NSS pin internally.
*
* @return none
*/
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
{
if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
{
SPIx->CTLR1 |= SPI_NSSInternalSoft_Set;
}
else
{
SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset;
}
}
/*********************************************************************
* @fn SPI_SSOutputCmd
*
* @brief Enables or disables the SS output for the selected SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* NewState - new state of the SPIx SS output.
*
* @return none
*/
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
SPIx->CTLR2 |= CTLR2_SSOE_Set;
}
else
{
SPIx->CTLR2 &= CTLR2_SSOE_Reset;
}
}
/*********************************************************************
* @fn SPI_DataSizeConfig
*
* @brief Configures the data size for the selected SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_DataSize - specifies the SPI data size.
* SPI_DataSize_16b - Set data frame format to 16bit.
* SPI_DataSize_8b - Set data frame format to 8bit.
*
* @return none
*/
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
{
SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b;
SPIx->CTLR1 |= SPI_DataSize;
}
/*********************************************************************
* @fn SPI_TransmitCRC
*
* @brief Transmit the SPIx CRC value.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
*
* @return none
*/
void SPI_TransmitCRC(SPI_TypeDef *SPIx)
{
SPIx->CTLR1 |= CTLR1_CRCNext_Set;
}
/*********************************************************************
* @fn SPI_CalculateCRC
*
* @brief Enables or disables the CRC value calculation of the transferred bytes.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* NewState - new state of the SPIx CRC value calculation.
*
* @return none
*/
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
SPIx->CTLR1 |= CTLR1_CRCEN_Set;
}
else
{
SPIx->CTLR1 &= CTLR1_CRCEN_Reset;
}
}
/*********************************************************************
* @fn SPI_GetCRC
*
* @brief Returns the transmit or the receive CRC register value for the specified SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_CRC - specifies the CRC register to be read.
* SPI_CRC_Tx - Selects Tx CRC register.
* SPI_CRC_Rx - Selects Rx CRC register.
*
* @return crcreg: The selected CRC register value.
*/
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC)
{
uint16_t crcreg = 0;
if(SPI_CRC != SPI_CRC_Rx)
{
crcreg = SPIx->TCRCR;
}
else
{
crcreg = SPIx->RCRCR;
}
return crcreg;
}
/*********************************************************************
* @fn SPI_GetCRCPolynomial
*
* @brief Returns the CRC Polynomial register value for the specified SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
*
* @return SPIx->CRCR - The CRC Polynomial register value.
*/
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
{
return SPIx->CRCR;
}
/*********************************************************************
* @fn SPI_BiDirectionalLineConfig
*
* @brief Selects the data transfer direction in bi-directional mode
* for the specified SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_Direction - specifies the data transfer direction in
* bi-directional mode.
* SPI_Direction_Tx - Selects Tx transmission direction.
* SPI_Direction_Rx - Selects Rx receive direction.
*
* @return none
*/
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction)
{
if(SPI_Direction == SPI_Direction_Tx)
{
SPIx->CTLR1 |= SPI_Direction_Tx;
}
else
{
SPIx->CTLR1 &= SPI_Direction_Rx;
}
}
/*********************************************************************
* @fn SPI_I2S_GetFlagStatus
*
* @brief Checks whether the specified SPI/I2S flag is set or not.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_FLAG - specifies the SPI/I2S flag to check.
* SPI_I2S_FLAG_TXE - Transmit buffer empty flag.
* SPI_I2S_FLAG_RXNE - Receive buffer not empty flag.
* SPI_I2S_FLAG_BSY - Busy flag.
* SPI_I2S_FLAG_OVR - Overrun flag.
* SPI_FLAG_MODF - Mode Fault flag.
* SPI_FLAG_CRCERR - CRC Error flag.
* I2S_FLAG_UDR - Underrun Error flag.
* I2S_FLAG_CHSIDE - Channel Side flag.
*
* @return none
*/
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
{
FlagStatus bitstatus = RESET;
if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn SPI_I2S_ClearFlag
*
* @brief Clears the SPIx CRC Error (CRCERR) flag.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_FLAG - specifies the SPI flag to clear.
* SPI_FLAG_CRCERR - CRC Error flag.
*
* @return none
*/
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
{
SPIx->STATR = (uint16_t)~SPI_I2S_FLAG;
}
/*********************************************************************
* @fn SPI_I2S_GetITStatus
*
* @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_IT - specifies the SPI/I2S interrupt source to check..
* SPI_I2S_IT_TXE - Transmit buffer empty interrupt.
* SPI_I2S_IT_RXNE - Receive buffer not empty interrupt.
* SPI_I2S_IT_OVR - Overrun interrupt.
* SPI_IT_MODF - Mode Fault interrupt.
* SPI_IT_CRCERR - CRC Error interrupt.
* I2S_IT_UDR - Underrun Error interrupt.
*
* @return FlagStatus: SET or RESET.
*/
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
{
ITStatus bitstatus = RESET;
uint16_t itpos = 0, itmask = 0, enablestatus = 0;
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
itmask = SPI_I2S_IT >> 4;
itmask = 0x01 << itmask;
enablestatus = (SPIx->CTLR2 & itmask);
if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn SPI_I2S_ClearITPendingBit
*
* @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* SPI_I2S_IT - specifies the SPI interrupt pending bit to clear.
* SPI_IT_CRCERR - CRC Error interrupt.
*
* @return none
*/
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
{
uint16_t itpos = 0;
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
SPIx->STATR = (uint16_t)~itpos;
}

229
libraries/sdk/Peripheral/ch32v30x_spi.h Normal file
View File

@@ -0,0 +1,229 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_spi.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* SPI firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_SPI_H
#define __CH32V30x_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* SPI Init structure definition */
typedef struct
{
uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_data_direction */
uint16_t SPI_Mode; /* Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_mode */
uint16_t SPI_DataSize; /* Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */
uint16_t SPI_CPOL; /* Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */
}SPI_InitTypeDef;
/* I2S Init structure definition */
typedef struct
{
uint16_t I2S_Mode; /* Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
}I2S_InitTypeDef;
/* SPI_data_direction */
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
/* SPI_mode */
#define SPI_Mode_Master ((uint16_t)0x0104)
#define SPI_Mode_Slave ((uint16_t)0x0000)
/* SPI_data_size */
#define SPI_DataSize_16b ((uint16_t)0x0800)
#define SPI_DataSize_8b ((uint16_t)0x0000)
/* SPI_Clock_Polarity */
#define SPI_CPOL_Low ((uint16_t)0x0000)
#define SPI_CPOL_High ((uint16_t)0x0002)
/* SPI_Clock_Phase */
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
/* SPI_Slave_Select_management */
#define SPI_NSS_Soft ((uint16_t)0x0200)
#define SPI_NSS_Hard ((uint16_t)0x0000)
/* SPI_BaudRate_Prescaler */
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
/* SPI_MSB_LSB_transmission */
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
/* I2S_Mode */
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
/* I2S_Standard */
#define I2S_Standard_Phillips ((uint16_t)0x0000)
#define I2S_Standard_MSB ((uint16_t)0x0010)
#define I2S_Standard_LSB ((uint16_t)0x0020)
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
/* I2S_Data_Format */
#define I2S_DataFormat_16b ((uint16_t)0x0000)
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define I2S_DataFormat_24b ((uint16_t)0x0003)
#define I2S_DataFormat_32b ((uint16_t)0x0005)
/* I2S_MCLK_Output */
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
/* I2S_Audio_Frequency */
#define I2S_AudioFreq_192k ((uint32_t)192000)
#define I2S_AudioFreq_96k ((uint32_t)96000)
#define I2S_AudioFreq_48k ((uint32_t)48000)
#define I2S_AudioFreq_44k ((uint32_t)44100)
#define I2S_AudioFreq_32k ((uint32_t)32000)
#define I2S_AudioFreq_22k ((uint32_t)22050)
#define I2S_AudioFreq_16k ((uint32_t)16000)
#define I2S_AudioFreq_11k ((uint32_t)11025)
#define I2S_AudioFreq_8k ((uint32_t)8000)
#define I2S_AudioFreq_Default ((uint32_t)2)
/* I2S_Clock_Polarity */
#define I2S_CPOL_Low ((uint16_t)0x0000)
#define I2S_CPOL_High ((uint16_t)0x0008)
/* SPI_I2S_DMA_transfer_requests */
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
/* SPI_NSS_internal_software_management */
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
/* SPI_CRC_Transmit_Receive */
#define SPI_CRC_Tx ((uint8_t)0x00)
#define SPI_CRC_Rx ((uint8_t)0x01)
/* SPI_direction_transmit_receive */
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
#define SPI_Direction_Tx ((uint16_t)0x4000)
/* SPI_I2S_interrupts_definition */
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
#define SPI_IT_MODF ((uint8_t)0x55)
#define SPI_IT_CRCERR ((uint8_t)0x54)
#define I2S_IT_UDR ((uint8_t)0x53)
/* SPI_I2S_flags_definition */
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define I2S_FLAG_UDR ((uint16_t)0x0008)
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define SPI_FLAG_MODF ((uint16_t)0x0020)
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
#ifdef __cplusplus
}
#endif
#endif

2366
libraries/sdk/Peripheral/ch32v30x_tim.c Normal file
View File

File diff suppressed because it is too large Load Diff

515
libraries/sdk/Peripheral/ch32v30x_tim.h Normal file
View File

@@ -0,0 +1,515 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_tim.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* TIM firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_TIM_H
#define __CH32V30x_TIM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* TIM Time Base Init structure definition */
typedef struct
{
uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between 0x0000 and 0xFFFF */
uint16_t TIM_CounterMode; /* Specifies the counter mode.
This parameter can be a value of @ref TIM_Counter_Mode */
uint16_t TIM_Period; /* Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter must be a number between 0x0000 and 0xFFFF. */
uint16_t TIM_ClockDivision; /* Specifies the clock division.
This parameter can be a value of @ref TIM_Clock_Division_CKD */
uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
This parameter must be a number between 0x00 and 0xFF.
@note This parameter is valid only for TIM1 and TIM8. */
} TIM_TimeBaseInitTypeDef;
/* TIM Output Compare Init structure definition */
typedef struct
{
uint16_t TIM_OCMode; /* Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_state */
uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_N_state
@note This parameter is valid only for TIM1 and TIM8. */
uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between 0x0000 and 0xFFFF */
uint16_t TIM_OCPolarity; /* Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
@note This parameter is valid only for TIM1 and TIM8. */
uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */
uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */
} TIM_OCInitTypeDef;
/* TIM Input Capture Init structure definition */
typedef struct
{
uint16_t TIM_Channel; /* Specifies the TIM channel.
This parameter can be a value of @ref TIM_Channel */
uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint16_t TIM_ICSelection; /* Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint16_t TIM_ICFilter; /* Specifies the input capture filter.
This parameter can be a number between 0x0 and 0xF */
} TIM_ICInitTypeDef;
/* BDTR structure definition */
typedef struct
{
uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode.
This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state.
This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters.
This parameter can be a value of @ref Lock_level */
uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the
switching-on of the outputs.
This parameter can be a number between 0x00 and 0xFF */
uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not.
This parameter can be a value of @ref Break_Input_enable_disable */
uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity.
This parameter can be a value of @ref Break_Polarity */
uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not.
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
} TIM_BDTRInitTypeDef;
/* TIM_Output_Compare_and_PWM_modes */
#define TIM_OCMode_Timing ((uint16_t)0x0000)
#define TIM_OCMode_Active ((uint16_t)0x0010)
#define TIM_OCMode_Inactive ((uint16_t)0x0020)
#define TIM_OCMode_Toggle ((uint16_t)0x0030)
#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
/* TIM_One_Pulse_Mode */
#define TIM_OPMode_Single ((uint16_t)0x0008)
#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
/* TIM_Channel */
#define TIM_Channel_1 ((uint16_t)0x0000)
#define TIM_Channel_2 ((uint16_t)0x0004)
#define TIM_Channel_3 ((uint16_t)0x0008)
#define TIM_Channel_4 ((uint16_t)0x000C)
/* TIM_Clock_Division_CKD */
#define TIM_CKD_DIV1 ((uint16_t)0x0000)
#define TIM_CKD_DIV2 ((uint16_t)0x0100)
#define TIM_CKD_DIV4 ((uint16_t)0x0200)
/* TIM_Counter_Mode */
#define TIM_CounterMode_Up ((uint16_t)0x0000)
#define TIM_CounterMode_Down ((uint16_t)0x0010)
#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
/* TIM_Output_Compare_Polarity */
#define TIM_OCPolarity_High ((uint16_t)0x0000)
#define TIM_OCPolarity_Low ((uint16_t)0x0002)
/* TIM_Output_Compare_N_Polarity */
#define TIM_OCNPolarity_High ((uint16_t)0x0000)
#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
/* TIM_Output_Compare_state */
#define TIM_OutputState_Disable ((uint16_t)0x0000)
#define TIM_OutputState_Enable ((uint16_t)0x0001)
/* TIM_Output_Compare_N_state */
#define TIM_OutputNState_Disable ((uint16_t)0x0000)
#define TIM_OutputNState_Enable ((uint16_t)0x0004)
/* TIM_Capture_Compare_state */
#define TIM_CCx_Enable ((uint16_t)0x0001)
#define TIM_CCx_Disable ((uint16_t)0x0000)
/* TIM_Capture_Compare_N_state */
#define TIM_CCxN_Enable ((uint16_t)0x0004)
#define TIM_CCxN_Disable ((uint16_t)0x0000)
/* Break_Input_enable_disable */
#define TIM_Break_Enable ((uint16_t)0x1000)
#define TIM_Break_Disable ((uint16_t)0x0000)
/* Break_Polarity */
#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
#define TIM_BreakPolarity_High ((uint16_t)0x2000)
/* TIM_AOE_Bit_Set_Reset */
#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
/* Lock_level */
#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
/* OSSI_Off_State_Selection_for_Idle_mode_state */
#define TIM_OSSIState_Enable ((uint16_t)0x0400)
#define TIM_OSSIState_Disable ((uint16_t)0x0000)
/* OSSR_Off_State_Selection_for_Run_mode_state */
#define TIM_OSSRState_Enable ((uint16_t)0x0800)
#define TIM_OSSRState_Disable ((uint16_t)0x0000)
/* TIM_Output_Compare_Idle_State */
#define TIM_OCIdleState_Set ((uint16_t)0x0100)
#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
/* TIM_Output_Compare_N_Idle_State */
#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
/* TIM_Input_Capture_Polarity */
#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
/* TIM_Input_Capture_Selection */
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be
connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be
connected to IC2, IC1, IC4 or IC3, respectively. */
#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
/* TIM_Input_Capture_Prescaler */
#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */
#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */
#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */
#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */
/* TIM_interrupt_sources */
#define TIM_IT_Update ((uint16_t)0x0001)
#define TIM_IT_CC1 ((uint16_t)0x0002)
#define TIM_IT_CC2 ((uint16_t)0x0004)
#define TIM_IT_CC3 ((uint16_t)0x0008)
#define TIM_IT_CC4 ((uint16_t)0x0010)
#define TIM_IT_COM ((uint16_t)0x0020)
#define TIM_IT_Trigger ((uint16_t)0x0040)
#define TIM_IT_Break ((uint16_t)0x0080)
/* TIM_DMA_Base_address */
#define TIM_DMABase_CR1 ((uint16_t)0x0000)
#define TIM_DMABase_CR2 ((uint16_t)0x0001)
#define TIM_DMABase_SMCR ((uint16_t)0x0002)
#define TIM_DMABase_DIER ((uint16_t)0x0003)
#define TIM_DMABase_SR ((uint16_t)0x0004)
#define TIM_DMABase_EGR ((uint16_t)0x0005)
#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
#define TIM_DMABase_CCER ((uint16_t)0x0008)
#define TIM_DMABase_CNT ((uint16_t)0x0009)
#define TIM_DMABase_PSC ((uint16_t)0x000A)
#define TIM_DMABase_ARR ((uint16_t)0x000B)
#define TIM_DMABase_RCR ((uint16_t)0x000C)
#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
#define TIM_DMABase_BDTR ((uint16_t)0x0011)
#define TIM_DMABase_DCR ((uint16_t)0x0012)
/* TIM_DMA_Burst_Length */
#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
/* TIM_DMA_sources */
#define TIM_DMA_Update ((uint16_t)0x0100)
#define TIM_DMA_CC1 ((uint16_t)0x0200)
#define TIM_DMA_CC2 ((uint16_t)0x0400)
#define TIM_DMA_CC3 ((uint16_t)0x0800)
#define TIM_DMA_CC4 ((uint16_t)0x1000)
#define TIM_DMA_COM ((uint16_t)0x2000)
#define TIM_DMA_Trigger ((uint16_t)0x4000)
/* TIM_External_Trigger_Prescaler */
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
/* TIM_Internal_Trigger_Selection */
#define TIM_TS_ITR0 ((uint16_t)0x0000)
#define TIM_TS_ITR1 ((uint16_t)0x0010)
#define TIM_TS_ITR2 ((uint16_t)0x0020)
#define TIM_TS_ITR3 ((uint16_t)0x0030)
#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
#define TIM_TS_ETRF ((uint16_t)0x0070)
/* TIM_TIx_External_Clock_Source */
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
/* TIM_External_Trigger_Polarity */
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
/* TIM_Prescaler_Reload_Mode */
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
/* TIM_Forced_Action */
#define TIM_ForcedAction_Active ((uint16_t)0x0050)
#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
/* TIM_Encoder_Mode */
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
/* TIM_Event_Source */
#define TIM_EventSource_Update ((uint16_t)0x0001)
#define TIM_EventSource_CC1 ((uint16_t)0x0002)
#define TIM_EventSource_CC2 ((uint16_t)0x0004)
#define TIM_EventSource_CC3 ((uint16_t)0x0008)
#define TIM_EventSource_CC4 ((uint16_t)0x0010)
#define TIM_EventSource_COM ((uint16_t)0x0020)
#define TIM_EventSource_Trigger ((uint16_t)0x0040)
#define TIM_EventSource_Break ((uint16_t)0x0080)
/* TIM_Update_Source */
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow
or the setting of UG bit, or an update generation
through the slave mode controller. */
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
/* TIM_Output_Compare_Preload_State */
#define TIM_OCPreload_Enable ((uint16_t)0x0008)
#define TIM_OCPreload_Disable ((uint16_t)0x0000)
/* TIM_Output_Compare_Fast_State */
#define TIM_OCFast_Enable ((uint16_t)0x0004)
#define TIM_OCFast_Disable ((uint16_t)0x0000)
/* TIM_Output_Compare_Clear_State */
#define TIM_OCClear_Enable ((uint16_t)0x0080)
#define TIM_OCClear_Disable ((uint16_t)0x0000)
/* TIM_Trigger_Output_Source */
#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
#define TIM_TRGOSource_Update ((uint16_t)0x0020)
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
/* TIM_Slave_Mode */
#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
/* TIM_Master_Slave_Mode */
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
/* TIM_Flags */
#define TIM_FLAG_Update ((uint16_t)0x0001)
#define TIM_FLAG_CC1 ((uint16_t)0x0002)
#define TIM_FLAG_CC2 ((uint16_t)0x0004)
#define TIM_FLAG_CC3 ((uint16_t)0x0008)
#define TIM_FLAG_CC4 ((uint16_t)0x0010)
#define TIM_FLAG_COM ((uint16_t)0x0020)
#define TIM_FLAG_Trigger ((uint16_t)0x0040)
#define TIM_FLAG_Break ((uint16_t)0x0080)
#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
/* TIM_Legacy */
#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
void TIM_DeInit(TIM_TypeDef* TIMx);
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
uint16_t TIM_ICPolarity, uint16_t ICFilter);
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter);
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter);
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
#ifdef __cplusplus
}
#endif
#endif

826
libraries/sdk/Peripheral/ch32v30x_usart.c Normal file
View File

@@ -0,0 +1,826 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_usart.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the USART firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v30x_usart.h"
#include "ch32v30x_rcc.h"
/* USART_Private_Defines */
#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */
#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */
#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */
#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */
#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */
#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */
#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */
#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */
#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */
#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */
#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */
#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */
#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */
#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */
#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */
#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */
#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */
#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */
#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */
#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */
#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */
#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */
#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */
#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */
#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */
#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */
/* USART OverSampling-8 Mask */
#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */
#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */
/* USART One Bit Sampling Mask */
#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */
#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */
/*********************************************************************
* @fn USART_DeInit
*
* @brief Deinitializes the USARTx peripheral registers to their default
* reset values.
*
* @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
*
* @return none
*/
void USART_DeInit(USART_TypeDef *USARTx)
{
if(USARTx == USART1)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
}
else if(USARTx == USART2)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
}
else if(USARTx == USART3)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
}
else if(USARTx == UART4)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
}
else if(USARTx == UART5)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
}
else if(USARTx == UART6)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, DISABLE);
}
else if(USARTx == UART7)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE);
}
else if(USARTx == UART8)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE);
}
}
/*********************************************************************
* @fn USART_Init
*
* @brief Initializes the USARTx peripheral according to the specified
* parameters in the USART_InitStruct.
*
* @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
* USART_InitStruct - pointer to a USART_InitTypeDef structure
* that contains the configuration information for the specified
* USART peripheral.
*
* @return none
*/
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
{
uint32_t tmpreg = 0x00, apbclock = 0x00;
uint32_t integerdivider = 0x00;
uint32_t fractionaldivider = 0x00;
uint32_t usartxbase = 0;
RCC_ClocksTypeDef RCC_ClocksStatus;
if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
{
}
usartxbase = (uint32_t)USARTx;
tmpreg = USARTx->CTLR2;
tmpreg &= CTLR2_STOP_CLEAR_Mask;
tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
USARTx->CTLR2 = (uint16_t)tmpreg;
tmpreg = USARTx->CTLR1;
tmpreg &= CTLR1_CLEAR_Mask;
tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
USART_InitStruct->USART_Mode;
USARTx->CTLR1 = (uint16_t)tmpreg;
tmpreg = USARTx->CTLR3;
tmpreg &= CTLR3_CLEAR_Mask;
tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
USARTx->CTLR3 = (uint16_t)tmpreg;
RCC_GetClocksFreq(&RCC_ClocksStatus);
if(usartxbase == USART1_BASE)
{
apbclock = RCC_ClocksStatus.PCLK2_Frequency;
}
else
{
apbclock = RCC_ClocksStatus.PCLK1_Frequency;
}
if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0)
{
integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
}
else
{
integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
}
tmpreg = (integerdivider / 100) << 4;
fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0)
{
tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
}
else
{
tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
}
USARTx->BRR = (uint16_t)tmpreg;
}
/*********************************************************************
* @fn USART_StructInit
*
* @brief Fills each USART_InitStruct member with its default value.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
*
* @return none
*/
void USART_StructInit(USART_InitTypeDef *USART_InitStruct)
{
USART_InitStruct->USART_BaudRate = 9600;
USART_InitStruct->USART_WordLength = USART_WordLength_8b;
USART_InitStruct->USART_StopBits = USART_StopBits_1;
USART_InitStruct->USART_Parity = USART_Parity_No;
USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
}
/*********************************************************************
* @fn USART_ClockInit
*
* @brief Initializes the USARTx peripheral Clock according to the
* specified parameters in the USART_ClockInitStruct .
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
* structure that contains the configuration information for the specified
* USART peripheral.
*
* @return none
*/
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
{
uint32_t tmpreg = 0x00;
tmpreg = USARTx->CTLR2;
tmpreg &= CTLR2_CLOCK_CLEAR_Mask;
tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
USARTx->CTLR2 = (uint16_t)tmpreg;
}
/*********************************************************************
* @fn USART_ClockStructInit
*
* @brief Fills each USART_ClockStructInit member with its default value.
*
* @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
* structure which will be initialized.
*
* @return none
*/
void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct)
{
USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
}
/*********************************************************************
* @fn USART_Cmd
*
* @brief Enables or disables the specified USART peripheral.
* reset values (Affects also the I2Ss).
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState: ENABLE or DISABLE.
*
* @return none
*/
void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR1 |= CTLR1_UE_Set;
}
else
{
USARTx->CTLR1 &= CTLR1_UE_Reset;
}
}
/*********************************************************************
* @fn USART_ITConfig
*
* @brief Enables or disables the specified USART interrupts.
* reset values (Affects also the I2Ss).
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_IT - specifies the USART interrupt sources to be enabled or disabled.
* USART_IT_CTS - CTS change interrupt.
* USART_IT_LBD - LIN Break detection interrupt.
* USART_IT_TXE - Transmit Data Register empty interrupt.
* USART_IT_TC - Transmission complete interrupt.
* USART_IT_RXNE - Receive Data register not empty interrupt.
* USART_IT_IDLE - Idle line detection interrupt.
* USART_IT_PE - Parity Error interrupt.
* USART_IT_ERR - Error interrupt.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
{
uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
uint32_t usartxbase = 0x00;
if(USART_IT == USART_IT_CTS)
{
}
usartxbase = (uint32_t)USARTx;
usartreg = (((uint8_t)USART_IT) >> 0x05);
itpos = USART_IT & IT_Mask;
itmask = (((uint32_t)0x01) << itpos);
if(usartreg == 0x01)
{
usartxbase += 0x0C;
}
else if(usartreg == 0x02)
{
usartxbase += 0x10;
}
else
{
usartxbase += 0x14;
}
if(NewState != DISABLE)
{
*(__IO uint32_t *)usartxbase |= itmask;
}
else
{
*(__IO uint32_t *)usartxbase &= ~itmask;
}
}
/*********************************************************************
* @fn USART_DMACmd
*
* @brief Enables or disables the USART DMA interface.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_DMAReq - specifies the DMA request.
* USART_DMAReq_Tx - USART DMA transmit request.
* USART_DMAReq_Rx - USART DMA receive request.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR3 |= USART_DMAReq;
}
else
{
USARTx->CTLR3 &= (uint16_t)~USART_DMAReq;
}
}
/*********************************************************************
* @fn USART_SetAddress
*
* @brief Sets the address of the USART node.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_Address - Indicates the address of the USART node.
*
* @return none
*/
void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address)
{
USARTx->CTLR2 &= CTLR2_Address_Mask;
USARTx->CTLR2 |= USART_Address;
}
/*********************************************************************
* @fn USART_WakeUpConfig
*
* @brief Selects the USART WakeUp method.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_WakeUp - specifies the USART wakeup method.
* USART_WakeUp_IdleLine - WakeUp by an idle line detection.
* USART_WakeUp_AddressMark - WakeUp by an address mark.
*
* @return none
*/
void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp)
{
USARTx->CTLR1 &= CTLR1_WAKE_Mask;
USARTx->CTLR1 |= USART_WakeUp;
}
/*********************************************************************
* @fn USART_ReceiverWakeUpCmd
*
* @brief Determines if the USART is in mute mode or not.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR1 |= CTLR1_RWU_Set;
}
else
{
USARTx->CTLR1 &= CTLR1_RWU_Reset;
}
}
/*********************************************************************
* @fn USART_LINBreakDetectLengthConfig
*
* @brief Sets the USART LIN Break detection length.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_LINBreakDetectLength - specifies the LIN break detection length.
* USART_LINBreakDetectLength_10b - 10-bit break detection.
* USART_LINBreakDetectLength_11b - 11-bit break detection.
*
* @return none
*/
void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
{
USARTx->CTLR2 &= CTLR2_LBDL_Mask;
USARTx->CTLR2 |= USART_LINBreakDetectLength;
}
/*********************************************************************
* @fn USART_LINCmd
*
* @brief Enables or disables the USART LIN mode.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR2 |= CTLR2_LINEN_Set;
}
else
{
USARTx->CTLR2 &= CTLR2_LINEN_Reset;
}
}
/*********************************************************************
* @fn USART_SendData
*
* @brief Transmits single data through the USARTx peripheral.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* Data - the data to transmit.
*
* @return none
*/
void USART_SendData(USART_TypeDef *USARTx, uint16_t Data)
{
USARTx->DATAR = (Data & (uint16_t)0x01FF);
}
/*********************************************************************
* @fn USART_ReceiveData
*
* @brief Returns the most recent received data by the USARTx peripheral.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
*
* @return The received data.
*/
uint16_t USART_ReceiveData(USART_TypeDef *USARTx)
{
return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF);
}
/*********************************************************************
* @fn USART_SendBreak
*
* @brief Transmits break characters.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
*
* @return none
*/
void USART_SendBreak(USART_TypeDef *USARTx)
{
USARTx->CTLR1 |= CTLR1_SBK_Set;
}
/*********************************************************************
* @fn USART_SetGuardTime
*
* @brief Sets the specified USART guard time.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_GuardTime - specifies the guard time.
*
* @return none
*/
void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime)
{
USARTx->GPR &= GPR_LSB_Mask;
USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
}
/*********************************************************************
* @fn USART_SetPrescaler
*
* @brief Sets the system clock prescaler.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_Prescaler - specifies the prescaler clock.
*
* @return none
*/
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler)
{
USARTx->GPR &= GPR_MSB_Mask;
USARTx->GPR |= USART_Prescaler;
}
/*********************************************************************
* @fn USART_SmartCardCmd
*
* @brief Enables or disables the USART Smart Card mode.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_SCEN_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_SCEN_Reset;
}
}
/*********************************************************************
* @fn USART_SmartCardNACKCmd
*
* @brief Enables or disables NACK transmission.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_NACK_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_NACK_Reset;
}
}
/*********************************************************************
* @fn USART_HalfDuplexCmd
*
* @brief Enables or disables the USART Half Duplex communication.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_HDSEL_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_HDSEL_Reset;
}
}
/*********************************************************************
* @fn USART_OverSampling8Cmd
*
* @brief Enables or disables the USART's 8x oversampling mode.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR1 |= CTLR1_OVER8_Set;
}
else
{
USARTx->CTLR1 &= CTLR1_OVER8_Reset;
}
}
/*********************************************************************
* @fn USART_OneBitMethodCmd
*
* @brief Enables or disables the USART's one bit sampling method.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_ONEBITE_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_ONEBITE_Reset;
}
}
/*********************************************************************
* @fn USART_IrDAConfig
*
* @brief Configures the USART's IrDA interface.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_IrDAMode - specifies the IrDA mode.
* USART_IrDAMode_LowPower.
* USART_IrDAMode_Normal.
*
* @return none
*/
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
{
USARTx->CTLR3 &= CTLR3_IRLP_Mask;
USARTx->CTLR3 |= USART_IrDAMode;
}
/*********************************************************************
* @fn USART_IrDACmd
*
* @brief Enables or disables the USART's IrDA interface.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_IREN_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_IREN_Reset;
}
}
/*********************************************************************
* @fn USART_GetFlagStatus
*
* @brief Checks whether the specified USART flag is set or not.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_FLAG - specifies the flag to check.
* USART_FLAG_CTS - CTS Change flag.
* USART_FLAG_LBD - LIN Break detection flag.
* USART_FLAG_TXE - Transmit data register empty flag.
* USART_FLAG_TC - Transmission Complete flag.
* USART_FLAG_RXNE - Receive data register not empty flag.
* USART_FLAG_IDLE - Idle Line detection flag.
* USART_FLAG_ORE - OverRun Error flag.
* USART_FLAG_NE - Noise Error flag.
* USART_FLAG_FE - Framing Error flag.
* USART_FLAG_PE - Parity Error flag.
*
* @return none
*/
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
{
FlagStatus bitstatus = RESET;
if(USART_FLAG == USART_FLAG_CTS)
{
}
if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn USART_ClearFlag
*
* @brief Clears the USARTx's pending flags.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_FLAG - specifies the flag to clear.
* USART_FLAG_CTS - CTS Change flag.
* USART_FLAG_LBD - LIN Break detection flag.
* USART_FLAG_TC - Transmission Complete flag.
* USART_FLAG_RXNE - Receive data register not empty flag.
*
* @return none
*/
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG)
{
if((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
{
}
USARTx->STATR = (uint16_t)~USART_FLAG;
}
/*********************************************************************
* @fn USART_GetITStatus
*
* @brief Checks whether the specified USART interrupt has occurred or not.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_IT - specifies the USART interrupt source to check.
* USART_IT_CTS - CTS change interrupt.
* USART_IT_LBD - LIN Break detection interrupt.
* USART_IT_TXE - Tansmit Data Register empty interrupt.
* USART_IT_TC - Transmission complete interrupt.
* USART_IT_RXNE - Receive Data register not empty interrupt.
* USART_IT_IDLE - Idle line detection interrupt.
* USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set.
* USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set.
* USART_IT_NE - Noise Error interrupt.
* USART_IT_FE - Framing Error interrupt.
* USART_IT_PE - Parity Error interrupt.
*
* @return none
*/
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT)
{
uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
ITStatus bitstatus = RESET;
if(USART_IT == USART_IT_CTS)
{
}
usartreg = (((uint8_t)USART_IT) >> 0x05);
itmask = USART_IT & IT_Mask;
itmask = (uint32_t)0x01 << itmask;
if(usartreg == 0x01)
{
itmask &= USARTx->CTLR1;
}
else if(usartreg == 0x02)
{
itmask &= USARTx->CTLR2;
}
else
{
itmask &= USARTx->CTLR3;
}
bitpos = USART_IT >> 0x08;
bitpos = (uint32_t)0x01 << bitpos;
bitpos &= USARTx->STATR;
if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn USART_ClearITPendingBit
*
* @brief Clears the USARTx's interrupt pending bits.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_IT - specifies the interrupt pending bit to clear.
* USART_IT_CTS - CTS change interrupt.
* USART_IT_LBD - LIN Break detection interrupt.
* USART_IT_TC - Transmission complete interrupt.
* USART_IT_RXNE - Receive Data register not empty interrupt.
*
* @return none
*/
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT)
{
uint16_t bitpos = 0x00, itmask = 0x00;
if(USART_IT == USART_IT_CTS)
{
}
bitpos = USART_IT >> 0x08;
itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
USARTx->STATR = (uint16_t)~itmask;
}

195
libraries/sdk/Peripheral/ch32v30x_usart.h Normal file
View File

@@ -0,0 +1,195 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_usart.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* USART firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_USART_H
#define __CH32V30x_USART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* USART Init Structure definition */
typedef struct
{
uint32_t USART_BaudRate; /* This member configures the USART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
uint16_t USART_Parity; /* Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} USART_InitTypeDef;
/* USART Clock Init Structure definition */
typedef struct
{
uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_Clock */
uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */
uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */
uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitTypeDef;
/* USART_Word_Length */
#define USART_WordLength_8b ((uint16_t)0x0000)
#define USART_WordLength_9b ((uint16_t)0x1000)
/* USART_Stop_Bits */
#define USART_StopBits_1 ((uint16_t)0x0000)
#define USART_StopBits_0_5 ((uint16_t)0x1000)
#define USART_StopBits_2 ((uint16_t)0x2000)
#define USART_StopBits_1_5 ((uint16_t)0x3000)
/* USART_Parity */
#define USART_Parity_No ((uint16_t)0x0000)
#define USART_Parity_Even ((uint16_t)0x0400)
#define USART_Parity_Odd ((uint16_t)0x0600)
/* USART_Mode */
#define USART_Mode_Rx ((uint16_t)0x0004)
#define USART_Mode_Tx ((uint16_t)0x0008)
/* USART_Hardware_Flow_Control */
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
/* USART_Clock */
#define USART_Clock_Disable ((uint16_t)0x0000)
#define USART_Clock_Enable ((uint16_t)0x0800)
/* USART_Clock_Polarity */
#define USART_CPOL_Low ((uint16_t)0x0000)
#define USART_CPOL_High ((uint16_t)0x0400)
/* USART_Clock_Phase */
#define USART_CPHA_1Edge ((uint16_t)0x0000)
#define USART_CPHA_2Edge ((uint16_t)0x0200)
/* USART_Last_Bit */
#define USART_LastBit_Disable ((uint16_t)0x0000)
#define USART_LastBit_Enable ((uint16_t)0x0100)
/* USART_Interrupt_definition */
#define USART_IT_PE ((uint16_t)0x0028)
#define USART_IT_TXE ((uint16_t)0x0727)
#define USART_IT_TC ((uint16_t)0x0626)
#define USART_IT_RXNE ((uint16_t)0x0525)
#define USART_IT_ORE_RX ((uint16_t)0x0325)
#define USART_IT_IDLE ((uint16_t)0x0424)
#define USART_IT_LBD ((uint16_t)0x0846)
#define USART_IT_CTS ((uint16_t)0x096A)
#define USART_IT_ERR ((uint16_t)0x0060)
#define USART_IT_ORE_ER ((uint16_t)0x0360)
#define USART_IT_NE ((uint16_t)0x0260)
#define USART_IT_FE ((uint16_t)0x0160)
#define USART_IT_ORE USART_IT_ORE_ER
/* USART_DMA_Requests */
#define USART_DMAReq_Tx ((uint16_t)0x0080)
#define USART_DMAReq_Rx ((uint16_t)0x0040)
/* USART_WakeUp_methods */
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
/* USART_LIN_Break_Detection_Length */
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
/* USART_IrDA_Low_Power */
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
/* USART_Flags */
#define USART_FLAG_CTS ((uint16_t)0x0200)
#define USART_FLAG_LBD ((uint16_t)0x0100)
#define USART_FLAG_TXE ((uint16_t)0x0080)
#define USART_FLAG_TC ((uint16_t)0x0040)
#define USART_FLAG_RXNE ((uint16_t)0x0020)
#define USART_FLAG_IDLE ((uint16_t)0x0010)
#define USART_FLAG_ORE ((uint16_t)0x0008)
#define USART_FLAG_NE ((uint16_t)0x0004)
#define USART_FLAG_FE ((uint16_t)0x0002)
#define USART_FLAG_PE ((uint16_t)0x0001)
void USART_DeInit(USART_TypeDef* USARTx);
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
void USART_SendBreak(USART_TypeDef* USARTx);
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
#ifdef __cplusplus
}
#endif
#endif

908
libraries/sdk/Peripheral/ch32v30x_usbotg_device.c Normal file
View File

@@ -0,0 +1,908 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : zf_usb_cdc.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the USBOTG firmware functions.
*******************************************************************************/
#include "stdio.h"
#include "ch32v30x_rcc.h"
#include "ch32v30x_usbotg_device.h"
/* Global define */
/* OTH */
#define pMySetupReqPakHD ((PUSB_SETUP_REQ)EP0_DatabufHD)
#define RepDescSize 62
#define DevEP0SIZE 8
#define PID_OUT 0
#define PID_SOF 1
#define PID_IN 2
#define PID_SETUP 3
typedef struct{
UINT8 dataRat[4];
UINT8 stopBit;
UINT8 parityType;
UINT8 dataBit;
}LINECODINGST;
/******************************************************************************/
/* ȫ<>ֱ<EFBFBD><D6B1><EFBFBD> */
/* Endpoint Buffer */
__attribute__ ((aligned(4))) UINT8 EP0_DatabufHD[8]; //ep0(64)
__attribute__ ((aligned(4))) UINT8 EP1_DatabufHD[64+64]; //ep1_out(64)+ep1_in(64)
__attribute__ ((aligned(4))) UINT8 EP2_DatabufHD[64+64]; //ep2_out(64)+ep2_in(64)
PUINT8 pEP0_RAM_Addr; //ep0(64)
PUINT8 pEP1_RAM_Addr; //ep1_out(64)+ep1_in(64)
PUINT8 pEP2_RAM_Addr; //ep2_out(64)+ep2_in(64)
const UINT8 *pDescr;
volatile UINT8 USBHD_Dev_SetupReqCode = 0xFF; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸Setup<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
volatile UINT16 USBHD_Dev_SetupReqLen = 0x00; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸Setup<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
volatile UINT8 USBHD_Dev_SetupReqValueH = 0x00; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸Setup<EFBFBD><EFBFBD>Value<EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD> */
volatile UINT8 USBHD_Dev_Config = 0x00; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ */
volatile UINT8 USBHD_Dev_Address = 0x00; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD>ֵַ */
volatile UINT8 USBHD_Dev_SleepStatus = 0x00; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸˯<EFBFBD><EFBFBD>״̬ */
volatile UINT8 USBHD_Dev_EnumStatus = 0x00; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸ö<EFBFBD><EFBFBD>״̬ */
volatile UINT8 USBHD_Dev_Endp0_Tog = 0x01; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>0ͬ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>־ */
volatile UINT8 USBHD_Dev_Speed = 0x01; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>ٶ<EFBFBD> */
volatile UINT16 USBHD_Endp1_Up_Flag = 0x00; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>״̬: 0:<3A><><EFBFBD><EFBFBD>; 1:<3A><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>; */
volatile UINT8 USBHD_Endp1_Down_Flag = 0x00; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>1<EFBFBD>´<EFBFBD><EFBFBD>ɹ<EFBFBD><EFBFBD><EFBFBD>־ */
volatile UINT8 USBHD_Endp1_Down_Len = 0x00; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>1<EFBFBD>´<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
volatile BOOL USBHD_Endp1_T_Tog = 0; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>togλ<EFBFBD><EFBFBD>ת */
volatile BOOL USBHD_Endp1_R_Tog = 0;
volatile UINT16 USBHD_Endp2_Up_Flag = 0x00; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>״̬: 0:<3A><><EFBFBD><EFBFBD>; 1:<3A><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>; */
volatile UINT16 USBHD_Endp2_Up_LoadPtr = 0x00; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>װ<EFBFBD><EFBFBD>ƫ<EFBFBD><EFBFBD> */
volatile UINT8 USBHD_Endp2_Down_Flag = 0x00; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>2<EFBFBD>´<EFBFBD><EFBFBD>ɹ<EFBFBD><EFBFBD><EFBFBD>־ */
volatile UINT32V Endp2_send_seq=0x00;
volatile UINT8 DevConfig;
volatile UINT8 SetupReqCode;
volatile UINT16 SetupReqLen;
/******************************************************************************/
/* Device Descriptor */
//<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>ȫ<EFBFBD><C8AB><EFBFBD>豸
const UINT8 MyDevDescrHD[] =
{
0x12, //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD>18<31>ֽ<EFBFBD>
0x01, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD>0x01Ϊ<31>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
0x00,0x02, //<2F><><EFBFBD>豸<EFBFBD><E8B1B8>ʹ<EFBFBD><CAB9>USB<53>汾Э<E6B1BE>飬<EFBFBD><E9A3AC>Ϊ<EFBFBD><CEAA>С<EFBFBD>˽ṹ<CBBD><E1B9B9><EFBFBD><EFBFBD><EFBFBD>Ե<EFBFBD><D4B5>ֽ<EFBFBD><D6BD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>USB1.1<EFBFBD>汾Ϊ0x10,0x01<30><31>USB2.0Ϊ0x00,0x02
0x02, //<2F><><EFBFBD><EFBFBD><EFBFBD>룬CDC<44><43>Ϊ0x02<30><32>CDC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD>0x02<30><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ü<EFBFBD><C3BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿڣ<D3BF><DAA3><EFBFBD><EFBFBD>ᱻϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>Ϊһ<CEAA><D2BB>USB<53><42><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD>Ӷ<EFBFBD><D3B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//<2F><>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>Ϊͨ<CEAA><CDA8><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>õ<EFBFBD>Э<EFBFBD>鶼<EFBFBD><E9B6BC><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>Ϊ0.
0x00, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>룬<EFBFBD><EBA3AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bDeviceClassΪ0ʱ<30><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bDeviceSubClassҲ<73><D2B2><EFBFBD><EFBFBD>Ϊ0<CEAA><30>
0x00, //<2F>豸<EFBFBD><E8B1B8>ʹ<EFBFBD>õ<EFBFBD>Э<EFBFBD>飬Э<E9A3AC><D0AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>USBЭ<42><D0AD><EFBFBD>涨<EFBFBD><E6B6A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֶ<EFBFBD>Ϊ0ʱ<30><CAB1><EFBFBD><EFBFBD>ʾ<EFBFBD>豸<EFBFBD><E8B1B8>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Э<EFBFBD>顣
DevEP0SIZE, //<2F>˵<EFBFBD>0<EFBFBD><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ8<D6B5><38>16<31><36>32<33><32>64<36><34><EFBFBD>˴<EFBFBD>Ϊ64<36>ֽ<EFBFBD>
0x86,0x1a, //<2F><><EFBFBD><EFBFBD>ID
0x22,0x57, //<2F><>Ʒ<EFBFBD>豸ID
0x00,0x01, //<2F>豸<EFBFBD>汾<EFBFBD><E6B1BE>
0x01, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̵<EFBFBD><CCB5>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵΪ0ʱ<30><CAB1><EFBFBD><EFBFBD>ʾû<CABE>г<EFBFBD><D0B3><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>
0x02, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʒ<EFBFBD><C6B7><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵΪ0ʱ<30><CAB1><EFBFBD><EFBFBD>ʾû<CABE>в<EFBFBD>Ʒ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>
0x03, //<2F><><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD><D0BA>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵΪ0ʱ<30><CAB1><EFBFBD><EFBFBD>ʾû<CABE><C3BB><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD><D0BA>ַ<EFBFBD><D6B7><EFBFBD>
0x01, //<2F><><EFBFBD>ܵ<EFBFBD><DCB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>Ϊ1
};
/* Configration Descriptor */
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
const UINT8 MyCfgDescrHD[] =
{
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿڣ<D3BF>
0x09, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD><C8A3><EFBFBD>׼USB<53><42><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ9<CEAA>ֽ<EFBFBD>
0x02, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0x02
0x43,0x00, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܳ<EFBFBD><DCB3>ȣ<EFBFBD>67<36>ֽ<EFBFBD>
0x02, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֧<EFBFBD>ֵĽӿ<C4BD><D3BF><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD>ӿ<EFBFBD>
0x01, //<2F><>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>ֵ
0x00, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD><C3B5>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5>0x00<30><30>ʾû<CABE><C3BB><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>
0xa0, //<2F><><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8>һЩ<D2BB><D0A9><EFBFBD>ԣ<EFBFBD><D4A3>繩<EFBFBD>緽ʽ<E7B7BD>ͻ<EFBFBD><CDBB>ѵȣ<D1B5>0xA0<41><30>ʾ<EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD>߹<EFBFBD><DFB9><EFBFBD><EFBFBD><EFBFBD>֧<EFBFBD><D6A7>Զ<EFBFBD>̻<EFBFBD><CCBB><EFBFBD>
0x32, //<2F>豸<EFBFBD><E8B1B8>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD>߻<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0x32<33><32>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>100ma
//<2F><><EFBFBD><EFBFBD>Ϊ<EFBFBD>ӿ<EFBFBD>0<EFBFBD><30>CDC<44>ӿڣ<D3BF><DAA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿ<EFBFBD><D3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܵ<EFBFBD><DCB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>أ<EFBFBD><D8A3><EFBFBD><EFBFBD>븽<EFBFBD><EBB8BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
0x09, //<2F>ӿ<EFBFBD><D3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD><C8A3><EFBFBD>׼<EFBFBD><D7BC>USB<53>ӿ<EFBFBD><D3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ9<CEAA>ֽ<EFBFBD>
0x04, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>ӿ<EFBFBD><D3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0x04
0x00, //<2F>ýӿڵı<DAB5><C4B1>ţ<EFBFBD><C5A3><EFBFBD>0<EFBFBD><30>ʼ<EFBFBD><CABC><EFBFBD>˴<EFBFBD>Ϊ0x00
0x00, //<2F>ýӿڵı<DAB5><C4B1>ñ<EFBFBD><C3B1><EFBFBD>,ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0
0x01, //<2F>ýӿ<C3BD><D3BF><EFBFBD>ʹ<EFBFBD>õĶ˵<C4B6><CBB5><EFBFBD><EFBFBD><EFBFBD>0x01<30><31>ʾʹ<CABE><CAB9>1<EFBFBD><31><EFBFBD>˵㡣<CBB5><E3A1A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֶ<EFBFBD>Ϊ0<CEAA><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾû<CABE>з<EFBFBD>0<EFBFBD>˵㣬ֻʹ<D6BB><CAB9>Ĭ<EFBFBD>ϵĿ<CFB5><C4BF>ƶ˵㡣CDC<44>ӿ<EFBFBD>ֻʹ<D6BB><CAB9>һ<EFBFBD><D2BB><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD>
0x02, //<2F>ýӿ<C3BD><D3BF><EFBFBD>ʹ<EFBFBD>õ<EFBFBD><C3B5>࣬0x02ΪCDC<44><43>
0x02, //<2F>ýӿ<C3BD><D3BF><EFBFBD>ʹ<EFBFBD>õ<EFBFBD><C3B5><EFBFBD><EFBFBD>࣬Ҫʵ<D2AA><CAB5>USBת<42><D7AA><EFBFBD>ڣ<EFBFBD><DAA3>ͱ<EFBFBD><CDB1><EFBFBD>ʹ<EFBFBD><CAB9>Abstract Control Model<65><6C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>࣬<EFBFBD><E0A3AC><EFBFBD>ı<EFBFBD><C4B1><EFBFBD>Ϊ0x02
0x01, //<2F>ýӿ<C3BD><D3BF><EFBFBD>ʹ<EFBFBD>õ<EFBFBD>Э<EFBFBD>飬ʹ<E9A3AC><CAB9>Common AT Commands<64><73>ͨ<EFBFBD><CDA8>AT<41><54><EFBFBD>Э<EEA3A9><D0AD>
0x00, //<2F>ýӿڵ<D3BF><DAB5>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5>0x00<30><30>ʾû<CABE><C3BB><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>
//<2F><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿ<EFBFBD><D3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿڵĹ<DAB5><C4B9>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CDC<44>ӿڣ<D3BF><DAA3><EFBFBD><EFBFBD>ӿڣ<D3BF>֮<EFBFBD><D6AE>
//Header Functional Descriptor
0x05, //<2F>ù<EFBFBD><C3B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ij<EFBFBD><C4B3>ȣ<EFBFBD>5<EFBFBD><35><EFBFBD>ֽ<EFBFBD>
0x24, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>̶<EFBFBD>λ0x24<32><34>CS_INTERFACE<43>ı<EFBFBD><C4B1>룩
0x00, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
0x10,0x01, //USBͨ<42><CDA8><EFBFBD>豸Э<E8B1B8><D0AD><EFBFBD>İ汾<C4B0>š<EFBFBD><C5A1>˴<EFBFBD>ΪUSB1.1
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(û<><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿ<EFBFBD>)
//Call Management Functional Descriptor
0x05, //<2F>ù<EFBFBD><C3B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ij<EFBFBD><C4B3>ȣ<EFBFBD>5<EFBFBD><35><EFBFBD>ֽ<EFBFBD>
0x24, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>̶<EFBFBD>λ0x24<32><34>CS_INTERFACE<43>ı<EFBFBD><C4B1>룩
0x01, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
0x00, //<2F><><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λD0<44><30>D1<44><31><EFBFBD><EFBFBD><EFBFBD>壬<EFBFBD><E5A3AC><EFBFBD><EFBFBD>λΪ<CEBB><CEAA><EFBFBD><EFBFBD>ֵ0<D6B5><30>D0Ϊ0<CEAA><30><EFBFBD><EFBFBD>ʾ<EFBFBD>豸<EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ù<EFBFBD><C3B9><EFBFBD><EFBFBD><EFBFBD>Ϊ1<CEAA><31><EFBFBD><EFBFBD>ʾ<EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
0x00, //<2F><>ʾѡ<CABE><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ù<EFBFBD><C3B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿڱ<D3BF><DAB1>ţ<EFBFBD><C5A3><EFBFBD><EFBFBD>ڲ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿ<EFBFBD><D3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ù<EFBFBD><C3B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֶ<EFBFBD><D6B6><EFBFBD><EFBFBD><EFBFBD>Ϊ0
//Abstract Control Management Functional Descriptor <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƹ<EFBFBD><C6B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
0x04, //<2F>ù<EFBFBD><C3B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ij<EFBFBD><C4B3>ȣ<EFBFBD>4<EFBFBD><34><EFBFBD>ֽ<EFBFBD>
0x24, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>̶<EFBFBD>λ0x24<32><34>CS_INTERFACE<43>ı<EFBFBD><C4B1>룩
0x02, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
0x02, //<2F><><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>D7-4λΪ<CEBB><CEAA><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0<CEAA><30>֧<EFBFBD><D6A7>Set_Line_Coding<6E><67>Set_Control_Line_State<74><65>Get_Line_Coding<6E><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Serial_State֪ͨ
//D0<44><30>ʾ<EFBFBD>Ƿ<EFBFBD>֧<EFBFBD><D6A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Set_Comm_Feature<72><65>Clear_Comm_Feature<72><65>Get_Comm_Feature,Ϊ1<CEAA><31>ʾ֧<CABE>֣<EFBFBD>
//D1λ<31><CEBB>ʾ<EFBFBD>Ƿ<EFBFBD>֧<EFBFBD><D6A7>Set_Line_Coding<6E><67>Set_Control_Line_State<74><65>Get_Line_Coding<6E><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Serial_State֪ͨ<CDA8><D6AA>Ϊ1<CEAA><31>ʾ֧<CABE><D6A7>
//D2Ϊ<32><CEAA>ʾ<EFBFBD>Ƿ<EFBFBD>֧<EFBFBD><D6A7>Send_Break<61><6B>Ϊ1<CEAA><31>ʾ֧<CABE><D6A7>
//D3<44><33>ʾ<EFBFBD>Ƿ<EFBFBD>֧<EFBFBD><D6A7>Network_Connection֪ͨ<CDA8><D6AA>Ϊ1<CEAA><31>ʾ֧<CABE><D6A7>
//Union Functional Descriptor<6F><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD>5<EFBFBD>ֽڣ<D6BD><DAA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD>ӿ<EFBFBD>֮<EFBFBD><D6AE><EFBFBD>Ĺ<EFBFBD>ϵ<EFBFBD><CFB5><EFBFBD>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD><EFBFBD>Ϊһ<CEAA><D2BB><EFBFBD><EFBFBD><EFBFBD>ܵ<EFBFBD>Ԫ<EFBFBD><D4AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Щ<EFBFBD>ӿ<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD>ӿڣ<D3BF><DAA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>ӽӿ<D3BD>
0x05, //<2F>ù<EFBFBD><C3B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ij<EFBFBD><C4B3>ȣ<EFBFBD>5<EFBFBD><35><EFBFBD>ֽ<EFBFBD>
0x24, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>̶<EFBFBD>λ0x24<32><34>CS_INTERFACE<43>ı<EFBFBD><C4B1>룩
0x06, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
0x00, //<2F><><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD>ӿڱ<D3BF><DAB1>ţ<EFBFBD><C5A3>˴<EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>Ϊ0<CEAA><30>CDC<44>ӿ<EFBFBD>
0x01, //<2F><><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>Ϊ<EFBFBD><CEAA>һ<EFBFBD>ӽӿڱ<D3BF><DAB1>ţ<EFBFBD><C5A3>˴<EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿڣ<D3BF><DAA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>һ<EFBFBD><D2BB><EFBFBD>ӽӿ<D3BD>
//<2F>ӿ<EFBFBD>0<EFBFBD><30>CDC<44>ӿڣ<D3BF><DAA3>Ķ˵<C4B6><CBB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>˵<EFBFBD>1 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
0x07, //<2F>˵<EFBFBD><CBB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD>7<EFBFBD>ֽ<EFBFBD>
0x05, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>˵<EFBFBD><CBB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0x05
0x81, //<2F>ö˵<C3B6><CBB5>ĵ<EFBFBD>ַ<EFBFBD><D6B7>0x81<38><31>ʾ<EFBFBD>˵<EFBFBD>1<EFBFBD><31>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
0x03, //<2F>ö˵<C3B6><CBB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ԡ<EFBFBD><D4A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λD1-0<><30>ʾ<EFBFBD>ö˵<C3B6><CBB5>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD>0Ϊ<30><CEAA><EFBFBD>ƴ<EFBFBD><C6B4>䣬1Ϊ<31><CEAA>ʱ<EFBFBD><CAB1><EFBFBD>䣬2Ϊ<32><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>䣬3Ϊ<33>жϴ<D0B6><CFB4><EFBFBD>
0x40,0x00, //<2F>ö˵<C3B6>֧<EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD>64<36>ֽ<EFBFBD>
0xFF, //<2F>˵<EFBFBD><CBB5>IJ<EFBFBD>ѯʱ<D1AF><CAB1>
//<2F><><EFBFBD><EFBFBD>Ϊ<EFBFBD>ӿ<EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD>ݽӿڣ<D3BF><DAA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>˵<EFBFBD>2
//CDC<44><43><EFBFBD>ӿڣ<D3BF><DAA3>ӿ<EFBFBD>0<EFBFBD><30><EFBFBD>Ǹ<EFBFBD><C7B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD><DDB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿڽ<D3BF><DABD>еġ<D0B5><C4A1><EFBFBD><EFBFBD><EFBFBD>ֻʹ<D6BB><CAB9>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿڣ<D3BF><DAA3><EFBFBD><EFBFBD><EFBFBD>Ϊ1
0x09, //<2F>ӿ<EFBFBD><D3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD>9<EFBFBD>ֽ<EFBFBD>
0x04, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>ӿ<EFBFBD><D3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0x04
0x01, //<2F>ýӿڵı<DAB5><C4B1>ţ<EFBFBD><C5A3><EFBFBD>0<EFBFBD><30>ʼ<EFBFBD><CABC><EFBFBD>˴<EFBFBD>Ϊ0x01
0x00, //<2F>ýӿڵı<DAB5><C4B1>ñ<EFBFBD><C3B1><EFBFBD>
0x02, //<2F>ýӿ<C3BD><D3BF><EFBFBD>ʹ<EFBFBD>õĶ˵<C4B6><CBB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ýӿ<C3BD>Ҫʹ<D2AA><CAB9>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵㣬<CBB5><E3A3AC><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><CBB5><EFBFBD><EFBFBD><EFBFBD>Ϊ2
0x0a, //<2F>ýӿ<C3BD><D3BF><EFBFBD>ʹ<EFBFBD>õ<EFBFBD><C3B5>࣬0x0aΪCDC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
0x00, //<2F>ýӿ<C3BD><D3BF><EFBFBD>ʹ<EFBFBD>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD>
0x00, //<2F>ýӿ<C3BD><D3BF><EFBFBD>ʹ<EFBFBD>õ<EFBFBD>Э<EFBFBD><D0AD>
0x00, //<2F>ýӿڵ<D3BF><DAB5>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5>0x00<30><30>ʾû<CABE><C3BB><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>
//<2F>ӿ<EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿڣ<D3BF><DAA3>Ķ˵<C4B6><CBB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>˵<EFBFBD>2
0x07, //<2F>˵<EFBFBD><CBB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD>7<EFBFBD>ֽ<EFBFBD>
0x05, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>˵<EFBFBD><CBB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0x05
0x02, //<2F>ö˵<C3B6><CBB5>ĵ<EFBFBD>ַ<EFBFBD><D6B7>0x02<30><32>ʾ<EFBFBD>˵<EFBFBD>2<EFBFBD><32>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
0x02, //<2F>ö˵<C3B6><CBB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ԡ<EFBFBD><D4A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λD1-0<><30>ʾ<EFBFBD>ö˵<C3B6><CBB5>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD>0Ϊ<30><CEAA><EFBFBD>ƴ<EFBFBD><C6B4>䣬1Ϊ<31><CEAA>ʱ<EFBFBD><CAB1><EFBFBD>䣬2Ϊ<32><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>䣬3Ϊ<33>жϴ<D0B6><CFB4><EFBFBD>
0x40,0x00, //<2F>ö˵<C3B6>֧<EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD>64<36>ֽ<EFBFBD>
0x00, //<2F>˵<EFBFBD><CBB5>IJ<EFBFBD>ѯʱ<D1AF>䣬<EFBFBD><E4A3AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><CBB5><EFBFBD>Ч
0x07, //<2F>˵<EFBFBD><CBB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD>7<EFBFBD>ֽ<EFBFBD>
0x05, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>˵<EFBFBD><CBB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0x05
0x82, //<2F>ö˵<C3B6><CBB5>ĵ<EFBFBD>ַ<EFBFBD><D6B7>0x82<38><32>ʾ<EFBFBD>˵<EFBFBD>2<EFBFBD><32>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
0x02, //<2F>ö˵<C3B6><CBB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ԡ<EFBFBD><D4A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λD1-0<><30>ʾ<EFBFBD>ö˵<C3B6><CBB5>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD>0Ϊ<30><CEAA><EFBFBD>ƴ<EFBFBD><C6B4>䣬1Ϊ<31><CEAA>ʱ<EFBFBD><CAB1><EFBFBD>䣬2Ϊ<32><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>䣬3Ϊ<33>жϴ<D0B6><CFB4><EFBFBD>
0x40,0x00, //<2F>ö˵<C3B6>֧<EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD>64<36>ֽ<EFBFBD>
0x00, //<2F>˵<EFBFBD><CBB5>IJ<EFBFBD>ѯʱ<D1AF>䣬<EFBFBD><E4A3AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><CBB5><EFBFBD>Ч //<2F>˵<EFBFBD><CBB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
};
/* USB<53><42><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
const UINT8 MyReportDescHD[ ] =
{0x14,0x03,0x32,0x00,0x30,0x00,0x31,0x00,0x37,0x00,0x2D,0x00,0x32,0x00,0x2D,0x00,0x32,0x00,0x35,0x00};
/* Language Descriptor */
const UINT8 MyLangDescrHD[] =
{
0x04, 0x03, 0x09, 0x04
};
/* Manufactor Descriptor */
const UINT8 MyManuInfoHD[] =
{
0x0E, 0x03, 'w', 0, 'c', 0, 'h', 0, '.', 0, 'c', 0, 'n', 0
};
/* Product Information */
const UINT8 MyProdInfoHD[] =
{
0x0C, 0x03, 'C', 0, 'H', 0, '3', 0, '0', 0, '7', 0
};
/* USB<53><42><EFBFBD>к<EFBFBD><D0BA>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
const UINT8 MySerNumInfoHD[ ] =
{
/* 0123456789 */
22,03,48,0,49,0,50,0,51,0,52,0,53,0,54,0,55,0,56,0,57,0
};
/* USB<53>豸<EFBFBD>޶<EFBFBD><DEB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
const UINT8 MyUSBQUADescHD[ ] =
{
0x0A, 0x06, 0x00, 0x02, 0xFF, 0x00, 0xFF, 0x40, 0x01, 0x00,
};
/* USBȫ<42><C8AB>ģʽ,<2C><><EFBFBD><EFBFBD><EFBFBD>ٶ<EFBFBD><D9B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
UINT8 TAB_USB_FS_OSC_DESC[ sizeof( MyCfgDescrHD ) ] =
{
0x09, 0x07, /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
};
void OTG_FS_IRQHandler(void) __attribute__((interrupt()));
/*******************************************************************************
* Function Name : USBOTG_FS_DeviceInit
* Description : Initializes USB device.
* Input : None
* Return : None
*******************************************************************************/
void USBDeviceInit( void )
{
USBOTG_FS->BASE_CTRL = 0x00;
USBOTG_FS->UEP4_1_MOD = USBHD_UEP4_RX_EN|USBHD_UEP4_TX_EN|USBHD_UEP1_RX_EN|USBHD_UEP1_TX_EN;
USBOTG_FS->UEP2_3_MOD = USBHD_UEP2_RX_EN|USBHD_UEP2_TX_EN|USBHD_UEP3_RX_EN|USBHD_UEP3_TX_EN;
USBOTG_FS->UEP5_6_MOD = USBHD_UEP5_RX_EN|USBHD_UEP5_TX_EN|USBHD_UEP6_RX_EN|USBHD_UEP6_TX_EN;
USBOTG_FS->UEP7_MOD = USBHD_UEP7_RX_EN|USBHD_UEP7_TX_EN;
USBOTG_FS->UEP0_DMA = (UINT32)pEP0_RAM_Addr;
USBOTG_FS->UEP1_DMA = (UINT32)pEP1_RAM_Addr;
USBOTG_FS->UEP2_DMA = (UINT32)pEP2_RAM_Addr;
USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK;
USBOTG_FS->UEP1_RX_CTRL = USBHD_UEP_R_RES_ACK;
USBOTG_FS->UEP2_RX_CTRL = USBHD_UEP_R_RES_ACK;
USBOTG_FS->UEP1_TX_LEN = 8;
USBOTG_FS->UEP2_TX_LEN = 8;
USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK;
USBOTG_FS->UEP1_TX_CTRL = USBHD_UEP_T_RES_NAK;
USBOTG_FS->UEP2_TX_CTRL = USBHD_UEP_T_RES_NAK;
USBOTG_FS->INT_FG = 0xFF;
USBOTG_FS->INT_EN = USBHD_UIE_SUSPEND | USBHD_UIE_BUS_RST | USBHD_UIE_TRANSFER;
USBOTG_FS->DEV_ADDR = 0x00;
USBOTG_FS->BASE_CTRL = USBHD_UC_DEV_PU_EN | USBHD_UC_INT_BUSY | USBHD_UC_DMA_EN;
USBOTG_FS->UDEV_CTRL = USBHD_UD_PD_DIS|USBHD_UD_PORT_EN;
}
/*******************************************************************************
* Function Name : USBOTG_RCC_Init
* Description : USBOTG RCC init
* Input : None
* Return : None
*******************************************************************************/
void USBOTG_RCC_Init( void )
{
RCC_USBCLK48MConfig( RCC_USBCLK48MCLKSource_USBPHY );
RCC_USBHSPLLCLKConfig( RCC_HSBHSPLLCLKSource_HSE );
RCC_USBHSConfig( RCC_USBPLL_Div2 );
RCC_USBHSPLLCKREFCLKConfig( RCC_USBHSPLLCKREFCLK_4M );
RCC_USBHSPHYPLLALIVEcmd( ENABLE );
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBHS, ENABLE );
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_OTG_FS, ENABLE );
}
/**********************************************************/
UINT8 Ready = 0;
UINT8 UsbConfig;
//UINT8 SetupReqCode;
//UINT16 SetupReqLen;
//CDC<44><43><EFBFBD><EFBFBD>
UINT8 LineCoding[7]={0x00,0xC2,0x01,0x00,0x00,0x00,0x08}; //<2F><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ57600<30><30>1ֹͣλ<D6B9><CEBB><EFBFBD><EFBFBD>У<EFBFBD>飬8<E9A3AC><38><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>
#define SET_LINE_CODING 0x20 //Configures DTE rate, stop-bits, parity, and number-of-character
#define GET_LINE_CODING 0x21 //This request allows the host to find out the currently configured line coding.
#define SET_CONTROL_LINE_STATE 0x22 //This request generates RS-232/V.24 style control signals.
#define UART_REV_LEN 0x40 //<2F><><EFBFBD>ڽ<EFBFBD><DABD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С
UINT8 Receive_Uart_Buf[UART_REV_LEN]; //<2F><><EFBFBD>ڽ<EFBFBD><DABD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD>
volatile UINT8 Uart_Input_Point = 0; //ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4>ָ<EFBFBD>룬<EFBFBD><EBA3AC><EFBFBD>߸<EFBFBD>λ<EFBFBD><CEBB>Ҫ<EFBFBD><D2AA>ʼ<EFBFBD><CABC>Ϊ0
volatile UINT8 Uart_Output_Point = 0; //ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ָ<EFBFBD>룬<EFBFBD><EBA3AC><EFBFBD>߸<EFBFBD>λ<EFBFBD><CEBB>Ҫ<EFBFBD><D2AA>ʼ<EFBFBD><CABC>Ϊ0
volatile UINT8 UartByteCount = 0; //<2F><>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʣ<EFBFBD><CAA3><EFBFBD><EFBFBD>ȡ<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>
volatile UINT8 USBByteCount = 0; //<2F><><EFBFBD><EFBFBD>USB<53>˵<EFBFBD><CBB5><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
volatile UINT8 USBBufOutPoint = 0; //ȡ<><C8A1><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
volatile UINT8 UpPoint2_Busy = 0; //<2F>ϴ<EFBFBD><CFB4>˵<EFBFBD><CBB5>Ƿ<EFBFBD>æ<EFBFBD><C3A6>־
const UINT8 *pDescr;
/*******************************************************************************
* Function Name : DevEP1_IN_Deal
* Description : Device endpoint1 IN.
* Input : l: IN length(<64B)
* Return : None
*******************************************************************************/
void DevEP1_IN_Deal( UINT8 l )
{
USBOTG_FS->UEP1_TX_LEN = l;
USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL & ~USBHD_UEP_T_RES_MASK)| USBHD_UEP_T_RES_ACK;
}
/*******************************************************************************
* Function Name : DevEP2_IN_Deal
* Description : Device endpoint2 IN.
* Input : l: IN length(<64B)
* Return : None
*******************************************************************************/
void DevEP2_IN_Deal( UINT8 l )
{
USBOTG_FS->UEP2_TX_LEN = l;
USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL & ~USBHD_UEP_T_RES_MASK)| USBHD_UEP_T_RES_ACK;
}
/*******************************************************************************
* Function Name : DevEP1_OUT_Deal
* Description : Deal device Endpoint 1 OUT.
* Input : l: Data length.
* Return : None
*******************************************************************************/
void DevEP1_OUT_Deal( UINT8 l )
{
UINT8 i;
for(i=0; i<l; i++)
{
pEP1_IN_DataBuf[i] = ~pEP1_OUT_DataBuf[i];
}
DevEP1_IN_Deal( l );
}
/*******************************************************************************
* Function Name : DevEP2_OUT_Deal
* Description : Deal device Endpoint 2 OUT.
* Input : l: Data length.
* Return : None
*******************************************************************************/
void DevEP2_OUT_Deal( UINT8 l )
{
UINT8 i;
for(i=0; i<l; i++)
{
pEP2_IN_DataBuf[i] = ~pEP2_OUT_DataBuf[i];
}
DevEP2_IN_Deal( l );
}
/*******************************************************************************
* Function Name : OTG_FS_IRQHandler
* Description : OTG_FS_IRQHandler OTG<54>豸<EFBFBD>жϴ<D0B6><CFB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* Input : None
* Return : None
*******************************************************************************/
void OTG_FS_IRQHandler( void )
{
UINT8 len, chtype;
UINT8 intflag, errflag = 0;
intflag = USBOTG_FS->INT_FG;
if( intflag & USBHD_UIF_TRANSFER )
{
switch ( USBOTG_FS->INT_ST & USBHD_UIS_TOKEN_MASK )
{
/* SETUP<55><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
case USBHD_UIS_TOKEN_SETUP:
/* <20><>ӡ<EFBFBD><D3A1>ǰUsbsetup<75><70><EFBFBD><EFBFBD> */
// printf( "Setup Req :\n" );
// printf( "%02X ", pSetupReqPakHD->bRequestType );
// printf( "%02X ", pSetupReqPakHD->bRequest );
// printf( "%04X ", pSetupReqPakHD->wValue );
// printf( "%04X ", pSetupReqPakHD->wIndex );
// printf( "%04X ", pSetupReqPakHD->wLength );
// printf( "\n" );
USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_TOG|USBHD_UEP_T_RES_NAK;
USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_TOG|USBHD_UEP_R_RES_ACK;
SetupReqLen = pSetupReqPakHD->wLength;
SetupReqCode = pSetupReqPakHD->bRequest;
chtype = pSetupReqPakHD->bRequestType;
len = 0;
errflag = 0;
/* <20>жϵ<D0B6>ǰ<EFBFBD>DZ<EFBFBD>׼<EFBFBD><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if ( ( pSetupReqPakHD->bRequestType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD ) //<2F>DZ<EFBFBD>׼<EFBFBD><D7BC><EFBFBD><EFBFBD>
{
//CDC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
if(SetupReqCode & 0x20)
{
switch( SetupReqCode )
{
case GET_LINE_CODING: //0x21 currently configured
pDescr = LineCoding;
len = sizeof(LineCoding);
len = SetupReqLen >= DEFAULT_ENDP0_SIZE ? DEFAULT_ENDP0_SIZE : SetupReqLen; // <20><><EFBFBD>δ<EFBFBD><CEB4>䳤<EFBFBD><E4B3A4>
memcpy(pEP0_DataBuf,pDescr,len);
SetupReqLen -= len;
pDescr += len;
break;
case SET_CONTROL_LINE_STATE: //0x22 generates RS-232/V.24 style control signals
break;
case SET_LINE_CODING: //0x20 Configure
break;
default:
errflag = 0xFF;
}
}
// /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
// if( pSetupReqPakHD->bRequestType & 0x40 )
// {
// /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
// switch( pSetupReqPakHD->bRequest )
// {
// default:
// errflag = 0xFF;/* <20><><EFBFBD><EFBFBD>ʧ<EFBFBD><CAA7> */
// break;
// }
// }
// }
/* <20>ж<EFBFBD><D0B6>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if( errflag != 0xFF )
{
if( SetupReqLen > len )
{
SetupReqLen = len;
}
len = ( USBHD_Dev_SetupReqLen >= DevEP0SIZE ) ? DevEP0SIZE : USBHD_Dev_SetupReqLen;
memcpy( EP0_DatabufHD, pDescr, len );
pDescr += len;
}
}
else
{
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>׼USB<53><42><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
switch( SetupReqCode )
{
case USB_GET_DESCRIPTOR:
{
switch( ((pSetupReqPakHD->wValue)>>8) )
{
case USB_DESCR_TYP_DEVICE:
/* <20><>ȡ<EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
pDescr = MyDevDescrHD;
len = MyDevDescrHD[0];
break;
case USB_DESCR_TYP_CONFIG:
/* <20><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
pDescr = MyCfgDescrHD;
len = MyCfgDescrHD[2];
break;
case USB_DESCR_TYP_STRING:
/* <20><>ȡ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
switch( (pSetupReqPakHD->wValue)&0xff )
{
case 0:
/* <20><><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
pDescr = MyLangDescrHD;
len = MyLangDescrHD[0];
break;
case 1:
/* USB<53><42><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
pDescr = MyManuInfoHD;
len = MyManuInfoHD[0];
break;
case 2:
/* USB<53><42>Ʒ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
pDescr = MyProdInfoHD;
len = MyProdInfoHD[0];
break;
case 3:
/* USB<53><42><EFBFBD>к<EFBFBD><D0BA>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
pDescr = MySerNumInfoHD;
len = sizeof( MySerNumInfoHD );
break;
default:
errflag = 0xFF;
break;
}
break;
case USB_DESCR_TYP_REPORT:
/* USB<53>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
pDescr = MyReportDescHD;
len = sizeof( MyReportDescHD );
break;
case USB_DESCR_TYP_QUALIF:
/* <20>豸<EFBFBD>޶<EFBFBD><DEB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
pDescr = ( PUINT8 )&MyUSBQUADescHD[ 0 ];
len = sizeof( MyUSBQUADescHD );
break;
case USB_DESCR_TYP_SPEED:
/* <20><><EFBFBD><EFBFBD><EFBFBD>ٶ<EFBFBD><D9B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
/* <20><><EFBFBD><EFBFBD><EFBFBD>ٶ<EFBFBD><D9B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if( USBHD_Dev_Speed == 0x00 )
{
/* ȫ<><C8AB>ģʽ */
memcpy( &TAB_USB_FS_OSC_DESC[ 2 ], &MyCfgDescrHD[ 2 ], sizeof( MyCfgDescrHD ) - 2 );
pDescr = ( PUINT8 )&TAB_USB_FS_OSC_DESC[ 0 ];
len = sizeof( TAB_USB_FS_OSC_DESC );
}
else
{
errflag = 0xFF;
}
break;
case USB_DESCR_TYP_BOS:
/* BOS<4F><53><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
/* USB2.0<EFBFBD>豸<EFBFBD><EFBFBD>֧<EFBFBD><EFBFBD>BOS<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
errflag = 0xFF;
break;
default :
errflag = 0xff;
break;
}
if( SetupReqLen>len ) SetupReqLen = len;
len = (SetupReqLen >= DevEP0SIZE) ? DevEP0SIZE : SetupReqLen;
memcpy( pEP0_DataBuf, pDescr, len );
pDescr += len;
}
break;
case USB_SET_ADDRESS:
/* <20><><EFBFBD>õ<EFBFBD>ַ */
SetupReqLen = (pSetupReqPakHD->wValue)&0xff;
break;
case USB_GET_CONFIGURATION:
/* <20><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>ֵ */
pEP0_DataBuf[0] = DevConfig;
if ( SetupReqLen > 1 ) SetupReqLen = 1;
break;
case USB_SET_CONFIGURATION:
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ */
DevConfig = (pSetupReqPakHD->wValue)&0xff;
break;
case USB_CLEAR_FEATURE:
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if ( ( pSetupReqPakHD->bRequestType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP )
{
/* <20><><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD> */
switch( (pSetupReqPakHD->wIndex)&0xff )
{
case 0x82:
USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL & ~( USBHD_UEP_T_TOG|USBHD_UEP_T_RES_MASK )) | USBHD_UEP_T_RES_NAK;
break;
case 0x02:
USBOTG_FS->UEP2_RX_CTRL = (USBOTG_FS->UEP2_RX_CTRL & ~( USBHD_UEP_R_TOG|USBHD_UEP_R_RES_MASK )) | USBHD_UEP_R_RES_ACK;
break;
case 0x81:
USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL & ~( USBHD_UEP_T_TOG|USBHD_UEP_T_RES_MASK )) | USBHD_UEP_T_RES_NAK;
break;
case 0x01:
USBOTG_FS->UEP1_RX_CTRL = (USBOTG_FS->UEP1_RX_CTRL & ~( USBHD_UEP_R_TOG|USBHD_UEP_R_RES_MASK )) | USBHD_UEP_R_RES_ACK;
break;
default:
errflag = 0xFF;
break;
}
}
else errflag = 0xFF;
break;
case USB_SET_FEATURE:
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if( ( pMySetupReqPakHD->bRequestType & 0x1F ) == 0x00 )
{
/* <20><><EFBFBD><EFBFBD><EFBFBD>豸 */
if( pMySetupReqPakHD->wValue == 0x01 )
{
if( MyCfgDescrHD[ 7 ] & 0x20 )
{
/* <20><><EFBFBD>û<EFBFBD><C3BB><EFBFBD>ʹ<EFBFBD>ܱ<EFBFBD>־ */
USBHD_Dev_SleepStatus = 0x01;
}
else
{
errflag = 0xFF;
}
}
else
{
errflag = 0xFF;
}
}
else if( ( pMySetupReqPakHD->bRequestType & 0x1F ) == 0x02 )
{
/* <20><><EFBFBD>ö˵<C3B6> */
if( pMySetupReqPakHD->wValue == 0x00 )
{
/* <20><><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>˵<EFBFBD>STALL */
switch( ( pMySetupReqPakHD->wIndex ) & 0xff )
{
case 0x82:
/* <20><><EFBFBD>ö˵<C3B6>2 IN STALL */
USBOTG_FS->UEP2_TX_CTRL = ( USBOTG_FS->UEP2_TX_CTRL &= ~USBHD_UEP_T_RES_MASK ) | USBHD_UEP_T_RES_STALL;
//USBHS->UEP2_CTRL = ( USBHS->UEP2_CTRL & ~USBHS_EP_T_RES_MASK ) | USBHS_EP_T_RES_STALL;
break;
case 0x02:
/* <20><><EFBFBD>ö˵<C3B6>2 OUT Stall */
USBOTG_FS->UEP2_RX_CTRL = ( USBOTG_FS->UEP2_RX_CTRL &= ~USBHD_UEP_R_RES_MASK ) | USBHD_UEP_R_RES_STALL;
//USBHS->UEP2_CTRL = ( USBHS->UEP2_CTRL & ~USBHS_EP_R_RES_MASK ) | USBHS_EP_R_RES_STALL;
break;
case 0x81:
/* <20><><EFBFBD>ö˵<C3B6>1 IN STALL */
USBOTG_FS->UEP1_TX_CTRL = ( USBOTG_FS->UEP1_TX_CTRL &= ~USBHD_UEP_T_RES_MASK ) | USBHD_UEP_T_RES_STALL;
//USBHS->UEP1_CTRL = ( USBHS->UEP1_CTRL & ~USBHS_EP_T_RES_MASK ) | USBHS_EP_T_RES_STALL;
break;
case 0x01:
/* <20><><EFBFBD>ö˵<C3B6>1 OUT STALL */
USBOTG_FS->UEP1_RX_CTRL = ( USBOTG_FS->UEP1_RX_CTRL &= ~USBHD_UEP_R_RES_MASK ) | USBHD_UEP_R_RES_STALL;
//USBHS->UEP1_CTRL = ( USBHS->UEP1_CTRL & ~USBHS_EP_R_RES_MASK ) | USBHS_EP_R_RES_STALL;
break;
default:
errflag = 0xFF;
break;
}
}
else
{
errflag = 0xFF;
}
}
else
{
errflag = 0xFF;
}
break;
case USB_GET_INTERFACE:
/* <20><>ȡ<EFBFBD>ӿ<EFBFBD> */
pEP0_DataBuf[0] = 0x00;
if ( SetupReqLen > 1 ) SetupReqLen = 1;
break;
case USB_SET_INTERFACE:
/* <20><><EFBFBD>ýӿ<C3BD> */
EP0_DatabufHD[ 0 ] = 0x00;
if( USBHD_Dev_SetupReqLen > 1 )
{
USBHD_Dev_SetupReqLen = 1;
}
break;
case USB_GET_STATUS:
/* <20><><EFBFBD>ݵ<EFBFBD>ǰ<EFBFBD>˵<EFBFBD>ʵ<EFBFBD><CAB5>״̬<D7B4><CCAC><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6> */
EP0_DatabufHD[ 0 ] = 0x00;
EP0_DatabufHD[ 1 ] = 0x00;
if( pMySetupReqPakHD->wIndex == 0x81 )
{
if( ( USBOTG_FS->UEP1_TX_CTRL & USBHD_UEP_T_RES_MASK ) == USBHD_UEP_T_RES_STALL )
{
EP0_DatabufHD[ 0 ] = 0x01;
}
}
else if( pMySetupReqPakHD->wIndex == 0x01 )
{
if( ( USBOTG_FS->UEP1_RX_CTRL & USBHD_UEP_R_RES_MASK ) == USBHD_UEP_R_RES_STALL )
{
EP0_DatabufHD[ 0 ] = 0x01;
}
}
else if( pMySetupReqPakHD->wIndex == 0x82 )
{
if( ( USBOTG_FS->UEP2_TX_CTRL & USBHD_UEP_T_RES_MASK ) == USBHD_UEP_T_RES_STALL )
{
EP0_DatabufHD[ 0 ] = 0x01;
}
}
else if( pMySetupReqPakHD->wIndex == 0x02 )
{
if( ( USBOTG_FS->UEP2_RX_CTRL & USBHD_UEP_R_RES_MASK ) == USBHD_UEP_R_RES_STALL )
{
EP0_DatabufHD[ 0 ] = 0x01;
}
}
if( USBHD_Dev_SetupReqLen > 2 )
{
USBHD_Dev_SetupReqLen = 2;
}
break;
default:
errflag = 0xFF;
break;
}
}
if( errflag == 0xff)
{
// printf("uep0 stall\n");
USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_TOG|USBHD_UEP_T_RES_STALL;
USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_TOG|USBHD_UEP_R_RES_STALL;
}
else
{
if( chtype & 0x80 )
{
len = (SetupReqLen>DevEP0SIZE) ? DevEP0SIZE : SetupReqLen;
SetupReqLen -= len;
}
else len = 0;
USBOTG_FS->UEP0_TX_LEN = len;
USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_TOG|USBHD_UEP_T_RES_ACK;
USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_TOG|USBHD_UEP_R_RES_ACK;
}
break;
case USBHD_UIS_TOKEN_IN:
switch ( USBOTG_FS->INT_ST & ( USBHD_UIS_TOKEN_MASK | USBHD_UIS_ENDP_MASK ) )
{
case USBHD_UIS_TOKEN_IN:
switch( SetupReqCode )
{
case USB_GET_DESCRIPTOR:
len = SetupReqLen >= DevEP0SIZE ? DevEP0SIZE : SetupReqLen;
memcpy( pEP0_DataBuf, pDescr, len );
SetupReqLen -= len;
pDescr += len;
USBOTG_FS->UEP0_TX_LEN = len;
USBOTG_FS->UEP0_TX_CTRL ^= USBHD_UEP_T_TOG;
break;
case USB_SET_ADDRESS:
USBOTG_FS->DEV_ADDR = (USBOTG_FS->DEV_ADDR&USBHD_UDA_GP_BIT) | SetupReqLen;
USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK;
USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK;
break;
default:
USBOTG_FS->UEP0_TX_LEN = 0;
USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK;
USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK;
break;
}
break;
case USBHD_UIS_TOKEN_IN | 1:
USBOTG_FS->UEP1_TX_CTRL = (USBHD_UEP1_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
USBOTG_FS->UEP1_TX_CTRL ^= USBHD_UEP_T_TOG;
break;
case USBHD_UIS_TOKEN_IN | 2:
USBOTG_FS->UEP2_TX_CTRL ^= USBHD_UEP_T_TOG;
USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK;
break;
default :
break;
}
break;
case USBHD_UIS_TOKEN_OUT:
switch ( USBOTG_FS->INT_ST & ( USBHD_UIS_TOKEN_MASK | USBHD_UIS_ENDP_MASK ) )
{
case USBHD_UIS_TOKEN_OUT:
switch( SetupReqCode )
{
case 0x20:
if((((LINECODINGST *)pEP0_DataBuf)->dataRat[0] || ((LINECODINGST *)pEP0_DataBuf)->dataRat[1] ||
((LINECODINGST *)pEP0_DataBuf)->dataRat[2] || ((LINECODINGST *)pEP0_DataBuf)->dataRat[3]))
{
printf( "\nBaud Rate = %d",
(((LINECODINGST *)pEP0_DataBuf)->dataRat[3] <<24) |
(((LINECODINGST *)pEP0_DataBuf)->dataRat[2] <<16) |
(((LINECODINGST *)pEP0_DataBuf)->dataRat[1] <<8) |
(((LINECODINGST *)pEP0_DataBuf)->dataRat[0]));
}
else
{
printf( "\ndataBit = %d", ((LINECODINGST *)pEP0_DataBuf)->dataBit);
printf( "\nstopBit = %d", ((LINECODINGST *)pEP0_DataBuf)->stopBit);
printf( "\nparityType = %d", ((LINECODINGST *)pEP0_DataBuf)->parityType);
}
break;
}
len = USBOTG_FS->RX_LEN;
break;
case USBHD_UIS_TOKEN_OUT | 1:
if ( USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK )
{
USBOTG_FS->UEP1_RX_CTRL ^= USBHD_UEP_R_TOG;
len = USBOTG_FS->RX_LEN;
// printf( "point 1 len %d\n", len );
DevEP1_OUT_Deal( len );
}
break;
case USBHD_UIS_TOKEN_OUT | 2:
if ( USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK )
{
USBOTG_FS->UEP2_RX_CTRL ^= USBHD_UEP_R_TOG;
len = USBOTG_FS->RX_LEN;
// printf( "point 2 len %d\n", len );
DevEP2_OUT_Deal( len );
}
break;
}
break;
case USBHD_UIS_TOKEN_SOF:
break;
default :
break;
}
USBOTG_FS->INT_FG = USBHD_UIF_TRANSFER;
}
else if( intflag & USBHD_UIF_BUS_RST )
{
USBOTG_FS->DEV_ADDR = 0;
USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK;
USBOTG_FS->UEP1_RX_CTRL = USBHD_UEP_R_RES_ACK;
USBOTG_FS->UEP2_RX_CTRL = USBHD_UEP_R_RES_ACK;
USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK;
USBOTG_FS->UEP1_TX_CTRL = USBHD_UEP_T_RES_NAK;
USBOTG_FS->UEP2_TX_CTRL = USBHD_UEP_T_RES_NAK;
USBOTG_FS->INT_FG |= USBHD_UIF_BUS_RST;
}
else if( intflag & USBHD_UIF_SUSPEND )
{
if ( USBOTG_FS->MIS_ST & USBHD_UMS_SUSPEND ) {;}
else{;}
USBOTG_FS->INT_FG = USBHD_UIF_SUSPEND;
}
else
{
USBOTG_FS->INT_FG = intflag;
}
}

746
libraries/sdk/Peripheral/ch32v30x_usbotg_device.h Normal file
View File

@@ -0,0 +1,746 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_usbotg_device.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* USBOTG firmware library.
*******************************************************************************/
#ifndef __CH32V30X_USBOTG_DEVICE_H_
#define __CH32V30X_USBOTG_DEVICE_H_
#include "string.h"
#ifndef NULL
#define NULL 0
#endif
#ifndef VOID
#define VOID void
#endif
#ifndef CONST
#define CONST const
#endif
#ifndef BOOL
typedef unsigned char BOOL;
#endif
#ifndef BOOLEAN
typedef unsigned char BOOLEAN;
#endif
#ifndef CHAR
typedef char CHAR;
#endif
#ifndef INT8
typedef char INT8;
#endif
#ifndef INT16
typedef short INT16;
#endif
#ifndef INT32
typedef long INT32;
#endif
#ifndef UINT8
typedef unsigned char UINT8;
#endif
#ifndef UINT16
typedef unsigned short UINT16;
#endif
#ifndef UINT32
typedef unsigned long UINT32;
#endif
#ifndef UINT8V
typedef unsigned char volatile UINT8V;
#endif
#ifndef UINT16V
typedef unsigned short volatile UINT16V;
#endif
#ifndef UINT32V
typedef unsigned long volatile UINT32V;
#endif
#ifndef PVOID
typedef void *PVOID;
#endif
#ifndef PCHAR
typedef char *PCHAR;
#endif
#ifndef PCHAR
typedef const char *PCCHAR;
#endif
#ifndef PINT8
typedef char *PINT8;
#endif
#ifndef PINT16
typedef short *PINT16;
#endif
#ifndef PINT32
typedef long *PINT32;
#endif
#ifndef PUINT8
typedef unsigned char *PUINT8;
#endif
#ifndef PUINT16
typedef unsigned short *PUINT16;
#endif
#ifndef PUINT32
typedef unsigned long *PUINT32;
#endif
#ifndef PUINT8V
typedef volatile unsigned char *PUINT8V;
#endif
#ifndef PUINT16V
typedef volatile unsigned short *PUINT16V;
#endif
#ifndef PUINT32V
typedef volatile unsigned long *PUINT32V;
#endif
/* USB constant and structure define */
/* USB PID */
#ifndef USB_PID_SETUP
#define USB_PID_NULL 0x00 /* reserved PID */
#define USB_PID_SOF 0x05
#define USB_PID_SETUP 0x0D
#define USB_PID_IN 0x09
#define USB_PID_OUT 0x01
#define USB_PID_ACK 0x02
#define USB_PID_NAK 0x0A
#define USB_PID_STALL 0x0E
#define USB_PID_DATA0 0x03
#define USB_PID_DATA1 0x0B
#define USB_PID_PRE 0x0C
#endif
/* USB standard device request code */
#ifndef USB_GET_DESCRIPTOR
#define USB_GET_STATUS 0x00
#define USB_CLEAR_FEATURE 0x01
#define USB_SET_FEATURE 0x03
#define USB_SET_ADDRESS 0x05
#define USB_GET_DESCRIPTOR 0x06
#define USB_SET_DESCRIPTOR 0x07
#define USB_GET_CONFIGURATION 0x08
#define USB_SET_CONFIGURATION 0x09
#define USB_GET_INTERFACE 0x0A
#define USB_SET_INTERFACE 0x0B
#define USB_SYNCH_FRAME 0x0C
#endif
/* USB hub class request code */
#ifndef HUB_GET_DESCRIPTOR
#define HUB_GET_STATUS 0x00
#define HUB_CLEAR_FEATURE 0x01
#define HUB_GET_STATE 0x02
#define HUB_SET_FEATURE 0x03
#define HUB_GET_DESCRIPTOR 0x06
#define HUB_SET_DESCRIPTOR 0x07
#endif
/* USB HID class request code */
#ifndef HID_GET_REPORT
#define HID_GET_REPORT 0x01
#define HID_GET_IDLE 0x02
#define HID_GET_PROTOCOL 0x03
#define HID_SET_REPORT 0x09
#define HID_SET_IDLE 0x0A
#define HID_SET_PROTOCOL 0x0B
#endif
/* Bit define for USB request type */
#ifndef USB_REQ_TYP_MASK
#define USB_REQ_TYP_IN 0x80 /* control IN, device to host */
#define USB_REQ_TYP_OUT 0x00 /* control OUT, host to device */
#define USB_REQ_TYP_READ 0x80 /* control read, device to host */
#define USB_REQ_TYP_WRITE 0x00 /* control write, host to device */
#define USB_REQ_TYP_MASK 0x60 /* bit mask of request type */
#define USB_REQ_TYP_STANDARD 0x00
#define USB_REQ_TYP_CLASS 0x20
#define USB_REQ_TYP_VENDOR 0x40
#define USB_REQ_TYP_RESERVED 0x60
#define USB_REQ_RECIP_MASK 0x1F /* bit mask of request recipient */
#define USB_REQ_RECIP_DEVICE 0x00
#define USB_REQ_RECIP_INTERF 0x01
#define USB_REQ_RECIP_ENDP 0x02
#define USB_REQ_RECIP_OTHER 0x03
#endif
/* USB request type for hub class request */
#ifndef HUB_GET_HUB_DESCRIPTOR
#define HUB_CLEAR_HUB_FEATURE 0x20
#define HUB_CLEAR_PORT_FEATURE 0x23
#define HUB_GET_BUS_STATE 0xA3
#define HUB_GET_HUB_DESCRIPTOR 0xA0
#define HUB_GET_HUB_STATUS 0xA0
#define HUB_GET_PORT_STATUS 0xA3
#define HUB_SET_HUB_DESCRIPTOR 0x20
#define HUB_SET_HUB_FEATURE 0x20
#define HUB_SET_PORT_FEATURE 0x23
#endif
/* Hub class feature selectors */
#ifndef HUB_PORT_RESET
#define HUB_C_HUB_LOCAL_POWER 0
#define HUB_C_HUB_OVER_CURRENT 1
#define HUB_PORT_CONNECTION 0
#define HUB_PORT_ENABLE 1
#define HUB_PORT_SUSPEND 2
#define HUB_PORT_OVER_CURRENT 3
#define HUB_PORT_RESET 4
#define HUB_PORT_POWER 8
#define HUB_PORT_LOW_SPEED 9
#define HUB_C_PORT_CONNECTION 16
#define HUB_C_PORT_ENABLE 17
#define HUB_C_PORT_SUSPEND 18
#define HUB_C_PORT_OVER_CURRENT 19
#define HUB_C_PORT_RESET 20
#endif
/* USB descriptor type */
#ifndef USB_DESCR_TYP_DEVICE
#define USB_DESCR_TYP_DEVICE 0x01
#define USB_DESCR_TYP_CONFIG 0x02
#define USB_DESCR_TYP_STRING 0x03
#define USB_DESCR_TYP_INTERF 0x04
#define USB_DESCR_TYP_ENDP 0x05
#define USB_DESCR_TYP_QUALIF 0x06
#define USB_DESCR_TYP_SPEED 0x07
#define USB_DESCR_TYP_OTG 0x09
#define USB_DESCR_TYP_BOS 0X0F
#define USB_DESCR_TYP_HID 0x21
#define USB_DESCR_TYP_REPORT 0x22
#define USB_DESCR_TYP_PHYSIC 0x23
#define USB_DESCR_TYP_CS_INTF 0x24
#define USB_DESCR_TYP_CS_ENDP 0x25
#define USB_DESCR_TYP_HUB 0x29
#endif
/* USB device class */
#ifndef USB_DEV_CLASS_HUB
#define USB_DEV_CLASS_RESERVED 0x00
#define USB_DEV_CLASS_AUDIO 0x01
#define USB_DEV_CLASS_COMMUNIC 0x02
#define USB_DEV_CLASS_HID 0x03
#define USB_DEV_CLASS_MONITOR 0x04
#define USB_DEV_CLASS_PHYSIC_IF 0x05
#define USB_DEV_CLASS_POWER 0x06
#define USB_DEV_CLASS_PRINTER 0x07
#define USB_DEV_CLASS_STORAGE 0x08
#define USB_DEV_CLASS_HUB 0x09
#define USB_DEV_CLASS_VEN_SPEC 0xFF
#endif
/* USB endpoint type and attributes */
#ifndef USB_ENDP_TYPE_MASK
#define USB_ENDP_DIR_MASK 0x80
#define USB_ENDP_ADDR_MASK 0x0F
#define USB_ENDP_TYPE_MASK 0x03
#define USB_ENDP_TYPE_CTRL 0x00
#define USB_ENDP_TYPE_ISOCH 0x01
#define USB_ENDP_TYPE_BULK 0x02
#define USB_ENDP_TYPE_INTER 0x03
#endif
#ifndef USB_DEVICE_ADDR
#define USB_DEVICE_ADDR 0x02
#endif
#ifndef DEFAULT_ENDP0_SIZE
#define DEFAULT_ENDP0_SIZE 8 /* default maximum packet size for endpoint 0 */
#endif
#ifndef MAX_PACKET_SIZE
#define MAX_PACKET_SIZE 64 /* maximum packet size */
#endif
#ifndef USB_BO_CBW_SIZE
#define USB_BO_CBW_SIZE 0x1F
#define USB_BO_CSW_SIZE 0x0D
#endif
#ifndef USB_BO_CBW_SIG0
#define USB_BO_CBW_SIG0 0x55
#define USB_BO_CBW_SIG1 0x53
#define USB_BO_CBW_SIG2 0x42
#define USB_BO_CBW_SIG3 0x43
#define USB_BO_CSW_SIG0 0x55
#define USB_BO_CSW_SIG1 0x53
#define USB_BO_CSW_SIG2 0x42
#define USB_BO_CSW_SIG3 0x53
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
typedef struct __PACKED _USB_SETUP_REQ {
UINT8 bRequestType;
UINT8 bRequest;
UINT16 wValue;
UINT16 wIndex;
UINT16 wLength;
} USB_SETUP_REQ, *PUSB_SETUP_REQ;
typedef struct __PACKED _USB_DEVICE_DESCR {
UINT8 bLength;
UINT8 bDescriptorType;
UINT16 bcdUSB;
UINT8 bDeviceClass;
UINT8 bDeviceSubClass;
UINT8 bDeviceProtocol;
UINT8 bMaxPacketSize0;
UINT16 idVendor;
UINT16 idProduct;
UINT16 bcdDevice;
UINT8 iManufacturer;
UINT8 iProduct;
UINT8 iSerialNumber;
UINT8 bNumConfigurations;
} USB_DEV_DESCR, *PUSB_DEV_DESCR;
typedef struct __PACKED _USB_CONFIG_DESCR {
UINT8 bLength;
UINT8 bDescriptorType;
UINT16 wTotalLength;
UINT8 bNumInterfaces;
UINT8 bConfigurationValue;
UINT8 iConfiguration;
UINT8 bmAttributes;
UINT8 MaxPower;
} USB_CFG_DESCR, *PUSB_CFG_DESCR;
typedef struct __PACKED _USB_INTERF_DESCR {
UINT8 bLength;
UINT8 bDescriptorType;
UINT8 bInterfaceNumber;
UINT8 bAlternateSetting;
UINT8 bNumEndpoints;
UINT8 bInterfaceClass;
UINT8 bInterfaceSubClass;
UINT8 bInterfaceProtocol;
UINT8 iInterface;
} USB_ITF_DESCR, *PUSB_ITF_DESCR;
typedef struct __PACKED _USB_ENDPOINT_DESCR {
UINT8 bLength;
UINT8 bDescriptorType;
UINT8 bEndpointAddress;
UINT8 bmAttributes;
UINT16 wMaxPacketSize;
UINT8 bInterval;
} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
typedef struct __PACKED _USB_CONFIG_DESCR_LONG {
USB_CFG_DESCR cfg_descr;
USB_ITF_DESCR itf_descr;
USB_ENDP_DESCR endp_descr[1];
} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
typedef struct __PACKED _USB_HUB_DESCR {
UINT8 bDescLength;
UINT8 bDescriptorType;
UINT8 bNbrPorts;
UINT8 wHubCharacteristicsL;
UINT8 wHubCharacteristicsH;
UINT8 bPwrOn2PwrGood;
UINT8 bHubContrCurrent;
UINT8 DeviceRemovable;
UINT8 PortPwrCtrlMask;
} USB_HUB_DESCR, *PUSB_HUB_DESCR;
typedef struct __PACKED _USB_HID_DESCR {
UINT8 bLength;
UINT8 bDescriptorType;
UINT16 bcdHID;
UINT8 bCountryCode;
UINT8 bNumDescriptors;
UINT8 bDescriptorTypeX;
UINT8 wDescriptorLengthL;
UINT8 wDescriptorLengthH;
} USB_HID_DESCR, *PUSB_HID_DESCR;
typedef struct __PACKED _UDISK_BOC_CBW {/* command of BulkOnly USB-FlashDisk */
UINT32 mCBW_Sig;
UINT32 mCBW_Tag;
UINT32 mCBW_DataLen; /* uppest byte of data length, always is 0 */
UINT8 mCBW_Flag; /* transfer direction and etc. */
UINT8 mCBW_LUN;
UINT8 mCBW_CB_Len; /* length of command block */
UINT8 mCBW_CB_Buf[16]; /* command block buffer */
} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
typedef struct __PACKED _UDISK_BOC_CSW {/* status of BulkOnly USB-FlashDisk */
UINT32 mCBW_Sig;
UINT32 mCBW_Tag;
UINT32 mCSW_Residue; /* return: remainder bytes */ /* uppest byte of remainder length, always is 0 */
UINT8 mCSW_Status; /* return: result status */
} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
/* <20><><EFBFBD><EFBFBD><EFBFBD>Ժ궨<D4BA><EAB6A8> */
#define USE_SYS_CLK 0
//#define USBHD_HOST 0
//#define USB_OTG 0
/******************************************************************************/
/* USBOTG_FS DEVICE USB_CONTROL */
/* BASE USB_CTRL */
#define USBHD_BASE_CTRL (USBOTG_FS->BASE_CTRL) // USB base control
#define USBHD_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode
#define USBHD_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps
#define USBHD_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable
#define USBHD_UC_SYS_CTRL1 0x20 // USB system control high bit
#define USBHD_UC_SYS_CTRL0 0x10 // USB system control low bit
#define USBHD_UC_SYS_CTRL_MASK 0x30 // bit mask of USB system control
// UC_HOST_MODE & UC_SYS_CTRL1 & UC_SYS_CTRL0: USB system control
// 0 00: disable USB device and disable internal pullup resistance
// 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance
// 0 1x: enable USB device and enable internal pullup resistance
// 1 00: enable USB host and normal status
// 1 01: enable USB host and force UDP/UDM output SE0 state
// 1 10: enable USB host and force UDP/UDM output J state
// 1 11: enable USB host and force UDP/UDM output resume or K state
#define USBHD_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid
#define USBHD_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear
#define USBHD_UC_CLR_ALL 0x02 // force clear FIFO and count of USB
#define USBHD_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB
/* DEVICE USB_CTRL */
#define USBHD_UDEV_CTRL (USBOTG_FS->UDEV_CTRL) // USB device physical prot control
#define USBHD_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
#define USBHD_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
#define USBHD_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
#define USBHD_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed
#define USBHD_UD_GP_BIT 0x02 // general purpose bit
#define USBHD_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable
/* USB INT EN */
#define USBHD_INT_EN (USBOTG_FS->INT_EN) // USB interrupt enable
#define USBHD_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode
#define USBHD_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode
#define USBHD_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow
#define USBHD_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode
#define USBHD_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event
#define USBHD_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion
#define USBHD_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode
#define USBHD_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode
/* USB_DEV_ADDR */
#define USBHD_DEV_ADDR (USBOTG_FS->DEV_ADDR) // USB device address
#define USBHD_UDA_GP_BIT 0x80 // general purpose bit
#define USBHD_USB_ADDR_MASK 0x7F // bit mask for USB device address
/* USBOTG_FS DEVICE USB_STATUS */
/* USB_MIS_ST */
#define USBHD_MIS_ST (USBOTG_FS->MIS_ST) // USB miscellaneous status
#define USBHD_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status
#define USBHD_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host
#define USBHD_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status
#define USBHD_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty)
#define USBHD_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status
#define USBHD_UMS_SUSPEND 0x04 // RO, indicate USB suspend status
#define USBHD_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host
#define USBHD_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host
/* USB_INT_FG */
#define USBHD_INT_FG (USBOTG_FS->INT_FG) // USB interrupt flag
#define USBHD_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received
#define USBHD_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
#define USBHD_U_SIE_FREE 0x20 // RO, indicate USB SIE free status
#define USBHD_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
#define USBHD_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
#define USBHD_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
#define USBHD_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
#define USBHD_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
#define USBHD_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
/* USB_INT_ST */
#define USBHD_INT_ST (USBOTG_FS->INT_ST) // USB interrupt flag
#define USBHD_UIS_IS_SETUP 0x80 // RO, indicate current USB transfer is setup received for USB device mode
#define USBHD_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode
#define USBHD_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
#define USBHD_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode
#define USBHD_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode
#define USBHD_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode
#define USBHD_UIS_TOKEN_OUT 0x00
#define USBHD_UIS_TOKEN_SOF 0x10
#define USBHD_UIS_TOKEN_IN 0x20
#define USBHD_UIS_TOKEN_SETUP 0x30
// UIS_TOKEN1 & UIS_TOKEN0: current token PID code received for USB device mode
// 00: OUT token PID received
// 01: SOF token PID received
// 10: IN token PID received
// 11: SETUP token PID received
#define USBHD_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode
/* USB_RX_LEN */
#define USBHD_RX_LEN (USBOTG_FS->Rx_Len) // USB receiving length
/* USB_BUF_MOD */
#define USBHD_UEP4_1_MOD (USBOTG_FS->UEP4_1_MOD) // endpoint 4/1 mode
#define USBHD_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT)
#define USBHD_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN)
#define USBHD_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1
// UEPn_RX_EN & UEPn_TX_EN & UEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
// 0 0 x: disable endpoint and disable buffer
// 1 0 0: 64 bytes buffer for receiving (OUT endpoint)
// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
// 0 1 0: 64 bytes buffer for transmittal (IN endpoint)
// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
#define USBHD_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT)
#define USBHD_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN)
// UEP4_RX_EN & UEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
#define USBHD_UEP2_3_MOD (USBOTG_FS->UEP2_3_MOD) // endpoint 2/3 mode
#define USBHD_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT)
#define USBHD_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN)
#define USBHD_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3
#define USBHD_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT)
#define USBHD_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN)
#define USBHD_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2
#define USBHD_UEP5_6_MOD (USBOTG_FS->UEP5_6_MOD) // endpoint 5/6 mode
#define USBHD_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT)
#define USBHD_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN)
#define USBHD_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6
#define USBHD_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT)
#define USBHD_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN)
#define USBHD_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5
#define USBHD_UEP7_MOD (USBOTG_FS->UEP7_MOD) // endpoint 7 mode
#define USBHD_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT)
#define USBHD_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN)
#define USBHD_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7
/* USB_DMA */
#define USBHD_UEP0_DMA (USBOTG_FS->UEP0_DMA) // endpoint 0 DMA buffer address
#define USBHD_UEP1_DMA (USBOTG_FS->UEP1_DMA) // endpoint 1 DMA buffer address
#define USBHD_UEP2_DMA (USBOTG_FS->UEP2_DMA) // endpoint 2 DMA buffer address
#define USBHD_UEP3_DMA (USBOTG_FS->UEP3_DMA) // endpoint 3 DMA buffer address
#define USBHD_UEP4_DMA (USBOTG_FS->UEP4_DMA) // endpoint 4 DMA buffer address
#define USBHD_UEP5_DMA (USBOTG_FS->UEP5_DMA) // endpoint 5 DMA buffer address
#define USBHD_UEP6_DMA (USBOTG_FS->UEP6_DMA) // endpoint 6 DMA buffer address
#define USBHD_UEP7_DMA (USBOTG_FS->UEP7_DMA) // endpoint 7 DMA buffer address
/* USB_EP_CTRL */
#define USBHD_UEP0_T_LEN (USBOTG_FS->UEP0_TX_LEN) // endpoint 0 transmittal length
#define USBHD_UEP0_TX_CTRL (USBOTG_FS->UEP0_TX_CTRL) // endpoint 0 control
#define USBHD_UEP0_RX_CTRL (USBOTG_FS->UEP0_RX_CTRL) // endpoint 0 control
#define USBHD_UEP1_T_LEN (USBOTG_FS->UEP1_TX_LEN) // endpoint 1 transmittal length
#define USBHD_UEP1_TX_CTRL (USBOTG_FS->UEP1_TX_CTRL) // endpoint 1 control
#define USBHD_UEP1_RX_CTRL (USBOTG_FS->UEP1_RX_CTRL) // endpoint 1 control
#define USBHD_UEP2_T_LEN (USBOTG_FS->UEP2_TX_LEN) // endpoint 2 transmittal length
#define USBHD_UEP2_TX_CTRL (USBOTG_FS->UEP2_TX_CTRL) // endpoint 2 control
#define USBHD_UEP2_RX_CTRL (USBOTG_FS->UEP2_RX_CTRL) // endpoint 2 control
#define USBHD_UEP3_T_LEN (USBOTG_FS->UEP3_TX_LEN) // endpoint 3 transmittal length
#define USBHD_UEP3_TX_CTRL (USBOTG_FS->UEP3_TX_CTRL) // endpoint 3 control
#define USBHD_UEP3_RX_CTRL (USBOTG_FS->UEP3_RX_CTRL) // endpoint 3 control
#define USBHD_UEP4_T_LEN (USBOTG_FS->UEP4_TX_LEN) // endpoint 4 transmittal length
#define USBHD_UEP4_TX_CTRL (USBOTG_FS->UEP4_TX_CTRL) // endpoint 4 control
#define USBHD_UEP4_RX_CTRL (USBOTG_FS->UEP4_RX_CTRL) // endpoint 4 control
#define USBHD_UEP5_T_LEN (USBOTG_FS->UEP5_TX_LEN) // endpoint 5 transmittal length
#define USBHD_UEP5_TX_CTRL (USBOTG_FS->UEP5_TX_CTRL) // endpoint 5 control
#define USBHD_UEP5_RX_CTRL (USBOTG_FS->UEP5_RX_CTRL) // endpoint 5 control
#define USBHD_UEP6_T_LEN (USBOTG_FS->UEP6_TX_LEN) // endpoint 6 transmittal length
#define USBHD_UEP6_TX_CTRL (USBOTG_FS->UEP6_TX_CTRL) // endpoint 6 control
#define USBHD_UEP6_RX_CTRL (USBOTG_FS->UEP6_RX_CTRL) // endpoint 6 control
#define USBHD_UEP7_T_LEN (USBOTG_FS->UEP7_TX_LEN) // endpoint 7 transmittal length
#define USBHD_UEP7_TX_CTRL (USBOTG_FS->UEP7_TX_CTRL) // endpoint 7 control
#define USBHD_UEP7_RX_CTRL (USBOTG_FS->UEP7_RX_CTRL) // endpoint 7 control
#define USBHD_UEP_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
#define USBHD_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
#define USBHD_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
#define USBHD_UEP_R_RES1 0x02 // handshake response type high bit for USB endpoint X receiving (OUT)
#define USBHD_UEP_R_RES0 0x01 // handshake response type low bit for USB endpoint X receiving (OUT)
#define USBHD_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT)
#define USBHD_UEP_R_RES_ACK 0x00
#define USBHD_UEP_R_RES_TOUT 0x01
#define USBHD_UEP_R_RES_NAK 0x02
#define USBHD_UEP_R_RES_STALL 0x03
// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
// 00: ACK (ready)
// 01: no response, time out to host, for non-zero endpoint isochronous transactions
// 10: NAK (busy)
// 11: STALL (error)
#define USBHD_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN)
#define USBHD_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN)
#define USBHD_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN)
#define USBHD_UEP_T_RES_ACK 0x00
#define USBHD_UEP_T_RES_TOUT 0x01
#define USBHD_UEP_T_RES_NAK 0x02
#define USBHD_UEP_T_RES_STALL 0x03
// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
// 00: DATA0 or DATA1 then expecting ACK (ready)
// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
// 10: NAK (busy)
// 11: TALL (error)
#ifdef USBHD_HOST
/* USBOTG_FS HOST CONTROL&CFG */
/* HOST USB_CTRL */
#define USBHD_UHOST_CTRL (USBOTG_FS->UDEV_CTRL) // USB host physical prot control
#define USBHD_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
#define USBHD_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
#define USBHD_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
#define USBHD_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed
#define USBHD_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset
#define USBHD_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
/* USB_INT_ST */
#define USBHD_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
/* USB_BUF_MOD */
#define USBHD_UH_EP_MOD USBHD_UEP2_3_MOD //host endpoint mode
#define USBHD__UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal
#define USBHD__UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint
// UH_EP_TX_EN & UH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
// 0 x: disable endpoint and disable buffer
// 1 0: 64 bytes buffer for transmittal (OUT endpoint)
// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
#define USBHD_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving
#define USBHD_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint
// UH_EP_RX_EN & UH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
// 0 x: disable endpoint and disable buffer
// 1 0: 64 bytes buffer for receiving (IN endpoint)
// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
/* USB_DMA */
#define USBHD_UH_RX_DMA USBHD_UEP2_DMA // host rx endpoint buffer high address
#define USBHD_UH_TX_DMA USBHD_UEP3_DMA // host tx endpoint buffer high address
/* USB_HOST_SETUP */
#define USBHD_UH_SETUP (*((PUINT16V)(0x50000036))) // host aux setup
#define USBHD_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub
#define USBHD_UH_SOF_EN 0x04 // USB host automatic SOF enable
#define USBHD_UH_EP_PID USBHD_UEP2_T_LEN // host endpoint and PID
#define USBHD_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer
#define USBHD_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer
#define USBHD_UH_RX_CTRL USBHD_UEP2_RX_CTRL // host receiver endpoint control
#define USBHD_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
#define USBHD_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
#define USBHD_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
#define USBHD_UH_RX_CTRL USBHD_UEP2_RX_CTRL // host receiver endpoint control
#define USBHD_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
#define USBHD_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
#define USBHD_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
#define USBHD_UH_TX_LEN USBHD_UEP3_T_LEN // host transmittal endpoint transmittal length
#define USBHD_UH_TX_CTRL USBHD_UEP3_TX_CTRL // host transmittal endpoint control
#define USBHD_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
#define USBHD_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
#define USBHD_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
#endif
#ifdef USB_OTG
#define USB_OTG_CR (USBOTG_FS->OTG_CR) // usb otg control
#define USB_OTG_CR_SESS 0x20 // usb otg control,<2C>Ự<EFBFBD><E1BBB0>ƽʹ<C6BD><CAB9>
#define USB_OTG_CR_VBUS 0x10 // usb otg control,VBUS<55><53>ƽʹ<C6BD><CAB9>
#define USB_OTG_CR_OTG_EN 0x08 // usb otg control,OTG<54><47><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
#define USB_OTG_CR_IDPU 0x04 // usb otg control,ID<49><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define USB_OTG_CR_CHARGEVBUS 0x02 // usb otg control,VBUS<55><53><EFBFBD><EFBFBD>
#define USB_OTG_CR_DISCHARGEVBUS 0x01 // usb otg control,VBUS<55>ŵ<EFBFBD>
#define USB_OTG_SR (USBOTG_FS->OTG_CR) // usb otg status
#define USB_OTG_SR_VBUS_VLD 0x01 // usb otg status,A<>豸VBUS<55><53><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽ<EFBFBD><C6BD>Ч
#define USB_OTG_SR_SESS_VLD 0x02 // usb otg status,<2C>Ự<EFBFBD><E1BBB0>Ч<EFBFBD><D0A7>ƽ<EFBFBD><C6BD>Ч<EFBFBD><D0A7>־
#define USB_OTG_SR_SESS_END 0x04 // usb otg status,<2C>Ự<EFBFBD><E1BBB0><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽ<EFBFBD><C6BD>Ч<EFBFBD><D0A7>־
#define USB_OTG_SR_ID_DIG 0x08 // usb otg status,ID<49><44>ƽ
#endif
/******************************************************************************/
/* USBHS PHY Clock Config (RCC_CFGR2) ʹ<><CAB9>USBHS PHYʱ<59>ӵ<EFBFBD><D3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>£<EFBFBD><C2A3><EFBFBD>Ҫ<EFBFBD>õ<EFBFBD><C3B5><EFBFBD>Щ<EFBFBD>궨<EFBFBD><EAB6A8> */
#ifndef USBHS_EXIST
#define USB_48M_CLK_SRC_MASK (1<<31)
#define USB_48M_CLK_SRC_SYS (0<<31)
#define USB_48M_CLK_SRC_PHY (1<<31)
#define USBHS_PLL_ALIVE (1<<30)
#define USBHS_PLL_CKREF_MASK (3<<28)
#define USBHS_PLL_CKREF_3M (0<<28)
#define USBHS_PLL_CKREF_4M (1<<28)
#define USBHS_PLL_CKREF_8M (2<<28)
#define USBHS_PLL_CKREF_5M (3<<28)
#define USBHS_PLL_SRC_MASK (1<<27)
#define USBHS_PLL_SRC_HSE (0<<27)
#define USBHS_PLL_SRC_HSI (1<<27)
#define USBHS_PLL_SRC_PRE_MASK (7<<24)
#define USBHS_PLL_SRC_PRE_DIV1 (0<<24)
#define USBHS_PLL_SRC_PRE_DIV2 (1<<24)
#define USBHS_PLL_SRC_PRE_DIV3 (2<<24)
#define USBHS_PLL_SRC_PRE_DIV4 (3<<24)
#define USBHS_PLL_SRC_PRE_DIV5 (4<<24)
#define USBHS_PLL_SRC_PRE_DIV6 (5<<24)
#define USBHS_PLL_SRC_PRE_DIV7 (6<<24)
/* <20>˵<EFBFBD><CBB5><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD> */
#define DEF_USB_FS_EP_SIZE 64
#endif
/*ʹ<><CAB9>sysclkʱ<6B>ӵ<EFBFBD><D3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>£<EFBFBD><C2A3><EFBFBD>Ҫ<EFBFBD>õ<EFBFBD><C3B5><EFBFBD>Щ<EFBFBD>궨<EFBFBD><EAB6A8> */
#define RCC_USBFS_CLK_DIV_1 (0<<22)
#define RCC_USBFS_CLK_DIV_2 (1<<22)
#define RCC_USBFS_CLK_DIV_3 (2<<22)
#define RCC_USBFS_CLK_SRC (1<<31)
/******************************************************************************/
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
extern PUINT8 pEP0_RAM_Addr; //ep0(64)
extern PUINT8 pEP1_RAM_Addr; //ep1_out(64)+ep1_in(64)
extern PUINT8 pEP2_RAM_Addr; //ep2_out(64)+ep2_in(64)
extern PUINT8 pEP3_RAM_Addr; //ep3_out(64)+ep3_in(64)
extern PUINT8 pEP4_RAM_Addr; //ep4_out(64)+ep4_in(64)
extern PUINT8 pEP5_RAM_Addr; //ep5_out(64)+ep5_in(64)
extern PUINT8 pEP6_RAM_Addr; //ep6_out(64)+ep6_in(64)
extern PUINT8 pEP7_RAM_Addr; //ep7_out(64)+ep7_in(64)
extern volatile UINT16 USBHD_Endp1_Up_Flag; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>״̬: 0:<3A><><EFBFBD><EFBFBD>; 1:<3A><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>; */
extern volatile UINT8 USBHD_Endp1_Down_Flag; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>1<EFBFBD>´<EFBFBD><EFBFBD>ɹ<EFBFBD><EFBFBD><EFBFBD>־ */
extern volatile UINT8 USBHD_Endp1_Down_Len; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>1<EFBFBD>´<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
extern volatile BOOL USBHD_Endp1_T_Tog; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>togλ<EFBFBD><EFBFBD>ת */
extern volatile BOOL USBHD_Endp1_R_Tog;
extern volatile UINT16 USBHD_Endp2_Up_Flag; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>״̬: 0:<3A><><EFBFBD><EFBFBD>; 1:<3A><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>; */
extern volatile UINT16 USBHD_Endp2_Up_LoadPtr; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>װ<EFBFBD><EFBFBD>ƫ<EFBFBD><EFBFBD> */
extern volatile UINT8 USBHD_Endp2_Down_Flag; /* USB2.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>˵<EFBFBD>2<EFBFBD>´<EFBFBD><EFBFBD>ɹ<EFBFBD><EFBFBD><EFBFBD>־ */
/******************************************************************************/
/* DMA<4D><41>ַ<EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>غ궨<D8BA><EAB6A8> */
#define pSetupReqPakHD ((PUSB_SETUP_REQ)pEP0_RAM_Addr)
#define pEP0_DataBuf (pEP0_RAM_Addr)
#define pEP1_OUT_DataBuf (pEP1_RAM_Addr)
#define pEP1_IN_DataBuf (pEP1_RAM_Addr+64)
#define pEP2_OUT_DataBuf (pEP2_RAM_Addr)
#define pEP2_IN_DataBuf (pEP2_RAM_Addr+64)
/******************************************************************************/
/* <20>˵<EFBFBD>״̬<D7B4><CCAC>ȡ<EFBFBD>궨<EFBFBD><EAB6A8> */
#define EP1_GetINSta() (R8_UEP1_CTRL&UEP_T_RES_NAK)
#define EP2_GetINSta() (R8_UEP2_CTRL&UEP_T_RES_NAK)
#define EP3_GetINSta() (R8_UEP3_CTRL&UEP_T_RES_NAK)
/******************************************************************************/
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
extern UINT8 EP0_DatabufHD[8]; //ep0(64)
extern UINT8 EP1_DatabufHD[64+64]; //ep1_out(64)+ep1_in(64)
extern UINT8 EP2_DatabufHD[64+64]; //ep2_out(64)+ep2_in(64) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD>
extern void DevEP2_IN_Deal( UINT8 l );
extern void USBOTG_RCC_Init( void );
extern void USBDeviceInit( void );
#endif

139
libraries/sdk/Peripheral/ch32v30x_wwdg.c Normal file
View File

@@ -0,0 +1,139 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_wwdg.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the WWDG firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
**********************************************************************************/
#include "ch32v30x_wwdg.h"
#include "ch32v30x_rcc.h"
/* CTLR register bit mask */
#define CTLR_WDGA_Set ((uint32_t)0x00000080)
/* CFGR register bit mask */
#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
#define CFGR_W_Mask ((uint32_t)0xFFFFFF80)
#define BIT_Mask ((uint8_t)0x7F)
/*********************************************************************
* @fn WWDG_DeInit
*
* @brief Deinitializes the WWDG peripheral registers to their default reset values
*
* @return none
*/
void WWDG_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
}
/*********************************************************************
* @fn WWDG_SetPrescaler
*
* @brief Sets the WWDG Prescaler
*
* @param WWDG_Prescaler - specifies the WWDG Prescaler
* WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1
* WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2
* WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4
* WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8
*
* @return none
*/
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
{
uint32_t tmpreg = 0;
tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask;
tmpreg |= WWDG_Prescaler;
WWDG->CFGR = tmpreg;
}
/*********************************************************************
* @fn WWDG_SetWindowValue
*
* @brief Sets the WWDG window value
*
* @param WindowValue - specifies the window value to be compared to the
* downcounter,which must be lower than 0x80
*
* @return none
*/
void WWDG_SetWindowValue(uint8_t WindowValue)
{
__IO uint32_t tmpreg = 0;
tmpreg = WWDG->CFGR & CFGR_W_Mask;
tmpreg |= WindowValue & (uint32_t)BIT_Mask;
WWDG->CFGR = tmpreg;
}
/*********************************************************************
* @fn WWDG_EnableIT
*
* @brief Enables the WWDG Early Wakeup interrupt(EWI)
*
* @return none
*/
void WWDG_EnableIT(void)
{
WWDG->CFGR |= (1 << 9);
}
/*********************************************************************
* @fn WWDG_SetCounter
*
* @brief Sets the WWDG counter value
*
* @param Counter - specifies the watchdog counter value,which must be a
* number between 0x40 and 0x7F
*
* @return none
*/
void WWDG_SetCounter(uint8_t Counter)
{
WWDG->CTLR = Counter & BIT_Mask;
}
/*********************************************************************
* @fn WWDG_Enable
*
* @brief Enables WWDG and load the counter value
*
* @param Counter - specifies the watchdog counter value,which must be a
* number between 0x40 and 0x7F
* @return none
*/
void WWDG_Enable(uint8_t Counter)
{
WWDG->CTLR = CTLR_WDGA_Set | Counter;
}
/*********************************************************************
* @fn WWDG_GetFlagStatus
*
* @brief Checks whether the Early Wakeup interrupt flag is set or not
*
* @return The new state of the Early Wakeup interrupt flag (SET or RESET)
*/
FlagStatus WWDG_GetFlagStatus(void)
{
return (FlagStatus)(WWDG->STATR);
}
/*********************************************************************
* @fn WWDG_ClearFlag
*
* @brief Clears Early Wakeup interrupt flag
*
* @return none
*/
void WWDG_ClearFlag(void)
{
WWDG->STATR = (uint32_t)RESET;
}

42
libraries/sdk/Peripheral/ch32v30x_wwdg.h Normal file
View File

@@ -0,0 +1,42 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_wwdg.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the WWDG
* firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_WWDG_H
#define __CH32V30x_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v30x.h"
/* WWDG_Prescaler */
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
void WWDG_DeInit(void);
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_EnableIT(void);
void WWDG_SetCounter(uint8_t Counter);
void WWDG_Enable(uint8_t Counter);
FlagStatus WWDG_GetFlagStatus(void);
void WWDG_ClearFlag(void);
#ifdef __cplusplus
}
#endif
#endif