From 75b9cc4a8f403e17b45e9f2dcb9e89e21705e35f Mon Sep 17 00:00:00 2001
From: bmy <2583236812@qq.com>
Date: Mon, 15 Apr 2024 23:08:37 +0800
Subject: [PATCH] =?UTF-8?q?feat:=20=E6=A0=B9=E6=8D=AE=E6=96=B0=E6=9D=BF?=
 =?UTF-8?q?=E5=8D=A1QD4C=E6=9B=B4=E6=96=B0=E6=97=B6=E9=92=9F=E9=85=8D?=
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硬件上更换为 16MHz 的外部晶振，将PLL输入源更改为二分频之后的HSE，后续倍频系数不变（仅更改了144MHz下的配置）
---
 app/main.c                            |  2 +-
 libraries/zf_common/zf_common_clock.c | 12 ++++++------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/app/main.c b/app/main.c
index 2d92396..5559070 100644
--- a/app/main.c
+++ b/app/main.c
@@ -39,7 +39,7 @@ uint8_t last_state;
 int main(void)
 {
     TYPE_UNION test_data[BY_FRAME_DATA_NUM];
-    clock_init(SYSTEM_CLOCK_120M);
+    clock_init(SYSTEM_CLOCK_144M);
     system_delay_init();
     debug_init();
 
diff --git a/libraries/zf_common/zf_common_clock.c b/libraries/zf_common/zf_common_clock.c
index f72bcf8..8354214 100644
--- a/libraries/zf_common/zf_common_clock.c
+++ b/libraries/zf_common/zf_common_clock.c
@@ -2,11 +2,11 @@
  * CH32V307VCT6 Opensourec Library ����CH32V307VCT6 ��Դ�⣩��һ�����ڹٷ� SDK �ӿڵĵ�������Դ��
  * Copyright (c) 2022 SEEKFREE ��ɿƼ�
  *
- * ���ļ���CH32V307VCT6 ��Դ���һ����
+ * ���ļ��� CH32V307VCT6 ��Դ���һ����
  *
  * CH32V307VCT6 ��Դ�� ���������
- * �����Ը���������������ᷢ���� GPL��GNU General Public License���� GNUͨ�ù�������֤��������
- * �� GPL �ĵ�3�棨�� GPL3.0������ѡ��ģ��κκ����İ汾�����·�����/���޸���
+ * �����Ը���������������ᷢ���� GPL��GNU General Public License���� GNU ͨ�ù�������֤��������
+ * �� GPL �ĵ� 3 �棨�� GPL3.0������ѡ��ģ��κκ����İ汾�����·�����/���޸���
  *
  * ����Դ��ķ�����ϣ�����ܷ������ã�����δ�������κεı�֤
  * ����û�������������Ի��ʺ��ض���;�ı�֤
@@ -30,7 +30,7 @@
  *
  * �޸ļ�¼
  * ����                                      ����                             ��ע
- * 2022-09-15        ��W            first version
+ * 2022-09-15        �� W            first version
  ********************************************************************************************************************/
 
 #include "ch32v30x.h"
@@ -48,7 +48,7 @@ uint32 system_clock = SYSTEM_CLOCK_144M;                               // ϵͳʱ
 //-------------------------------------------------------------------------------------------------------------------
 void clock_reset(void)
 {
-    RCC->CTLR  |= (uint32) 0x00000001;      //ʹ��HSI����
+    RCC->CTLR  |= (uint32) 0x00000001;      //ʹ�� HSI ����
     RCC->CFGR0 &= (uint32) 0xF8FF0000;
     RCC->CTLR  &= (uint32) 0xFEF6FFFF;
     RCC->CTLR  &= (uint32) 0xFFFBFFFF;
@@ -105,7 +105,7 @@ void clock_set_freq(uint32 clock)
                 | RCC_PLLMULL));
 
         if (clock == SYSTEM_CLOCK_144M)
-            RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
+            RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE_Div2 
                     | RCC_PLLMULL18_EXTEN);
         else if (clock == SYSTEM_CLOCK_120M)
             RCC->CFGR0 |= (uint32) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE