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393
libraries/cmsis/cm4/device_support/at32f425.h Normal file
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/**
**************************************************************************
* @file at32f425.h
* @brief at32f425 header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#ifndef __AT32F425_H
#define __AT32F425_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup AT32F425
* @{
*/
/** @addtogroup Library_configuration_section
* @{
*/
/**
* tip: to avoid modifying this file each time you need to switch between these
* devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (AT32F425R8T7) && !defined (AT32F425R8T7_7) && !defined (AT32F425C8T7) && \
!defined (AT32F425C8U7) && !defined (AT32F425K8T7) && !defined (AT32F425K8U7_4) && \
!defined (AT32F425F8P7) && !defined (AT32F425G8U7) && !defined (AT32F425R6T7) && \
!defined (AT32F425R6T7_7) && !defined (AT32F425C6T7) && !defined (AT32F425C6U7) && \
!defined (AT32F425K6T7) && !defined (AT32F425K6U7_4) && !defined (AT32F425F6P7) && \
!defined (AT32F425G6U7)
#error "Please select first the target device used in your application (in at32f425.h file)"
#endif
#if defined (AT32F425R8T7) || defined (AT32F425R8T7_7) || defined (AT32F425C8T7) || \
defined (AT32F425C8U7) || defined (AT32F425K8T7) || defined (AT32F425K8U7_4) || \
defined (AT32F425F8P7) || defined (AT32F425G8U7) || defined (AT32F425R6T7) || \
defined (AT32F425R6T7_7) || defined (AT32F425C6T7) || defined (AT32F425C6U7) || \
defined (AT32F425K6T7) || defined (AT32F425K6U7_4) || defined (AT32F425F6P7) || \
defined (AT32F425G6U7)
#define AT32F425xx
#endif
/**
* define with package
*/
#if defined (AT32F425R8T7) || defined (AT32F425R8T7_7) || defined (AT32F425R6T7) || \
defined (AT32F425R6T7_7)
#define AT32F425Rx
#endif
#if defined (AT32F425C8T7) || defined (AT32F425C8U7) || defined (AT32F425C6T7) || \
defined (AT32F425C6U7)
#define AT32F425Cx
#endif
#if defined (AT32F425K8T7) || defined (AT32F425K8U7_4) || defined (AT32F425K6T7) || \
defined (AT32F425K6U7_4)
#define AT32F425Kx
#endif
#if defined (AT32F425G8U7) || defined (AT32F425G6U7)
#define AT32F425Gx
#endif
#if defined (AT32F425F8P7) || defined (AT32F425F6P7)
#define AT32F425Fx
#endif
/**
* define with memory density
*/
#if defined (AT32F425R6T7) || defined (AT32F425R6T7_7) || defined (AT32F425C6T7) || \
defined (AT32F425C6U7) || defined (AT32F425K6T7) || defined (AT32F425K6U7_4) || \
defined (AT32F425F6P7) || defined (AT32F425G6U7)
#define AT32F425x6
#endif
#if defined (AT32F425R8T7) || defined (AT32F425R8T7_7) || defined (AT32F425C8T7) || \
defined (AT32F425C8U7) || defined (AT32F425K8T7) || defined (AT32F425K8U7_4) || \
defined (AT32F425F8P7) || defined (AT32F425G8U7)
#define AT32F425x8
#endif
#ifndef USE_STDPERIPH_DRIVER
/**
* @brief comment the line below if you will not use the peripherals drivers.
* in this case, these drivers will not be included and the application code will
* be based on direct access to peripherals registers
*/
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
#define USE_STDPERIPH_DRIVER
#endif
#endif
#endif
/**
* @brief at32f425 standard peripheral library version number
*/
#define __AT32F425_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F425_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */
#define __AT32F425_LIBRARY_VERSION_MINOR (0x01) /*!< [15:8] minor version */
#define __AT32F425_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F425_LIBRARY_VERSION ((__AT32F425_LIBRARY_VERSION_MAJOR << 24) | \
(__AT32F425_LIBRARY_VERSION_MIDDLE << 16) | \
(__AT32F425_LIBRARY_VERSION_MINOR << 8) | \
(__AT32F425_LIBRARY_VERSION_RC))
/**
* @}
*/
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief configuration of the cortex-m4 processor and core peripherals
*/
#define __CM4_REV 0x0001U /*!< core revision r0p1 */
#define __MPU_PRESENT 1 /*!< mpu present */
#define __NVIC_PRIO_BITS 4 /*!< at32 uses 4 bits for the priority levels */
#define __Vendor_SysTickConfig 0 /*!< set to 1 if different systick config is used */
#define __FPU_PRESENT 0U /*!< fpu present */
/**
* @brief at32f425 interrupt number definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum IRQn
{
/****** cortex-m4 processor exceptions numbers ***************************************************/
Reset_IRQn = -15, /*!< 1 reset vector, invoked on power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
HardFault_IRQn = -13, /*!< 3 hard fault, all classes of fault */
MemoryManagement_IRQn = -12, /*!< 4 cortex-m4 memory management interrupt */
BusFault_IRQn = -11, /*!< 5 cortex-m4 bus fault interrupt */
UsageFault_IRQn = -10, /*!< 6 cortex-m4 usage fault interrupt */
SVCall_IRQn = -5, /*!< 11 cortex-m4 sv call interrupt */
DebugMonitor_IRQn = -4, /*!< 12 cortex-m4 debug monitor interrupt */
PendSV_IRQn = -2, /*!< 14 cortex-m4 pend sv interrupt */
SysTick_IRQn = -1, /*!< 15 cortex-m4 system tick interrupt */
/****** at32 specific interrupt numbers *********************************************************/
WWDT_IRQn = 0, /*!< window watchdog timer interrupt */
PVM_IRQn = 1, /*!< pvm through exint line detection interrupt */
ERTC_IRQn = 2, /*!< ertc global interrupt */
FLASH_IRQn = 3, /*!< flash global interrupt */
CRM_IRQn = 4, /*!< crm global interrupt */
EXINT1_0_IRQn = 5, /*!< external line1~0 interrupt */
EXINT3_2_IRQn = 6, /*!< external line3~2 interrupt */
EXINT15_4_IRQn = 7, /*!< external line15~4 interrupt */
ACC_IRQn = 8, /*!< acc interrupt */
DMA1_Channel1_IRQn = 9, /*!< dma1 channel 1 global interrupt */
DMA1_Channel3_2_IRQn = 10, /*!< dma1 channel 3~2 global interrupt */
DMA1_Channel7_4_IRQn = 11, /*!< dma1 channel 7~4 global interrupt */
ADC1_IRQn = 12, /*!< adc1 global interrupt */
TMR1_BRK_OVF_TRG_HALL_IRQn = 13, /*!< tmr1 brake overflow trigger and hall interrupt */
TMR1_CH_IRQn = 14, /*!< tmr1 channel interrupt */
TMR2_GLOBAL_IRQn = 15, /*!< tmr2 channel interrupt */
TMR3_GLOBAL_IRQn = 16, /*!< tmr3 global interrupt */
TMR6_GLOBAL_IRQn = 17, /*!< tmr6 global interrupt */
TMR7_GLOBAL_IRQn = 18, /*!< tmr7 channel interrupt */
TMR14_GLOBAL_IRQn = 19, /*!< tmr14 global interrupt */
TMR15_GLOBAL_IRQn = 20, /*!< tmr15 global interrupt */
TMR16_GLOBAL_IRQn = 21, /*!< tmr16 global interrupt */
TMR17_GLOBAL_IRQn = 22, /*!< tmr17 global interrupt */
I2C1_EVT_IRQn = 23, /*!< i2c1 event interrupt */
I2C2_EVT_IRQn = 24, /*!< i2c2 event interrupt */
SPI1_IRQn = 25, /*!< spi1 global interrupt */
SPI2_IRQn = 26, /*!< spi2 global interrupt */
USART1_IRQn = 27, /*!< usart1 global interrupt */
USART2_IRQn = 28, /*!< usart2 global interrupt */
USART4_3_IRQn = 29, /*!< usart3 & usart4 global interrupt */
CAN1_IRQn = 30, /*!< can1 global interrupt */
OTGFS1_IRQn = 31, /*!< otgfs1 global interrupt */
I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
SPI3_IRQn = 33, /*!< spi3 global interrupt */
I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
TMR13_GLOBAL_IRQn = 35 /*!< tmr13 global interrupt */
} IRQn_Type;
/**
* @}
*/
#include "core_cm4.h"
#include "system_at32f425.h"
#include <stdint.h>
/** @addtogroup Exported_types
* @{
*/
typedef int32_t INT32;
typedef int16_t INT16;
typedef int8_t INT8;
typedef uint32_t UINT32;
typedef uint16_t UINT16;
typedef uint8_t UINT8;
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
typedef const int32_t sc32; /*!< read only */
typedef const int16_t sc16; /*!< read only */
typedef const int8_t sc8; /*!< read only */
typedef __IO int32_t vs32;
typedef __IO int16_t vs16;
typedef __IO int8_t vs8;
typedef __I int32_t vsc32; /*!< read only */
typedef __I int16_t vsc16; /*!< read only */
typedef __I int8_t vsc8; /*!< read only */
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef const uint32_t uc32; /*!< read only */
typedef const uint16_t uc16; /*!< read only */
typedef const uint8_t uc8; /*!< read only */
typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef __I uint32_t vuc32; /*!< read only */
typedef __I uint16_t vuc16; /*!< read only */
typedef __I uint8_t vuc8; /*!< read only */
/**
* @brief flag status
*/
typedef enum {RESET = 0, SET = !RESET} flag_status;
/**
* @brief confirm state
*/
typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
/**
* @brief error status
*/
typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
/**
* @}
*/
/** @addtogroup Exported_macro
* @{
*/
#define REG8(addr) *(volatile uint8_t *)(addr)
#define REG16(addr) *(volatile uint16_t *)(addr)
#define REG32(addr) *(volatile uint32_t *)(addr)
#define MAKE_VALUE(reg_offset, bit_num) (uint32_t)(((reg_offset) << 16) | (bit_num & 0x1F))
#define PERIPH_REG(periph_base, value) REG32((periph_base + (value >> 16)))
#define PERIPH_REG_BIT(value) (0x1U << (value & 0x1F))
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE ((uint32_t)0x08000000)
#define USD_BASE ((uint32_t)0x1FFFF800)
#define SRAM_BASE ((uint32_t)0x20000000)
#define PERIPH_BASE ((uint32_t)0x40000000)
#define DEBUG_BASE ((uint32_t)0xE0042000)
#define APB1PERIPH_BASE (PERIPH_BASE + 0x00000)
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define AHBPERIPH1_BASE (PERIPH_BASE + 0x20000)
#define AHBPERIPH2_BASE (PERIPH_BASE + 0x8000000)
/* apb1 bus base address */
#define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
#define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
#define TMR6_BASE (APB1PERIPH_BASE + 0x1000)
#define TMR7_BASE (APB1PERIPH_BASE + 0x1400)
#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00)
#define TMR14_BASE (APB1PERIPH_BASE + 0x2000)
#define ERTC_BASE (APB1PERIPH_BASE + 0x2800)
#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
#define WDT_BASE (APB1PERIPH_BASE + 0x3000)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define USART4_BASE (APB1PERIPH_BASE + 0x4C00)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
#define ACC_BASE (APB1PERIPH_BASE + 0x6C00)
#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
/* apb2 bus base address */
#define SCFG_BASE (APB2PERIPH_BASE + 0x0000)
#define EXINT_BASE (APB2PERIPH_BASE + 0x0400)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
#define TMR1_BASE (APB2PERIPH_BASE + 0x2C00)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
#define TMR15_BASE (APB2PERIPH_BASE + 0x4000)
#define TMR16_BASE (APB2PERIPH_BASE + 0x4400)
#define TMR17_BASE (APB2PERIPH_BASE + 0x4800)
/* ahb bus base address */
#define DMA1_BASE (AHBPERIPH1_BASE + 0x0000)
#define DMA1_CHANNEL1_BASE (AHBPERIPH1_BASE + 0x0008)
#define DMA1_CHANNEL2_BASE (AHBPERIPH1_BASE + 0x001C)
#define DMA1_CHANNEL3_BASE (AHBPERIPH1_BASE + 0x0030)
#define DMA1_CHANNEL4_BASE (AHBPERIPH1_BASE + 0x0044)
#define DMA1_CHANNEL5_BASE (AHBPERIPH1_BASE + 0x0058)
#define DMA1_CHANNEL6_BASE (AHBPERIPH1_BASE + 0x006C)
#define DMA1_CHANNEL7_BASE (AHBPERIPH1_BASE + 0x0080)
#define CRM_BASE (AHBPERIPH1_BASE + 0x1000)
#define FLASH_REG_BASE (AHBPERIPH1_BASE + 0x2000)
#define CRC_BASE (AHBPERIPH1_BASE + 0x3000)
#define GPIOA_BASE (AHBPERIPH2_BASE + 0x0000)
#define GPIOB_BASE (AHBPERIPH2_BASE + 0x0400)
#define GPIOC_BASE (AHBPERIPH2_BASE + 0x0800)
#define GPIOD_BASE (AHBPERIPH2_BASE + 0x0C00)
#define GPIOF_BASE (AHBPERIPH2_BASE + 0x1400)
#define OTGFS1_BASE (PERIPH_BASE + 0x10000000)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#include "at32f425_def.h"
#include "at32f425_conf.h"
#ifdef __cplusplus
}
#endif
#endif

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libraries/cmsis/cm4/device_support/at32f425_conf_template.h Normal file
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/**
**************************************************************************
* @file at32f425_conf.h
* @brief at32f425 config header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F425_CONF_H
#define __AT32F425_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief in the following line adjust the value of high speed external crystal (hext)
* used in your application
*
* tip: to avoid modifying this file each time you need to use different hext, you
* can define the hext value in your toolchain compiler preprocessor.
*
*/
#if !defined HEXT_VALUE
#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed external crystal in hz */
#endif
/**
* @brief in the following line adjust the high speed external crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed external clock in hz */
/* module define -------------------------------------------------------------*/
#define ACC_MODULE_ENABLED
#define CRM_MODULE_ENABLED
#define TMR_MODULE_ENABLED
#define ERTC_MODULE_ENABLED
#define GPIO_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define CAN_MODULE_ENABLED
#define USB_MODULE_ENABLED
#define USART_MODULE_ENABLED
#define PWC_MODULE_ENABLED
#define ADC_MODULE_ENABLED
#define SPI_MODULE_ENABLED
#define DMA_MODULE_ENABLED
#define DEBUG_MODULE_ENABLED
#define FLASH_MODULE_ENABLED
#define CRC_MODULE_ENABLED
#define WWDT_MODULE_ENABLED
#define WDT_MODULE_ENABLED
#define EXINT_MODULE_ENABLED
#define MISC_MODULE_ENABLED
#define SCFG_MODULE_ENABLED
/* includes ------------------------------------------------------------------*/
#ifdef ACC_MODULE_ENABLED
#include "at32f425_acc.h"
#endif
#ifdef CRM_MODULE_ENABLED
#include "at32f425_crm.h"
#endif
#ifdef CAN_MODULE_ENABLED
#include "at32f425_can.h"
#endif
#ifdef USB_MODULE_ENABLED
#include "at32f425_usb.h"
#endif
#ifdef TMR_MODULE_ENABLED
#include "at32f425_tmr.h"
#endif
#ifdef ERTC_MODULE_ENABLED
#include "at32f425_ertc.h"
#endif
#ifdef GPIO_MODULE_ENABLED
#include "at32f425_gpio.h"
#endif
#ifdef I2C_MODULE_ENABLED
#include "at32f425_i2c.h"
#endif
#ifdef USART_MODULE_ENABLED
#include "at32f425_usart.h"
#endif
#ifdef PWC_MODULE_ENABLED
#include "at32f425_pwc.h"
#endif
#ifdef ADC_MODULE_ENABLED
#include "at32f425_adc.h"
#endif
#ifdef SPI_MODULE_ENABLED
#include "at32f425_spi.h"
#endif
#ifdef DMA_MODULE_ENABLED
#include "at32f425_dma.h"
#endif
#ifdef DEBUG_MODULE_ENABLED
#include "at32f425_debug.h"
#endif
#ifdef FLASH_MODULE_ENABLED
#include "at32f425_flash.h"
#endif
#ifdef CRC_MODULE_ENABLED
#include "at32f425_crc.h"
#endif
#ifdef WWDT_MODULE_ENABLED
#include "at32f425_wwdt.h"
#endif
#ifdef WDT_MODULE_ENABLED
#include "at32f425_wdt.h"
#endif
#ifdef EXINT_MODULE_ENABLED
#include "at32f425_exint.h"
#endif
#ifdef MISC_MODULE_ENABLED
#include "at32f425_misc.h"
#endif
#ifdef SCFG_MODULE_ENABLED
#include "at32f425_scfg.h"
#endif
#ifdef __cplusplus
}
#endif
#endif

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libraries/cmsis/cm4/device_support/startup/gcc/linker/AT32F425x4_FLASH.ld Normal file
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/*
*****************************************************************************
**
** File : AT32F425x4_FLASH.ld
**
** Abstract : Linker script for AT32F425x4 Device with
** 16KByte FLASH, 8KByte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
**
** Environment : Arm gcc toolchain
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20002000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 16K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

153
libraries/cmsis/cm4/device_support/startup/gcc/linker/AT32F425x6_FLASH.ld Normal file
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/*
*****************************************************************************
**
** File : AT32F425x6_FLASH.ld
**
** Abstract : Linker script for AT32F425x6 Device with
** 32KByte FLASH, 20KByte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
**
** Environment : Arm gcc toolchain
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20005000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

153
libraries/cmsis/cm4/device_support/startup/gcc/linker/AT32F425x8_FLASH.ld Normal file
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/*
*****************************************************************************
**
** File : AT32F425x8_FLASH.ld
**
** Abstract : Linker script for AT32F425x8 Device with
** 64KByte FLASH, 16KByte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
**
** Environment : Arm gcc toolchain
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20005000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

309
libraries/cmsis/cm4/device_support/startup/gcc/startup_at32f425.s Normal file
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/**
******************************************************************************
* @file startup_at32f425.s
* @brief at32f425xx devices vector table for gcc toolchain.
* this module performs:
* - set the initial sp
* - set the initial pc == reset_handler,
* - set the vector table entries with the exceptions isr address
* - configure the clock system and the external sram to
* be used as data memory (optional, to be enabled by user)
* - branches to main in the c library (which eventually
* calls main()).
* after reset the cortex-m4 processor is in thread mode,
* priority is privileged, and the stack is set to main.
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDT_IRQHandler /* Window Watchdog Timer */
.word PVM_IRQHandler /* PVM through EXINT Line detect */
.word ERTC_IRQHandler /* ERTC */
.word FLASH_IRQHandler /* Flash */
.word CRM_IRQHandler /* CRM */
.word EXINT1_0_IRQHandler /* EXINT Line 1 & 0 */
.word EXINT3_2_IRQHandler /* EXINT Line 3 & 2 */
.word EXINT15_4_IRQHandler /* EXINT Line 15 ~ 4 */
.word ACC_IRQHandler /* ACC */
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA1_Channel3_2_IRQHandler /* DMA1 Channel 3 & 2 */
.word DMA1_Channel7_4_IRQHandler /* DMA1 Channel 7 & 4 */
.word ADC1_IRQHandler /* ADC1 */
.word TMR1_BRK_OVF_TRG_HALL_IRQHandler /* TMR1 brake overflow trigger and hall */
.word TMR1_CH_IRQHandler /* TMR1 channel */
.word TMR2_GLOBAL_IRQHandler /* TMR2 */
.word TMR3_GLOBAL_IRQHandler /* TMR3 */
.word TMR6_GLOBAL_IRQHandler /* TMR6 */
.word TMR7_GLOBAL_IRQHandler /* TMR7 */
.word TMR14_GLOBAL_IRQHandler /* TMR14 */
.word TMR15_GLOBAL_IRQHandler /* TMR15 */
.word TMR16_GLOBAL_IRQHandler /* TMR16 */
.word TMR17_GLOBAL_IRQHandler /* TMR17 */
.word I2C1_EVT_IRQHandler /* I2C1 Event */
.word I2C2_EVT_IRQHandler /* I2C2 Event */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART4_3_IRQHandler /* USART3 & USART4 */
.word CAN1_IRQHandler /* CAN1 */
.word OTGFS1_IRQHandler /* OTGFS1 */
.word I2C1_ERR_IRQHandler /* I2C1 Error */
.word SPI3_IRQHandler /* SPI3 */
.word I2C2_ERR_IRQHandler /* I2C2 Error */
.word TMR13_GLOBAL_IRQHandler /* TMR13 */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDT_IRQHandler
.thumb_set WWDT_IRQHandler,Default_Handler
.weak PVM_IRQHandler
.thumb_set PVM_IRQHandler,Default_Handler
.weak ERTC_IRQHandler
.thumb_set ERTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak CRM_IRQHandler
.thumb_set CRM_IRQHandler,Default_Handler
.weak EXINT1_0_IRQHandler
.thumb_set EXINT1_0_IRQHandler,Default_Handler
.weak EXINT3_2_IRQHandler
.thumb_set EXINT3_2_IRQHandler,Default_Handler
.weak EXINT15_4_IRQHandler
.thumb_set EXINT15_4_IRQHandler,Default_Handler
.weak ACC_IRQHandler
.thumb_set ACC_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel3_2_IRQHandler
.thumb_set DMA1_Channel3_2_IRQHandler,Default_Handler
.weak DMA1_Channel7_4_IRQHandler
.thumb_set DMA1_Channel7_4_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak TMR1_BRK_OVF_TRG_HALL_IRQHandler
.thumb_set TMR1_BRK_OVF_TRG_HALL_IRQHandler,Default_Handler
.weak TMR1_CH_IRQHandler
.thumb_set TMR1_CH_IRQHandler,Default_Handler
.weak TMR2_GLOBAL_IRQHandler
.thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
.weak TMR3_GLOBAL_IRQHandler
.thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
.weak TMR6_GLOBAL_IRQHandler
.thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
.weak TMR7_GLOBAL_IRQHandler
.thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
.weak TMR14_GLOBAL_IRQHandler
.thumb_set TMR14_GLOBAL_IRQHandler,Default_Handler
.weak TMR15_GLOBAL_IRQHandler
.thumb_set TMR15_GLOBAL_IRQHandler,Default_Handler
.weak TMR16_GLOBAL_IRQHandler
.thumb_set TMR16_GLOBAL_IRQHandler,Default_Handler
.weak TMR17_GLOBAL_IRQHandler
.thumb_set TMR17_GLOBAL_IRQHandler,Default_Handler
.weak I2C1_EVT_IRQHandler
.thumb_set I2C1_EVT_IRQHandler,Default_Handler
.weak I2C2_EVT_IRQHandler
.thumb_set I2C2_EVT_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART4_3_IRQHandler
.thumb_set USART4_3_IRQHandler,Default_Handler
.weak CAN1_IRQHandler
.thumb_set CAN1_IRQHandler,Default_Handler
.weak OTGFS1_IRQHandler
.thumb_set OTGFS1_IRQHandler,Default_Handler
.weak I2C1_ERR_IRQHandler
.thumb_set I2C1_ERR_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak I2C2_ERR_IRQHandler
.thumb_set I2C2_ERR_IRQHandler,Default_Handler
.weak TMR13_GLOBAL_IRQHandler
.thumb_set TMR13_GLOBAL_IRQHandler,Default_Handler

30
libraries/cmsis/cm4/device_support/startup/iar/linker/AT32F425x4.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x08003FFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x1000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

30
libraries/cmsis/cm4/device_support/startup/iar/linker/AT32F425x6.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x08007FFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x1000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

30
libraries/cmsis/cm4/device_support/startup/iar/linker/AT32F425x8.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x1000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

320
libraries/cmsis/cm4/device_support/startup/iar/startup_at32f425.s Normal file
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;**************************************************************************
;* @file startup_at32f425.s
;* @brief at32f425 startup file for IAR Systems
;**************************************************************************
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog Timer
DCD PVM_IRQHandler ; PVM through EXINT Line detect
DCD ERTC_IRQHandler ; ERTC
DCD FLASH_IRQHandler ; Flash
DCD CRM_IRQHandler ; CRM
DCD EXINT1_0_IRQHandler ; EXINT Line 1 & 0
DCD EXINT3_2_IRQHandler ; EXINT Line 3 & 2
DCD EXINT15_4_IRQHandler ; EXINT Line 15 ~ 4
DCD ACC_IRQHandler ; ACC
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel3_2_IRQHandler ; DMA1 Channel 3 & 2
DCD DMA1_Channel7_4_IRQHandler ; DMA1 Channel 7 & 4
DCD ADC1_IRQHandler ; ADC1
DCD TMR1_BRK_OVF_TRG_HALL_IRQHandler ; TMR1 brake overflow trigger and hall
DCD TMR1_CH_IRQHandler ; TMR1 channel
DCD TMR2_GLOBAL_IRQHandler ; TMR2
DCD TMR3_GLOBAL_IRQHandler ; TMR3
DCD TMR6_GLOBAL_IRQHandler ; TMR6
DCD TMR7_GLOBAL_IRQHandler ; TMR7
DCD TMR14_GLOBAL_IRQHandler ; TMR14
DCD TMR15_GLOBAL_IRQHandler ; TMR15
DCD TMR16_GLOBAL_IRQHandler ; TMR16
DCD TMR17_GLOBAL_IRQHandler ; TMR17
DCD I2C1_EVT_IRQHandler ; I2C1 Event
DCD I2C2_EVT_IRQHandler ; I2C2 Event
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART4_3_IRQHandler ; USART3 & USART4
DCD CAN1_IRQHandler ; CAN1
DCD OTGFS1_IRQHandler ; OTGFS1
DCD I2C1_ERR_IRQHandler ; I2C1 Error
DCD SPI3_IRQHandler ; SPI3
DCD I2C2_ERR_IRQHandler ; I2C2 Error
DCD TMR13_GLOBAL_IRQHandler ; TMR13
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDT_IRQHandler
B WWDT_IRQHandler
PUBWEAK PVM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVM_IRQHandler
B PVM_IRQHandler
PUBWEAK ERTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ERTC_IRQHandler
B ERTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK CRM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CRM_IRQHandler
B CRM_IRQHandler
PUBWEAK EXINT1_0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXINT1_0_IRQHandler
B EXINT1_0_IRQHandler
PUBWEAK EXINT3_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXINT3_2_IRQHandler
B EXINT3_2_IRQHandler
PUBWEAK EXINT15_4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXINT15_4_IRQHandler
B EXINT15_4_IRQHandler
PUBWEAK ACC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ACC_IRQHandler
B ACC_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel3_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_2_IRQHandler
B DMA1_Channel3_2_IRQHandler
PUBWEAK DMA1_Channel7_4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_4_IRQHandler
B DMA1_Channel7_4_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK TMR1_BRK_OVF_TRG_HALL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_BRK_OVF_TRG_HALL_IRQHandler
B TMR1_BRK_OVF_TRG_HALL_IRQHandler
PUBWEAK TMR1_CH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_CH_IRQHandler
B TMR1_CH_IRQHandler
PUBWEAK TMR2_GLOBAL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR2_GLOBAL_IRQHandler
B TMR2_GLOBAL_IRQHandler
PUBWEAK TMR3_GLOBAL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR3_GLOBAL_IRQHandler
B TMR3_GLOBAL_IRQHandler
PUBWEAK TMR6_GLOBAL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR6_GLOBAL_IRQHandler
B TMR6_GLOBAL_IRQHandler
PUBWEAK TMR7_GLOBAL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR7_GLOBAL_IRQHandler
B TMR7_GLOBAL_IRQHandler
PUBWEAK TMR14_GLOBAL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR14_GLOBAL_IRQHandler
B TMR14_GLOBAL_IRQHandler
PUBWEAK TMR15_GLOBAL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR15_GLOBAL_IRQHandler
B TMR15_GLOBAL_IRQHandler
PUBWEAK TMR16_GLOBAL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR16_GLOBAL_IRQHandler
B TMR16_GLOBAL_IRQHandler
PUBWEAK TMR17_GLOBAL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR17_GLOBAL_IRQHandler
B TMR17_GLOBAL_IRQHandler
PUBWEAK I2C1_EVT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EVT_IRQHandler
B I2C1_EVT_IRQHandler
PUBWEAK I2C2_EVT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EVT_IRQHandler
B I2C2_EVT_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART4_3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART4_3_IRQHandler
B USART4_3_IRQHandler
PUBWEAK CAN1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_IRQHandler
B CAN1_IRQHandler
PUBWEAK OTGFS1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTGFS1_IRQHandler
B OTGFS1_IRQHandler
PUBWEAK I2C1_ERR_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ERR_IRQHandler
B I2C1_ERR_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK I2C2_ERR_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ERR_IRQHandler
B I2C2_ERR_IRQHandler
PUBWEAK TMR13_GLOBAL_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TMR13_GLOBAL_IRQHandler
B TMR13_GLOBAL_IRQHandler
END

261
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;**************************************************************************
;* @file startup_at32f425.s
;* @brief startup_at32f425 startup file for keil
;* <<< Use Configuration Wizard in Context Menu >>>
;**************************************************************************
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog Timer
DCD PVM_IRQHandler ; PVM through EXINT Line detect
DCD ERTC_IRQHandler ; ERTC
DCD FLASH_IRQHandler ; Flash
DCD CRM_IRQHandler ; CRM
DCD EXINT1_0_IRQHandler ; EXINT Line 1 & 0
DCD EXINT3_2_IRQHandler ; EXINT Line 3 & 2
DCD EXINT15_4_IRQHandler ; EXINT Line 15 ~ 4
DCD ACC_IRQHandler ; ACC
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel3_2_IRQHandler ; DMA1 Channel 3 & 2
DCD DMA1_Channel7_4_IRQHandler ; DMA1 Channel 7 & 4
DCD ADC1_IRQHandler ; ADC1
DCD TMR1_BRK_OVF_TRG_HALL_IRQHandler ; TMR1 brake overflow trigger and hall
DCD TMR1_CH_IRQHandler ; TMR1 channel
DCD TMR2_GLOBAL_IRQHandler ; TMR2
DCD TMR3_GLOBAL_IRQHandler ; TMR3
DCD TMR6_GLOBAL_IRQHandler ; TMR6
DCD TMR7_GLOBAL_IRQHandler ; TMR7
DCD TMR14_GLOBAL_IRQHandler ; TMR14
DCD TMR15_GLOBAL_IRQHandler ; TMR15
DCD TMR16_GLOBAL_IRQHandler ; TMR16
DCD TMR17_GLOBAL_IRQHandler ; TMR17
DCD I2C1_EVT_IRQHandler ; I2C1 Event
DCD I2C2_EVT_IRQHandler ; I2C2 Event
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART4_3_IRQHandler ; USART3 & USART4
DCD CAN1_IRQHandler ; CAN1
DCD OTGFS1_IRQHandler ; OTGFS1
DCD I2C1_ERR_IRQHandler ; I2C1 Error
DCD SPI3_IRQHandler ; SPI3
DCD I2C2_ERR_IRQHandler ; I2C2 Error
DCD TMR13_GLOBAL_IRQHandler ; TMR13
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT PVM_IRQHandler [WEAK]
EXPORT ERTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT CRM_IRQHandler [WEAK]
EXPORT EXINT1_0_IRQHandler [WEAK]
EXPORT EXINT3_2_IRQHandler [WEAK]
EXPORT EXINT15_4_IRQHandler [WEAK]
EXPORT ACC_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel3_2_IRQHandler [WEAK]
EXPORT DMA1_Channel7_4_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT TMR1_BRK_OVF_TRG_HALL_IRQHandler [WEAK]
EXPORT TMR1_CH_IRQHandler [WEAK]
EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
EXPORT TMR6_GLOBAL_IRQHandler [WEAK]
EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
EXPORT TMR14_GLOBAL_IRQHandler [WEAK]
EXPORT TMR15_GLOBAL_IRQHandler [WEAK]
EXPORT TMR16_GLOBAL_IRQHandler [WEAK]
EXPORT TMR17_GLOBAL_IRQHandler [WEAK]
EXPORT I2C1_EVT_IRQHandler [WEAK]
EXPORT I2C2_EVT_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART4_3_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT OTGFS1_IRQHandler [WEAK]
EXPORT I2C1_ERR_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT I2C2_ERR_IRQHandler [WEAK]
EXPORT TMR13_GLOBAL_IRQHandler [WEAK]
WWDT_IRQHandler
PVM_IRQHandler
ERTC_IRQHandler
FLASH_IRQHandler
CRM_IRQHandler
EXINT1_0_IRQHandler
EXINT3_2_IRQHandler
EXINT15_4_IRQHandler
ACC_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel3_2_IRQHandler
DMA1_Channel7_4_IRQHandler
ADC1_IRQHandler
TMR1_BRK_OVF_TRG_HALL_IRQHandler
TMR1_CH_IRQHandler
TMR2_GLOBAL_IRQHandler
TMR3_GLOBAL_IRQHandler
TMR6_GLOBAL_IRQHandler
TMR7_GLOBAL_IRQHandler
TMR14_GLOBAL_IRQHandler
TMR15_GLOBAL_IRQHandler
TMR16_GLOBAL_IRQHandler
TMR17_GLOBAL_IRQHandler
I2C1_EVT_IRQHandler
I2C2_EVT_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART4_3_IRQHandler
CAN1_IRQHandler
OTGFS1_IRQHandler
I2C1_ERR_IRQHandler
SPI3_IRQHandler
I2C2_ERR_IRQHandler
TMR13_GLOBAL_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

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libraries/cmsis/cm4/device_support/system_at32f425.c Normal file
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/**
**************************************************************************
* @file system_at32f425.c
* @brief contains all the functions for cmsis cortex-m4 system source file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup AT32F425_system
* @{
*/
#include "at32f425.h"
/** @addtogroup AT32F425_system_private_defines
* @{
*/
#define VECT_TAB_OFFSET 0x0 /*!< vector table base offset field. this value must be a multiple of 0x200. */
/**
* @}
*/
/** @addtogroup AT32F425_system_private_variables
* @{
*/
unsigned int system_core_clock = HICK_VALUE; /*!< system clock frequency (core clock) */
/**
* @}
*/
/** @addtogroup AT32F425_system_private_functions
* @{
*/
/**
* @brief setup the microcontroller system
* initialize the flash interface.
* @note this function should be used only after reset.
* @param none
* @retval none
*/
void SystemInit (void)
{
/* reset the crm clock configuration to the default reset state(for debug purpose) */
/* set hicken bit */
CRM->ctrl_bit.hicken = TRUE;
/* wait hick stable */
while(CRM->ctrl_bit.hickstbl != SET);
/* hick used as system clock */
CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
/* wait sclk switch status */
while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
/* reset hexten, hextbyps, cfden and pllen bits */
CRM->ctrl &= ~(0x010D0000U);
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */
CRM->cfg = 0;
/* reset pllfr, pllms, pllns and pllfref bits */
CRM->pll = (0x00001F10U);
/* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
CRM->misc1 = 0x00100000;
/* disable all interrupts enable and clear pending bits */
CRM->clkint = 0x009F0000;
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* vector table relocation in internal sram. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* vector table relocation in internal flash. */
#endif
}
/**
* @brief update system_core_clock variable according to clock register values.
* the system_core_clock variable contains the core clock (hclk), it can
* be used by the user application to setup the systick timer or configure
* other parameters.
* @param none
* @retval none
*/
void system_core_clock_update(void)
{
uint32_t pll_mult = 0, pll_mult_h = 0, pll_clock_source = 0, temp = 0, div_value = 0;
uint32_t pllrcsfreq = 0, pll_ms = 0, pll_ns = 0, pll_fr = 0;
crm_sclk_type sclk_source;
static const uint8_t sys_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/* get sclk source */
sclk_source = crm_sysclk_switch_status_get();
switch(sclk_source)
{
case CRM_SCLK_HICK:
if(((CRM->misc2_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
system_core_clock = HICK_VALUE * 6;
else
system_core_clock = HICK_VALUE;
break;
case CRM_SCLK_HEXT:
system_core_clock = HEXT_VALUE;
break;
case CRM_SCLK_PLL:
pll_clock_source = CRM->cfg_bit.pllrcs;
if(CRM->pll_bit.pllcfgen == FALSE)
{
/* get multiplication factor */
pll_mult = CRM->cfg_bit.pllmult_l;
pll_mult_h = CRM->cfg_bit.pllmult_h;
/* process high bits */
if((pll_mult_h != 0U) || (pll_mult == 15U)){
pll_mult += ((16U * pll_mult_h) + 1U);
}
else
{
pll_mult += 2U;
}
if (pll_clock_source == 0x00)
{
/* hick divided by 2 selected as pll clock entry */
system_core_clock = (HICK_VALUE >> 1) * pll_mult;
}
else
{
/* hext selected as pll clock entry */
if (CRM->cfg_bit.pllhextdiv != RESET)
{
/* hext clock divided by 2 */
system_core_clock = (HEXT_VALUE / 2) * pll_mult;
}
else
{
system_core_clock = HEXT_VALUE * pll_mult;
}
}
}
else
{
pll_ms = CRM->pll_bit.pllms;
pll_ns = CRM->pll_bit.pllns;
pll_fr = CRM->pll_bit.pllfr;
if (pll_clock_source == 0x00)
{
/* hick divided by 2 selected as pll clock entry */
pllrcsfreq = (HICK_VALUE >> 1);
}
else
{
/* hext selected as pll clock entry */
if (CRM->cfg_bit.pllhextdiv != RESET)
{
/* hext clock divided by 2 */
pllrcsfreq = (HEXT_VALUE / 2);
}
else
{
pllrcsfreq = HEXT_VALUE;
}
}
system_core_clock = (uint32_t)(((uint64_t)pllrcsfreq * pll_ns) / (pll_ms * (0x1 << pll_fr)));
}
break;
default:
system_core_clock = HICK_VALUE;
break;
}
/* compute sclk, ahbclk frequency */
/* get ahb division */
temp = CRM->cfg_bit.ahbdiv;
div_value = sys_ahb_div_table[temp];
/* ahbclk frequency */
system_core_clock = system_core_clock >> div_value;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

85
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/**
**************************************************************************
* @file system_at32f425.h
* @brief cmsis cortex-m4 system header file.
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#ifndef __SYSTEM_AT32F425_H
#define __SYSTEM_AT32F425_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup AT32F425_system
* @{
*/
/** @defgroup AT32F425_system_clock_stable_definition
* @{
*/
#define HEXT_STABLE_DELAY (5000u)
#define PLL_STABLE_DELAY (500u)
#define SystemCoreClock system_core_clock
/**
* @}
*/
/** @defgroup AT32F425_system_exported_variables
* @{
*/
extern unsigned int system_core_clock; /*!< system clock frequency (core clock) */
/**
* @}
*/
/** @defgroup AT32F425_system_exported_functions
* @{
*/
extern void SystemInit(void);
extern void system_core_clock_update(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif