221 lines
6.2 KiB
C
221 lines
6.2 KiB
C
/**
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**************************************************************************
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* @file system_at32f415.c
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* @brief contains all the functions for cmsis cortex-m4 system source file
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup AT32F415_system
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* @{
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*/
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#include "at32f415.h"
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/** @addtogroup AT32F415_system_private_defines
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* @{
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*/
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#define VECT_TAB_OFFSET 0x0 /*!< vector table base offset field. this value must be a multiple of 0x200. */
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/**
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* @}
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*/
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/** @addtogroup AT32F415_system_private_variables
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* @{
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*/
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unsigned int system_core_clock = HICK_VALUE; /*!< system clock frequency (core clock) */
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/**
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* @}
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*/
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/** @addtogroup AT32F415_system_private_functions
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* @{
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*/
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/**
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* @brief setup the microcontroller system
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* initialize the flash interface.
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* @note this function should be used only after reset.
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* @param none
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* @retval none
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*/
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void SystemInit (void)
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{
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/* enable low power mode */
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CRM->apb1en_bit.pwcen = 1;
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*(volatile uint8_t *)(0x40007050) |= (uint8_t)(0x1 << 2);
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CRM->apb1en_bit.pwcen = 0;
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/* reset the crm clock configuration to the default reset state(for debug purpose) */
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/* set hicken bit */
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CRM->ctrl_bit.hicken = TRUE;
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/* wait hick stable */
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while(CRM->ctrl_bit.hickstbl != SET);
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/* hick used as system clock */
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CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
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/* wait sclk switch status */
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while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
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/* reset hexten, hextbyps, cfden and pllen bits */
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CRM->ctrl &= ~(0x010D0000U);
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/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
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clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */
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CRM->cfg = 0;
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/* reset pllfr, pllms, pllns and pllfref bits */
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CRM->pll = (0x00001F10U);
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/* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
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CRM->misc1 = 0x00100000;
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/* disable all interrupts enable and clear pending bits */
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CRM->clkint = 0x009F0000;
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* vector table relocation in internal sram. */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* vector table relocation in internal flash. */
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#endif
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}
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/**
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* @brief update system_core_clock variable according to clock register values.
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* the system_core_clock variable contains the core clock (hclk), it can
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* be used by the user application to setup the systick timer or configure
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* other parameters.
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* @param none
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* @retval none
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*/
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void system_core_clock_update(void)
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{
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uint32_t pll_mult = 0, pll_mult_h = 0, pll_clock_source = 0, temp = 0, div_value = 0;
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uint32_t pllrcsfreq = 0, pll_ms = 0, pll_ns = 0, pll_fr = 0;
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crm_sclk_type sclk_source;
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static const uint8_t sys_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/* get sclk source */
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sclk_source = crm_sysclk_switch_status_get();
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switch(sclk_source)
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{
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case CRM_SCLK_HICK:
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if(((CRM->misc2_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
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system_core_clock = HICK_VALUE * 6;
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else
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system_core_clock = HICK_VALUE;
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break;
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case CRM_SCLK_HEXT:
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system_core_clock = HEXT_VALUE;
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break;
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case CRM_SCLK_PLL:
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pll_clock_source = CRM->cfg_bit.pllrcs;
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if(CRM->pll_bit.pllcfgen == FALSE)
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{
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/* get multiplication factor */
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pll_mult = CRM->cfg_bit.pllmult_l;
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pll_mult_h = CRM->cfg_bit.pllmult_h;
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/* process high bits */
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if((pll_mult_h != 0U) || (pll_mult == 15U)){
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pll_mult += ((16U * pll_mult_h) + 1U);
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}
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else
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{
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pll_mult += 2U;
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}
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if (pll_clock_source == 0x00)
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{
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/* hick divided by 2 selected as pll clock entry */
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system_core_clock = (HICK_VALUE >> 1) * pll_mult;
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}
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else
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{
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/* hext selected as pll clock entry */
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if (CRM->cfg_bit.pllhextdiv != RESET)
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{
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/* hext clock divided by 2 */
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system_core_clock = (HEXT_VALUE / 2) * pll_mult;
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}
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else
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{
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system_core_clock = HEXT_VALUE * pll_mult;
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}
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}
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}
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else
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{
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pll_ms = CRM->pll_bit.pllms;
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pll_ns = CRM->pll_bit.pllns;
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pll_fr = CRM->pll_bit.pllfr;
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if (pll_clock_source == 0x00)
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{
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/* hick divided by 2 selected as pll clock entry */
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pllrcsfreq = (HICK_VALUE >> 1);
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}
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else
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{
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/* hext selected as pll clock entry */
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if (CRM->cfg_bit.pllhextdiv != RESET)
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{
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/* hext clock divided by 2 */
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pllrcsfreq = (HEXT_VALUE / 2);
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}
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else
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{
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pllrcsfreq = HEXT_VALUE;
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}
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}
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system_core_clock = (uint32_t)(((uint64_t)pllrcsfreq * pll_ns) / (pll_ms * (0x1 << pll_fr)));
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}
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break;
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default:
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system_core_clock = HICK_VALUE;
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break;
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}
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/* compute sclk, ahbclk frequency */
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/* get ahb division */
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temp = CRM->cfg_bit.ahbdiv;
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div_value = sys_ahb_div_table[temp];
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/* ahbclk frequency */
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system_core_clock = system_core_clock >> div_value;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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