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libraries/drivers/inc/at32f415_adc.h Normal file
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/**
**************************************************************************
* @file at32f415_adc.h
* @brief at32f415 adc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_ADC_H
#define __AT32F415_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/** @defgroup ADC_interrupts_definition
* @brief adc interrupt
* @{
*/
#define ADC_CCE_INT ((uint32_t)0x00000020) /*!< channels conversion end interrupt */
#define ADC_VMOR_INT ((uint32_t)0x00000040) /*!< voltage monitoring out of range interrupt */
#define ADC_PCCE_INT ((uint32_t)0x00000080) /*!< preempt channels conversion end interrupt */
/**
* @}
*/
/** @defgroup ADC_flags_definition
* @brief adc flag
* @{
*/
#define ADC_VMOR_FLAG ((uint8_t)0x01) /*!< voltage monitoring out of range flag */
#define ADC_CCE_FLAG ((uint8_t)0x02) /*!< channels conversion end flag */
#define ADC_PCCE_FLAG ((uint8_t)0x04) /*!< preempt channels conversion end flag */
#define ADC_PCCS_FLAG ((uint8_t)0x08) /*!< preempt channel conversion start flag */
#define ADC_OCCS_FLAG ((uint8_t)0x10) /*!< ordinary channel conversion start flag */
/**
* @}
*/
/** @defgroup ADC_exported_types
* @{
*/
/**
* @brief adc data align type
*/
typedef enum
{
ADC_RIGHT_ALIGNMENT = 0x00, /*!< data right alignment */
ADC_LEFT_ALIGNMENT = 0x01 /*!< data left alignment */
} adc_data_align_type;
/**
* @brief adc channel select type
*/
typedef enum
{
ADC_CHANNEL_0 = 0x00, /*!< adc channel 0 */
ADC_CHANNEL_1 = 0x01, /*!< adc channel 1 */
ADC_CHANNEL_2 = 0x02, /*!< adc channel 2 */
ADC_CHANNEL_3 = 0x03, /*!< adc channel 3 */
ADC_CHANNEL_4 = 0x04, /*!< adc channel 4 */
ADC_CHANNEL_5 = 0x05, /*!< adc channel 5 */
ADC_CHANNEL_6 = 0x06, /*!< adc channel 6 */
ADC_CHANNEL_7 = 0x07, /*!< adc channel 7 */
ADC_CHANNEL_8 = 0x08, /*!< adc channel 8 */
ADC_CHANNEL_9 = 0x09, /*!< adc channel 9 */
ADC_CHANNEL_10 = 0x0A, /*!< adc channel 10 */
ADC_CHANNEL_11 = 0x0B, /*!< adc channel 11 */
ADC_CHANNEL_12 = 0x0C, /*!< adc channel 12 */
ADC_CHANNEL_13 = 0x0D, /*!< adc channel 13 */
ADC_CHANNEL_14 = 0x0E, /*!< adc channel 14 */
ADC_CHANNEL_15 = 0x0F, /*!< adc channel 15 */
ADC_CHANNEL_16 = 0x10, /*!< adc channel 16 */
ADC_CHANNEL_17 = 0x11 /*!< adc channel 17 */
} adc_channel_select_type;
/**
* @brief adc sampletime select type
*/
typedef enum
{
ADC_SAMPLETIME_1_5 = 0x00, /*!< adc sample time 1.5 cycle */
ADC_SAMPLETIME_7_5 = 0x01, /*!< adc sample time 7.5 cycle */
ADC_SAMPLETIME_13_5 = 0x02, /*!< adc sample time 13.5 cycle */
ADC_SAMPLETIME_28_5 = 0x03, /*!< adc sample time 28.5 cycle */
ADC_SAMPLETIME_41_5 = 0x04, /*!< adc sample time 41.5 cycle */
ADC_SAMPLETIME_55_5 = 0x05, /*!< adc sample time 55.5 cycle */
ADC_SAMPLETIME_71_5 = 0x06, /*!< adc sample time 71.5 cycle */
ADC_SAMPLETIME_239_5 = 0x07 /*!< adc sample time 239.5 cycle */
} adc_sampletime_select_type;
/**
* @brief adc ordinary group trigger event select type
*/
typedef enum
{
/*adc1 ordinary trigger event*/
ADC12_ORDINARY_TRIG_TMR1CH1 = 0x00, /*!< timer1 ch1 event as trigger source of adc1 ordinary sequence */
ADC12_ORDINARY_TRIG_TMR1CH2 = 0x01, /*!< timer1 ch2 event as trigger source of adc1 ordinary sequence */
ADC12_ORDINARY_TRIG_TMR1CH3 = 0x02, /*!< timer1 ch3 event as trigger source of adc1 ordinary sequence */
ADC12_ORDINARY_TRIG_TMR2CH2 = 0x03, /*!< timer2 ch2 event as trigger source of adc1 ordinary sequence */
ADC12_ORDINARY_TRIG_TMR3TRGOUT = 0x04, /*!< timer3 trgout event as trigger source of adc1 ordinary sequence */
ADC12_ORDINARY_TRIG_TMR4CH4 = 0x05, /*!< timer4 ch4 event as trigger source of adc1 ordinary sequence */
ADC12_ORDINARY_TRIG_EXINT11_TMR1TRGOUT = 0x06, /*!< exint line11/timer1 trgout event as trigger source of adc1 ordinary sequence */
ADC12_ORDINARY_TRIG_SOFTWARE = 0x07, /*!< software(OCSWTRG) control bit as trigger source of adc1 ordinary sequence */
ADC12_ORDINARY_TRIG_TMR1TRGOUT = 0x0D, /*!< timer1 trgout event as trigger source of adc1 ordinary sequence */
} adc_ordinary_trig_select_type;
/**
* @brief adc preempt group trigger event select type
*/
typedef enum
{
/*adc1 preempt trigger event*/
ADC12_PREEMPT_TRIG_TMR1TRGOUT = 0x00, /*!< timer1 trgout event as trigger source of adc1 preempt sequence */
ADC12_PREEMPT_TRIG_TMR1CH4 = 0x01, /*!< timer1 ch4 event as trigger source of adc1 preempt sequence */
ADC12_PREEMPT_TRIG_TMR2TRGOUT = 0x02, /*!< timer2 trgout event as trigger source of adc1 preempt sequence */
ADC12_PREEMPT_TRIG_TMR2CH1 = 0x03, /*!< timer2 ch1 event as trigger source of adc1 preempt sequence */
ADC12_PREEMPT_TRIG_TMR3CH4 = 0x04, /*!< timer3 ch4 event as trigger source of adc1 preempt sequence */
ADC12_PREEMPT_TRIG_TMR4TRGOUT = 0x05, /*!< timer4 trgout event as trigger source of adc1 preempt sequence */
ADC12_PREEMPT_TRIG_EXINT15_TMR1CH4 = 0x06, /*!< exint line15/timer1 ch4 event as trigger source of adc1 preempt sequence */
ADC12_PREEMPT_TRIG_SOFTWARE = 0x07, /*!< software(PCSWTRG) control bit as trigger source of adc1 preempt sequence */
ADC12_PREEMPT_TRIG_TMR1CH1 = 0x0D, /*!< timer1 ch1 event as trigger source of adc1 preempt sequence */
} adc_preempt_trig_select_type;
/**
* @brief adc preempt channel type
*/
typedef enum
{
ADC_PREEMPT_CHANNEL_1 = 0x00, /*!< adc preempt channel 1 */
ADC_PREEMPT_CHANNEL_2 = 0x01, /*!< adc preempt channel 2 */
ADC_PREEMPT_CHANNEL_3 = 0x02, /*!< adc preempt channel 3 */
ADC_PREEMPT_CHANNEL_4 = 0x03 /*!< adc preempt channel 4 */
} adc_preempt_channel_type;
/**
* @brief adc voltage_monitoring type
*/
typedef enum
{
ADC_VMONITOR_SINGLE_ORDINARY = 0x00800200, /*!< voltage_monitoring on a single ordinary channel */
ADC_VMONITOR_SINGLE_PREEMPT = 0x00400200, /*!< voltage_monitoring on a single preempt channel */
ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT = 0x00C00200, /*!< voltage_monitoring on a single ordinary or preempt channel */
ADC_VMONITOR_ALL_ORDINARY = 0x00800000, /*!< voltage_monitoring on all ordinary channel */
ADC_VMONITOR_ALL_PREEMPT = 0x00400000, /*!< voltage_monitoring on all preempt channel */
ADC_VMONITOR_ALL_ORDINARY_PREEMPT = 0x00C00000, /*!< voltage_monitoring on all ordinary and preempt channel */
ADC_VMONITOR_NONE = 0x00000000 /*!< no channel guarded by the voltage_monitoring */
} adc_voltage_monitoring_type;
/**
* @brief adc base config type
*/
typedef struct
{
confirm_state sequence_mode; /*!< adc sequence mode */
confirm_state repeat_mode; /*!< adc repeat mode */
adc_data_align_type data_align; /*!< adc data alignment */
uint8_t ordinary_channel_length; /*!< adc ordinary channel sequence length*/
} adc_base_config_type;
/**
* @brief type define adc register all
*/
typedef struct
{
/**
* @brief adc sts register, offset:0x00
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t vmor : 1; /* [0] */
__IO uint32_t cce : 1; /* [1] */
__IO uint32_t pcce : 1; /* [2] */
__IO uint32_t pccs : 1; /* [3] */
__IO uint32_t occs : 1; /* [4] */
__IO uint32_t reserved1 : 27;/* [31:5] */
} sts_bit;
};
/**
* @brief adc ctrl1 register, offset:0x04
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t vmcsel : 5; /* [4:0] */
__IO uint32_t cceien : 1; /* [5] */
__IO uint32_t vmorien : 1; /* [6] */
__IO uint32_t pcceien : 1; /* [7] */
__IO uint32_t sqen : 1; /* [8] */
__IO uint32_t vmsgen : 1; /* [9] */
__IO uint32_t pcautoen : 1; /* [10] */
__IO uint32_t ocpen : 1; /* [11] */
__IO uint32_t pcpen : 1; /* [12] */
__IO uint32_t ocpcnt : 3; /* [15:13] */
__IO uint32_t reserved1 : 6; /* [21:16] */
__IO uint32_t pcvmen : 1; /* [22] */
__IO uint32_t ocvmen : 1; /* [23] */
__IO uint32_t reserved2 : 8; /* [31:24] */
} ctrl1_bit;
};
/**
* @brief adc ctrl2 register, offset:0x08
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t adcen : 1; /* [0] */
__IO uint32_t rpen : 1; /* [1] */
__IO uint32_t adcal : 1; /* [2] */
__IO uint32_t adcalinit : 1; /* [3] */
__IO uint32_t reserved1 : 4; /* [7:4] */
__IO uint32_t ocdmaen : 1; /* [8] */
__IO uint32_t reserved2 : 2; /* [10:9] */
__IO uint32_t dtalign : 1; /* [11] */
__IO uint32_t pctesel_l : 3; /* [14:12] */
__IO uint32_t pcten : 1; /* [15] */
__IO uint32_t reserved3 : 1; /* [16] */
__IO uint32_t octesel_l : 3; /* [19:17] */
__IO uint32_t octen : 1; /* [20] */
__IO uint32_t pcswtrg : 1; /* [21] */
__IO uint32_t ocswtrg : 1; /* [22] */
__IO uint32_t itsrven : 1; /* [23] */
__IO uint32_t pctesel_h : 1; /* [24] */
__IO uint32_t octesel_h : 1; /* [25] */
__IO uint32_t reserved4 : 6; /* [31:26] */
} ctrl2_bit;
};
/**
* @brief adc spt1 register, offset:0x0C
*/
union
{
__IO uint32_t spt1;
struct
{
__IO uint32_t cspt10 : 3; /* [2:0] */
__IO uint32_t cspt11 : 3; /* [5:3] */
__IO uint32_t cspt12 : 3; /* [8:6] */
__IO uint32_t cspt13 : 3; /* [11:9] */
__IO uint32_t cspt14 : 3; /* [14:12] */
__IO uint32_t cspt15 : 3; /* [17:15] */
__IO uint32_t cspt16 : 3; /* [20:18] */
__IO uint32_t cspt17 : 3; /* [23:21] */
__IO uint32_t reserved1 : 8;/* [31:24] */
} spt1_bit;
};
/**
* @brief adc spt2 register, offset:0x10
*/
union
{
__IO uint32_t spt2;
struct
{
__IO uint32_t cspt0 : 3;/* [2:0] */
__IO uint32_t cspt1 : 3;/* [5:3] */
__IO uint32_t cspt2 : 3;/* [8:6] */
__IO uint32_t cspt3 : 3;/* [11:9] */
__IO uint32_t cspt4 : 3;/* [14:12] */
__IO uint32_t cspt5 : 3;/* [17:15] */
__IO uint32_t cspt6 : 3;/* [20:18] */
__IO uint32_t cspt7 : 3;/* [23:21] */
__IO uint32_t cspt8 : 3;/* [26:24] */
__IO uint32_t cspt9 : 3;/* [29:27] */
__IO uint32_t reserved1 : 2;/* [31:30] */
} spt2_bit;
};
/**
* @brief adc pcdto1 register, offset:0x14
*/
union
{
__IO uint32_t pcdto1;
struct
{
__IO uint32_t pcdto1 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto1_bit;
};
/**
* @brief adc pcdto2 register, offset:0x18
*/
union
{
__IO uint32_t pcdto2;
struct
{
__IO uint32_t pcdto2 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto2_bit;
};
/**
* @brief adc pcdto3 register, offset:0x1C
*/
union
{
__IO uint32_t pcdto3;
struct
{
__IO uint32_t pcdto3 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto3_bit;
};
/**
* @brief adc pcdto4 register, offset:0x20
*/
union
{
__IO uint32_t pcdto4;
struct
{
__IO uint32_t pcdto4 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto4_bit;
};
/**
* @brief adc vmhb register, offset:0x24
*/
union
{
__IO uint32_t vmhb;
struct
{
__IO uint32_t vmhb : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} vmhb_bit;
};
/**
* @brief adc vmlb register, offset:0x28
*/
union
{
__IO uint32_t vmlb;
struct
{
__IO uint32_t vmlb : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} vmlb_bit;
};
/**
* @brief adc osq1 register, offset:0x2C
*/
union
{
__IO uint32_t osq1;
struct
{
__IO uint32_t osn13 : 5; /* [4:0] */
__IO uint32_t osn14 : 5; /* [9:5] */
__IO uint32_t osn15 : 5; /* [14:10] */
__IO uint32_t osn16 : 5; /* [19:15] */
__IO uint32_t oclen : 4; /* [23:20] */
__IO uint32_t reserved1 : 8; /* [31:24] */
} osq1_bit;
};
/**
* @brief adc osq2 register, offset:0x30
*/
union
{
__IO uint32_t osq2;
struct
{
__IO uint32_t osn7 : 5; /* [4:0] */
__IO uint32_t osn8 : 5; /* [9:5] */
__IO uint32_t osn9 : 5; /* [14:10] */
__IO uint32_t osn10 : 5; /* [19:15] */
__IO uint32_t osn11 : 5; /* [24:20] */
__IO uint32_t osn12 : 5; /* [29:25] */
__IO uint32_t reserved1 : 2; /* [31:30] */
} osq2_bit;
};
/**
* @brief adc osq3 register, offset:0x34
*/
union
{
__IO uint32_t osq3;
struct
{
__IO uint32_t osn1 : 5; /* [4:0] */
__IO uint32_t osn2 : 5; /* [9:5] */
__IO uint32_t osn3 : 5; /* [14:10] */
__IO uint32_t osn4 : 5; /* [19:15] */
__IO uint32_t osn5 : 5; /* [24:20] */
__IO uint32_t osn6 : 5; /* [29:25] */
__IO uint32_t reserved1 : 2; /* [31:30] */
} osq3_bit;
};
/**
* @brief adc psq register, offset:0x38
*/
union
{
__IO uint32_t psq;
struct
{
__IO uint32_t psn1 : 5; /* [4:0] */
__IO uint32_t psn2 : 5; /* [9:5] */
__IO uint32_t psn3 : 5; /* [14:10] */
__IO uint32_t psn4 : 5; /* [19:15] */
__IO uint32_t pclen : 2; /* [21:20] */
__IO uint32_t reserved1 : 10;/* [31:22] */
} psq_bit;
};
/**
* @brief adc pdt1 register, offset:0x3C
*/
union
{
__IO uint32_t pdt1;
struct
{
__IO uint32_t pdt1 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt1_bit;
};
/**
* @brief adc pdt2 register, offset:0x40
*/
union
{
__IO uint32_t pdt2;
struct
{
__IO uint32_t pdt2 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt2_bit;
};
/**
* @brief adc pdt3 register, offset:0x44
*/
union
{
__IO uint32_t pdt3;
struct
{
__IO uint32_t pdt3 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt3_bit;
};
/**
* @brief adc pdt4 register, offset:0x48
*/
union
{
__IO uint32_t pdt4;
struct
{
__IO uint32_t pdt4 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt4_bit;
};
/**
* @brief adc odt register, offset:0x4C
*/
union
{
__IO uint32_t odt;
struct
{
__IO uint32_t odt : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} odt_bit;
};
} adc_type;
/**
* @}
*/
#define ADC1 ((adc_type *) ADC1_BASE)
/** @defgroup ADC_exported_functions
* @{
*/
void adc_reset(adc_type *adc_x);
void adc_enable(adc_type *adc_x, confirm_state new_state);
void adc_base_default_para_init(adc_base_config_type *adc_base_struct);
void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct);
void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state);
void adc_calibration_init(adc_type *adc_x);
flag_status adc_calibration_init_status_get(adc_type *adc_x);
void adc_calibration_start(adc_type *adc_x);
flag_status adc_calibration_status_get(adc_type *adc_x);
void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring);
void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold);
void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel);
void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght);
void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, confirm_state new_state);
void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, confirm_state new_state);
void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value);
void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count);
void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_tempersensor_vintrv_enable(confirm_state new_state);
void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x);
void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag);
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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libraries/drivers/inc/at32f415_can.h Normal file
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/**
**************************************************************************
* @file at32f415_can.h
* @brief at32f415 can header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_CAN_H
#define __AT32F415_CAN_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup CAN
* @{
*/
/** @defgroup CAN_timeout_count
* @{
*/
#define FZC_TIMEOUT ((uint32_t)0x0000FFFF) /*!< time out for fzc bit */
#define DZC_TIMEOUT ((uint32_t)0x0000FFFF) /*!< time out for dzc bit */
/**
* @}
*/
/** @defgroup CAN_flags_definition
* @brief can flag
* @{
*/
#define CAN_EAF_FLAG ((uint32_t)0x01) /*!< error active flag */
#define CAN_EPF_FLAG ((uint32_t)0x02) /*!< error passive flag */
#define CAN_BOF_FLAG ((uint32_t)0x03) /*!< bus-off flag */
#define CAN_ETR_FLAG ((uint32_t)0x04) /*!< error type record flag */
#define CAN_EOIF_FLAG ((uint32_t)0x05) /*!< error occur interrupt flag */
#define CAN_TM0TCF_FLAG ((uint32_t)0x06) /*!< transmit mailbox 0 transmission completed flag */
#define CAN_TM1TCF_FLAG ((uint32_t)0x07) /*!< transmit mailbox 1 transmission completed flag */
#define CAN_TM2TCF_FLAG ((uint32_t)0x08) /*!< transmit mailbox 2 transmission completed flag */
#define CAN_RF0MN_FLAG ((uint32_t)0x09) /*!< receive fifo 0 message num flag */
#define CAN_RF0FF_FLAG ((uint32_t)0x0A) /*!< receive fifo 0 full flag */
#define CAN_RF0OF_FLAG ((uint32_t)0x0B) /*!< receive fifo 0 overflow flag */
#define CAN_RF1MN_FLAG ((uint32_t)0x0C) /*!< receive fifo 1 message num flag */
#define CAN_RF1FF_FLAG ((uint32_t)0x0D) /*!< receive fifo 1 full flag */
#define CAN_RF1OF_FLAG ((uint32_t)0x0E) /*!< receive fifo 1 overflow flag */
#define CAN_QDZIF_FLAG ((uint32_t)0x0F) /*!< quit doze mode interrupt flag */
#define CAN_EDZC_FLAG ((uint32_t)0x10) /*!< enter doze mode confirm flag */
#define CAN_TMEF_FLAG ((uint32_t)0x11) /*!< transmit mailbox empty flag */
/**
* @}
*/
/** @defgroup CAN_interrupts_definition
* @brief can interrupt
* @{
*/
#define CAN_TCIEN_INT ((uint32_t)0x00000001) /*!< transmission complete interrupt */
#define CAN_RF0MIEN_INT ((uint32_t)0x00000002) /*!< receive fifo 0 message interrupt */
#define CAN_RF0FIEN_INT ((uint32_t)0x00000004) /*!< receive fifo 0 full interrupt */
#define CAN_RF0OIEN_INT ((uint32_t)0x00000008) /*!< receive fifo 0 overflow interrupt */
#define CAN_RF1MIEN_INT ((uint32_t)0x00000010) /*!< receive fifo 1 message interrupt */
#define CAN_RF1FIEN_INT ((uint32_t)0x00000020) /*!< receive fifo 1 full interrupt */
#define CAN_RF1OIEN_INT ((uint32_t)0x00000040) /*!< receive fifo 1 overflow interrupt */
#define CAN_EAIEN_INT ((uint32_t)0x00000100) /*!< error active interrupt */
#define CAN_EPIEN_INT ((uint32_t)0x00000200) /*!< error passive interrupt */
#define CAN_BOIEN_INT ((uint32_t)0x00000400) /*!< bus-off interrupt */
#define CAN_ETRIEN_INT ((uint32_t)0x00000800) /*!< error type record interrupt */
#define CAN_EOIEN_INT ((uint32_t)0x00008000) /*!< error occur interrupt */
#define CAN_QDZIEN_INT ((uint32_t)0x00010000) /*!< quit doze mode interrupt */
#define CAN_EDZIEN_INT ((uint32_t)0x00020000) /*!< enter doze mode confirm interrupt */
/**
* @}
*/
/**
* @brief can flag clear operation macro definition val
*/
#define CAN_MSTS_EOIF_VAL ((uint32_t)0x00000004) /*!< eoif bit value, it clear by writing 1 */
#define CAN_MSTS_QDZIF_VAL ((uint32_t)0x00000008) /*!< qdzif bit value, it clear by writing 1 */
#define CAN_MSTS_EDZIF_VAL ((uint32_t)0x00000010) /*!< edzif bit value, it clear by writing 1 */
#define CAN_TSTS_TM0TCF_VAL ((uint32_t)0x00000001) /*!< tm0tcf bit value, it clear by writing 1 */
#define CAN_TSTS_TM1TCF_VAL ((uint32_t)0x00000100) /*!< tm1tcf bit value, it clear by writing 1 */
#define CAN_TSTS_TM2TCF_VAL ((uint32_t)0x00010000) /*!< tm2tcf bit value, it clear by writing 1 */
#define CAN_TSTS_TM0CT_VAL ((uint32_t)0x00000080) /*!< tm0ct bit value, it clear by writing 1 */
#define CAN_TSTS_TM1CT_VAL ((uint32_t)0x00008000) /*!< tm1ct bit value, it clear by writing 1 */
#define CAN_TSTS_TM2CT_VAL ((uint32_t)0x00800000) /*!< tm2ct bit value, it clear by writing 1 */
#define CAN_RF0_RF0FF_VAL ((uint32_t)0x00000008) /*!< rf0ff bit value, it clear by writing 1 */
#define CAN_RF0_RF0OF_VAL ((uint32_t)0x00000010) /*!< rf0of bit value, it clear by writing 1 */
#define CAN_RF0_RF0R_VAL ((uint32_t)0x00000020) /*!< rf0r bit value, it clear by writing 1 */
#define CAN_RF1_RF1FF_VAL ((uint32_t)0x00000008) /*!< rf1ff bit value, it clear by writing 1 */
#define CAN_RF1_RF1OF_VAL ((uint32_t)0x00000010) /*!< rf1of bit value, it clear by writing 1 */
#define CAN_RF1_RF1R_VAL ((uint32_t)0x00000020) /*!< rf1r bit value, it clear by writing 1 */
/** @defgroup CAN_exported_types
* @{
*/
/**
* @brief can filter fifo
*/
typedef enum
{
CAN_FILTER_FIFO0 = 0x00, /*!< filter fifo 0 assignment for filter x */
CAN_FILTER_FIFO1 = 0x01 /*!< filter fifo 1 assignment for filter x */
} can_filter_fifo_type;
/**
* @brief can filter mode
*/
typedef enum
{
CAN_FILTER_MODE_ID_MASK = 0x00, /*!< identifier mask mode */
CAN_FILTER_MODE_ID_LIST = 0x01 /*!< identifier list mode */
} can_filter_mode_type;
/**
* @brief can filter bit width select
*/
typedef enum
{
CAN_FILTER_16BIT = 0x00, /*!< two 16-bit filters */
CAN_FILTER_32BIT = 0x01 /*!< one 32-bit filter */
} can_filter_bit_width_type;
/**
* @brief can mode
*/
typedef enum
{
CAN_MODE_COMMUNICATE = 0x00, /*!< communication mode */
CAN_MODE_LOOPBACK = 0x01, /*!< loopback mode */
CAN_MODE_LISTENONLY = 0x02, /*!< listen-only mode */
CAN_MODE_LISTENONLY_LOOPBACK = 0x03 /*!< loopback combined with listen-only mode */
} can_mode_type;
/**
* @brief can operating mode
*/
typedef enum
{
CAN_OPERATINGMODE_FREEZE = 0x00, /*!< freeze mode */
CAN_OPERATINGMODE_DOZE = 0x01, /*!< doze mode */
CAN_OPERATINGMODE_COMMUNICATE = 0x02 /*!< communication mode */
} can_operating_mode_type;
/**
* @brief can resynchronization adjust width
*/
typedef enum
{
CAN_RSAW_1TQ = 0x00, /*!< 1 time quantum */
CAN_RSAW_2TQ = 0x01, /*!< 2 time quantum */
CAN_RSAW_3TQ = 0x02, /*!< 3 time quantum */
CAN_RSAW_4TQ = 0x03 /*!< 4 time quantum */
} can_rsaw_type;
/**
* @brief can bit time segment 1
*/
typedef enum
{
CAN_BTS1_1TQ = 0x00, /*!< 1 time quantum */
CAN_BTS1_2TQ = 0x01, /*!< 2 time quantum */
CAN_BTS1_3TQ = 0x02, /*!< 3 time quantum */
CAN_BTS1_4TQ = 0x03, /*!< 4 time quantum */
CAN_BTS1_5TQ = 0x04, /*!< 5 time quantum */
CAN_BTS1_6TQ = 0x05, /*!< 6 time quantum */
CAN_BTS1_7TQ = 0x06, /*!< 7 time quantum */
CAN_BTS1_8TQ = 0x07, /*!< 8 time quantum */
CAN_BTS1_9TQ = 0x08, /*!< 9 time quantum */
CAN_BTS1_10TQ = 0x09, /*!< 10 time quantum */
CAN_BTS1_11TQ = 0x0A, /*!< 11 time quantum */
CAN_BTS1_12TQ = 0x0B, /*!< 12 time quantum */
CAN_BTS1_13TQ = 0x0C, /*!< 13 time quantum */
CAN_BTS1_14TQ = 0x0D, /*!< 14 time quantum */
CAN_BTS1_15TQ = 0x0E, /*!< 15 time quantum */
CAN_BTS1_16TQ = 0x0F /*!< 16 time quantum */
} can_bts1_type;
/**
* @brief can bit time segment 2
*/
typedef enum
{
CAN_BTS2_1TQ = 0x00, /*!< 1 time quantum */
CAN_BTS2_2TQ = 0x01, /*!< 2 time quantum */
CAN_BTS2_3TQ = 0x02, /*!< 3 time quantum */
CAN_BTS2_4TQ = 0x03, /*!< 4 time quantum */
CAN_BTS2_5TQ = 0x04, /*!< 5 time quantum */
CAN_BTS2_6TQ = 0x05, /*!< 6 time quantum */
CAN_BTS2_7TQ = 0x06, /*!< 7 time quantum */
CAN_BTS2_8TQ = 0x07 /*!< 8 time quantum */
} can_bts2_type;
/**
* @brief can identifier type
*/
typedef enum
{
CAN_ID_STANDARD = 0x00, /*!< standard Id */
CAN_ID_EXTENDED = 0x01 /*!< extended Id */
} can_identifier_type;
/**
* @brief can transmission frame type
*/
typedef enum
{
CAN_TFT_DATA = 0x00, /*!< data frame */
CAN_TFT_REMOTE = 0x01 /*!< remote frame */
} can_trans_frame_type;
/**
* @brief can tx mailboxes
*/
typedef enum
{
CAN_TX_MAILBOX0 = 0x00, /*!< can tx mailbox 0 */
CAN_TX_MAILBOX1 = 0x01, /*!< can tx mailbox 1 */
CAN_TX_MAILBOX2 = 0x02 /*!< can tx mailbox 2 */
} can_tx_mailbox_num_type;
/**
* @brief can receive fifo
*/
typedef enum
{
CAN_RX_FIFO0 = 0x00, /*!< can fifo 0 used to receive */
CAN_RX_FIFO1 = 0x01 /*!< can fifo 1 used to receive */
} can_rx_fifo_num_type;
/**
* @brief can transmit status
*/
typedef enum
{
CAN_TX_STATUS_FAILED = 0x00, /*!< can transmission failed */
CAN_TX_STATUS_SUCCESSFUL = 0x01, /*!< can transmission successful */
CAN_TX_STATUS_PENDING = 0x02, /*!< can transmission pending */
CAN_TX_STATUS_NO_EMPTY = 0x04 /*!< can transmission no empty mailbox */
} can_transmit_status_type;
/**
* @brief can enter doze mode status
*/
typedef enum
{
CAN_ENTER_DOZE_FAILED = 0x00, /*!< can enter the doze mode failed */
CAN_ENTER_DOZE_SUCCESSFUL = 0x01 /*!< can enter the doze mode successful */
} can_enter_doze_status_type;
/**
* @brief can quit doze mode status
*/
typedef enum
{
CAN_QUIT_DOZE_FAILED = 0x00, /*!< can quit doze mode failed */
CAN_QUIT_DOZE_SUCCESSFUL = 0x01 /*!< can quit doze mode successful */
} can_quit_doze_status_type;
/**
* @brief can message discarding rule select when overflow
*/
typedef enum
{
CAN_DISCARDING_FIRST_RECEIVED = 0x00, /*!< can discarding the first received message */
CAN_DISCARDING_LAST_RECEIVED = 0x01 /*!< can discarding the last received message */
} can_msg_discarding_rule_type;
/**
* @brief can multiple message sending sequence rule
*/
typedef enum
{
CAN_SENDING_BY_ID = 0x00, /*!< can sending the minimum id message first*/
CAN_SENDING_BY_REQUEST = 0x01 /*!< can sending the first request message first */
} can_msg_sending_rule_type;
/**
* @brief can error type record
*/
typedef enum
{
CAN_ERRORRECORD_NOERR = 0x00, /*!< no error */
CAN_ERRORRECORD_STUFFERR = 0x01, /*!< stuff error */
CAN_ERRORRECORD_FORMERR = 0x02, /*!< form error */
CAN_ERRORRECORD_ACKERR = 0x03, /*!< acknowledgment error */
CAN_ERRORRECORD_BITRECESSIVEERR = 0x04, /*!< bit recessive error */
CAN_ERRORRECORD_BITDOMINANTERR = 0x05, /*!< bit dominant error */
CAN_ERRORRECORD_CRCERR = 0x06, /*!< crc error */
CAN_ERRORRECORD_SOFTWARESETERR = 0x07 /*!< software set error */
} can_error_record_type;
/**
* @brief can init structure definition
*/
typedef struct
{
can_mode_type mode_selection; /*!< specifies the can mode.*/
confirm_state ttc_enable; /*!< time triggered communication mode enable */
confirm_state aebo_enable; /*!< automatic exit bus-off enable */
confirm_state aed_enable; /*!< automatic exit doze mode enable */
confirm_state prsf_enable; /*!< prohibit retransmission when sending fails enable */
can_msg_discarding_rule_type mdrsel_selection; /*!< message discarding rule select when overflow */
can_msg_sending_rule_type mmssr_selection; /*!< multiple message sending sequence rule */
} can_base_type;
/**
* @brief can baudrate structure definition
*/
typedef struct
{
uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/
can_rsaw_type rsaw_size; /*!< resynchronization adjust width */
can_bts1_type bts1_size; /*!< bit time segment 1 */
can_bts2_type bts2_size; /*!< bit time segment 2 */
} can_baudrate_type;
/**
* @brief can filter init structure definition
*/
typedef struct
{
confirm_state filter_activate_enable; /*!< enable or disable the filter activate.*/
can_filter_mode_type filter_mode; /*!< config the filter mode mask or list.*/
can_filter_fifo_type filter_fifo; /*!< config the fifo which will be assigned to the filter. */
uint8_t filter_number; /*!< config the filter number, parameter ranges from 0 to 13. */
can_filter_bit_width_type filter_bit; /*!< config the filter bit width 16bit or 32bit.*/
uint16_t filter_id_high; /*!< config the filter identification, for 32-bit configuration
it's high 16 bits, for 16-bit configuration it's first. */
uint16_t filter_id_low; /*!< config the filter identification, for 32-bit configuration
it's low 16 bits, for 16-bit configuration it's second. */
uint16_t filter_mask_high; /*!< config the filter mask or identification, according to the filtering mode,
for 32-bit configuration it's high 16 bits, for 16-bit configuration it's first. */
uint16_t filter_mask_low; /*!< config the filter mask or identification, according to the filtering mode,
for 32-bit configuration it's low 16 bits, for 16-bit configuration it's second. */
} can_filter_init_type;
/**
* @brief can tx message structure definition
*/
typedef struct
{
uint32_t standard_id; /*!< specifies the 11 bits standard identifier.
this parameter can be a value between 0 to 0x7FF. */
uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
this parameter can be a value between 0 to 0x1FFFFFFF. */
can_identifier_type id_type; /*!< specifies identifier type for the transmit message.*/
can_trans_frame_type frame_type; /*!< specifies frame type for the transmit message.*/
uint8_t dlc; /*!< specifies frame data length that will be transmitted.
this parameter can be a value between 0 to 8 */
uint8_t data[8]; /*!< contains the transmit data. it ranges from 0 to 0xFF. */
} can_tx_message_type;
/**
* @brief can rx message structure definition
*/
typedef struct
{
uint32_t standard_id; /*!< specifies the 11 bits standard identifier
this parameter can be a value between 0 to 0x7FF. */
uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
this parameter can be a value between 0 to 0x1FFFFFFF. */
can_identifier_type id_type; /*!< specifies identifier type for the receive message.*/
can_trans_frame_type frame_type; /*!< specifies frame type for the receive message.*/
uint8_t dlc; /*!< specifies the frame data length that will be received.
this parameter can be a value between 0 to 8 */
uint8_t data[8]; /*!< contains the receive data. it ranges from 0 to 0xFF.*/
uint8_t filter_index; /*!< specifies the message stored in which filter
this parameter can be a value between 0 to 0xFF */
} can_rx_message_type;
/**
* @brief can controller area network tx mailbox
*/
typedef struct
{
/**
* @brief can tmi register
*/
union
{
__IO uint32_t tmi;
struct
{
__IO uint32_t tmsr : 1; /* [0] */
__IO uint32_t tmfrsel : 1; /* [1] */
__IO uint32_t tmidsel : 1; /* [2] */
__IO uint32_t tmeid : 18;/* [20:3] */
__IO uint32_t tmsid : 11;/* [31:21] */
} tmi_bit;
};
/**
* @brief can tmc register
*/
union
{
__IO uint32_t tmc;
struct
{
__IO uint32_t tmdtbl : 4; /* [3:0] */
__IO uint32_t reserved1 : 4; /* [7:4] */
__IO uint32_t tmtsten : 1; /* [8] */
__IO uint32_t reserved2 : 7; /* [15:9] */
__IO uint32_t tmts : 16;/* [31:16] */
} tmc_bit;
};
/**
* @brief can tmdtl register
*/
union
{
__IO uint32_t tmdtl;
struct
{
__IO uint32_t tmdt0 : 8; /* [7:0] */
__IO uint32_t tmdt1 : 8; /* [15:8] */
__IO uint32_t tmdt2 : 8; /* [23:16] */
__IO uint32_t tmdt3 : 8; /* [31:24] */
} tmdtl_bit;
};
/**
* @brief can tmdth register
*/
union
{
__IO uint32_t tmdth;
struct
{
__IO uint32_t tmdt4 : 8; /* [7:0] */
__IO uint32_t tmdt5 : 8; /* [15:8] */
__IO uint32_t tmdt6 : 8; /* [23:16] */
__IO uint32_t tmdt7 : 8; /* [31:24] */
} tmdth_bit;
};
} can_tx_mailbox_type;
/**
* @brief can controller area network fifo mailbox
*/
typedef struct
{
/**
* @brief can rfi register
*/
union
{
__IO uint32_t rfi;
struct
{
__IO uint32_t reserved1 : 1; /* [0] */
__IO uint32_t rffri : 1; /* [1] */
__IO uint32_t rfidi : 1; /* [2] */
__IO uint32_t rfeid : 18;/* [20:3] */
__IO uint32_t rfsid : 11;/* [31:21] */
} rfi_bit;
};
/**
* @brief can rfc register
*/
union
{
__IO uint32_t rfc;
struct
{
__IO uint32_t rfdtl : 4; /* [3:0] */
__IO uint32_t reserved1 : 4; /* [7:4] */
__IO uint32_t rffmn : 8; /* [15:8] */
__IO uint32_t rfts : 16;/* [31:16] */
} rfc_bit;
};
/**
* @brief can rfdtl register
*/
union
{
__IO uint32_t rfdtl;
struct
{
__IO uint32_t rfdt0 : 8; /* [7:0] */
__IO uint32_t rfdt1 : 8; /* [15:8] */
__IO uint32_t rfdt2 : 8; /* [23:16] */
__IO uint32_t rfdt3 : 8; /* [31:24] */
} rfdtl_bit;
};
/**
* @brief can rfdth register
*/
union
{
__IO uint32_t rfdth;
struct
{
__IO uint32_t rfdt4 : 8; /* [7:0] */
__IO uint32_t rfdt5 : 8; /* [15:8] */
__IO uint32_t rfdt6 : 8; /* [23:16] */
__IO uint32_t rfdt7 : 8; /* [31:24] */
} rfdth_bit;
};
} can_fifo_mailbox_type;
/**
* @brief can controller area network filter bit register
*/
typedef struct
{
__IO uint32_t ffdb1;
__IO uint32_t ffdb2;
} can_filter_register_type;
/**
* @brief type define can register all
*/
typedef struct
{
/**
* @brief can mctrl register, offset:0x00
*/
union
{
__IO uint32_t mctrl;
struct
{
__IO uint32_t fzen : 1; /* [0] */
__IO uint32_t dzen : 1; /* [1] */
__IO uint32_t mmssr : 1; /* [2] */
__IO uint32_t mdrsel : 1; /* [3] */
__IO uint32_t prsfen : 1; /* [4] */
__IO uint32_t aeden : 1; /* [5] */
__IO uint32_t aeboen : 1; /* [6] */
__IO uint32_t ttcen : 1; /* [7] */
__IO uint32_t reserved1 : 7; /* [14:8] */
__IO uint32_t sprst : 1; /* [15] */
__IO uint32_t ptd : 1; /* [16] */
__IO uint32_t reserved2 : 15;/*[31:17] */
} mctrl_bit;
};
/**
* @brief can msts register, offset:0x04
*/
union
{
__IO uint32_t msts;
struct
{
__IO uint32_t fzc : 1; /* [0] */
__IO uint32_t dzc : 1; /* [1] */
__IO uint32_t eoif : 1; /* [2] */
__IO uint32_t qdzif : 1; /* [3] */
__IO uint32_t edzif : 1; /* [4] */
__IO uint32_t reserved1 : 3; /* [7:5] */
__IO uint32_t cuss : 1; /* [8] */
__IO uint32_t curs : 1; /* [9] */
__IO uint32_t lsamprx : 1; /* [10] */
__IO uint32_t realrx : 1; /* [11] */
__IO uint32_t reserved2 : 20;/*[31:12] */
} msts_bit;
};
/**
* @brief can tsts register, offset:0x08
*/
union
{
__IO uint32_t tsts;
struct
{
__IO uint32_t tm0tcf : 1; /* [0] */
__IO uint32_t tm0tsf : 1; /* [1] */
__IO uint32_t tm0alf : 1; /* [2] */
__IO uint32_t tm0tef : 1; /* [3] */
__IO uint32_t reserved1 : 3; /* [6:4] */
__IO uint32_t tm0ct : 1; /* [7] */
__IO uint32_t tm1tcf : 1; /* [8] */
__IO uint32_t tm1tsf : 1; /* [9] */
__IO uint32_t tm1alf : 1; /* [10] */
__IO uint32_t tm1tef : 1; /* [11] */
__IO uint32_t reserved2 : 3; /* [14:12] */
__IO uint32_t tm1ct : 1; /* [15] */
__IO uint32_t tm2tcf : 1; /* [16] */
__IO uint32_t tm2tsf : 1; /* [17] */
__IO uint32_t tm2alf : 1; /* [18] */
__IO uint32_t tm2tef : 1; /* [19] */
__IO uint32_t reserved3 : 3; /* [22:20] */
__IO uint32_t tm2ct : 1; /* [23] */
__IO uint32_t tmnr : 2; /* [25:24] */
__IO uint32_t tm0ef : 1; /* [26] */
__IO uint32_t tm1ef : 1; /* [27] */
__IO uint32_t tm2ef : 1; /* [28] */
__IO uint32_t tm0lpf : 1; /* [29] */
__IO uint32_t tm1lpf : 1; /* [30] */
__IO uint32_t tm2lpf : 1; /* [31] */
} tsts_bit;
};
/**
* @brief can rf0 register, offset:0x0C
*/
union
{
__IO uint32_t rf0;
struct
{
__IO uint32_t rf0mn : 2; /* [1:0] */
__IO uint32_t reserved1 : 1; /* [2] */
__IO uint32_t rf0ff : 1; /* [3] */
__IO uint32_t rf0of : 1; /* [4] */
__IO uint32_t rf0r : 1; /* [5] */
__IO uint32_t reserved2 : 26;/* [31:6] */
} rf0_bit;
};
/**
* @brief can rf1 register, offset:0x10
*/
union
{
__IO uint32_t rf1;
struct
{
__IO uint32_t rf1mn : 2; /* [1:0] */
__IO uint32_t reserved1 : 1; /* [2] */
__IO uint32_t rf1ff : 1; /* [3] */
__IO uint32_t rf1of : 1; /* [4] */
__IO uint32_t rf1r : 1; /* [5] */
__IO uint32_t reserved2 : 26;/* [31:6] */
} rf1_bit;
};
/**
* @brief can inten register, offset:0x14
*/
union
{
__IO uint32_t inten;
struct
{
__IO uint32_t tcien : 1; /* [0] */
__IO uint32_t rf0mien : 1; /* [1] */
__IO uint32_t rf0fien : 1; /* [2] */
__IO uint32_t rf0oien : 1; /* [3] */
__IO uint32_t rf1mien : 1; /* [4] */
__IO uint32_t rf1fien : 1; /* [5] */
__IO uint32_t rf1oien : 1; /* [6] */
__IO uint32_t reserved1 : 1; /* [7] */
__IO uint32_t eaien : 1; /* [8] */
__IO uint32_t epien : 1; /* [9] */
__IO uint32_t boien : 1; /* [10] */
__IO uint32_t etrien : 1; /* [11] */
__IO uint32_t reserved2 : 3; /* [14:12] */
__IO uint32_t eoien : 1; /* [15] */
__IO uint32_t qdzien : 1; /* [16] */
__IO uint32_t edzien : 1; /* [17] */
__IO uint32_t reserved3 : 14;/* [31:18] */
} inten_bit;
};
/**
* @brief can ests register, offset:0x18
*/
union
{
__IO uint32_t ests;
struct
{
__IO uint32_t eaf : 1; /* [0] */
__IO uint32_t epf : 1; /* [1] */
__IO uint32_t bof : 1; /* [2] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t etr : 3; /* [6:4] */
__IO uint32_t reserved2 : 9; /* [15:7] */
__IO uint32_t tec : 8; /* [23:16] */
__IO uint32_t rec : 8; /* [31:24] */
} ests_bit;
};
/**
* @brief can btmg register, offset:0x1C
*/
union
{
__IO uint32_t btmg;
struct
{
__IO uint32_t brdiv : 12;/* [11:0] */
__IO uint32_t reserved1 : 4; /* [15:12] */
__IO uint32_t bts1 : 4; /* [19:16] */
__IO uint32_t bts2 : 3; /* [22:20] */
__IO uint32_t reserved2 : 1; /* [23] */
__IO uint32_t rsaw : 2; /* [25:24] */
__IO uint32_t reserved3 : 4; /* [29:26] */
__IO uint32_t lben : 1; /* [30] */
__IO uint32_t loen : 1; /* [31] */
} btmg_bit;
};
/**
* @brief can reserved register, offset:0x20~0x17C
*/
__IO uint32_t reserved1[88];
/**
* @brief can controller area network tx mailbox register, offset:0x180~0x1AC
*/
can_tx_mailbox_type tx_mailbox[3];
/**
* @brief can controller area network fifo mailbox register, offset:0x1B0~0x1CC
*/
can_fifo_mailbox_type fifo_mailbox[2];
/**
* @brief can reserved register, offset:0x1D0~0x1FC
*/
__IO uint32_t reserved2[12];
/**
* @brief can fctrl register, offset:0x200
*/
union
{
__IO uint32_t fctrl;
struct
{
__IO uint32_t fcs : 1; /* [0] */
__IO uint32_t reserved1 : 31;/* [31:1] */
} fctrl_bit;
};
/**
* @brief can fmcfg register, offset:0x204
*/
union
{
__IO uint32_t fmcfg;
struct
{
__IO uint32_t fmsel0 : 1; /* [0] */
__IO uint32_t fmsel1 : 1; /* [1] */
__IO uint32_t fmsel2 : 1; /* [2] */
__IO uint32_t fmsel3 : 1; /* [3] */
__IO uint32_t fmsel4 : 1; /* [4] */
__IO uint32_t fmsel5 : 1; /* [5] */
__IO uint32_t fmsel6 : 1; /* [6] */
__IO uint32_t fmsel7 : 1; /* [7] */
__IO uint32_t fmsel8 : 1; /* [8] */
__IO uint32_t fmsel9 : 1; /* [9] */
__IO uint32_t fmsel10 : 1; /* [10] */
__IO uint32_t fmsel11 : 1; /* [11] */
__IO uint32_t fmsel12 : 1; /* [12] */
__IO uint32_t fmsel13 : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} fmcfg_bit;
};
/**
* @brief can reserved register, offset:0x208
*/
__IO uint32_t reserved3;
/**
* @brief can fbwcfg register, offset:0x20C
*/
union
{
__IO uint32_t fbwcfg;
struct
{
__IO uint32_t fbwsel0 : 1; /* [0] */
__IO uint32_t fbwsel1 : 1; /* [1] */
__IO uint32_t fbwsel2 : 1; /* [2] */
__IO uint32_t fbwsel3 : 1; /* [3] */
__IO uint32_t fbwsel4 : 1; /* [4] */
__IO uint32_t fbwsel5 : 1; /* [5] */
__IO uint32_t fbwsel6 : 1; /* [6] */
__IO uint32_t fbwsel7 : 1; /* [7] */
__IO uint32_t fbwsel8 : 1; /* [8] */
__IO uint32_t fbwsel9 : 1; /* [9] */
__IO uint32_t fbwsel10 : 1; /* [10] */
__IO uint32_t fbwsel11 : 1; /* [11] */
__IO uint32_t fbwsel12 : 1; /* [12] */
__IO uint32_t fbwsel13 : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} fbwcfg_bit;
};
/**
* @brief can reserved register, offset:0x210
*/
__IO uint32_t reserved4;
/**
* @brief can frf register, offset:0x214
*/
union
{
__IO uint32_t frf;
struct
{
__IO uint32_t frfsel0 : 1; /* [0] */
__IO uint32_t frfsel1 : 1; /* [1] */
__IO uint32_t frfsel2 : 1; /* [2] */
__IO uint32_t frfsel3 : 1; /* [3] */
__IO uint32_t frfsel4 : 1; /* [4] */
__IO uint32_t frfsel5 : 1; /* [5] */
__IO uint32_t frfsel6 : 1; /* [6] */
__IO uint32_t frfsel7 : 1; /* [7] */
__IO uint32_t frfsel8 : 1; /* [8] */
__IO uint32_t frfsel9 : 1; /* [9] */
__IO uint32_t frfsel10 : 1; /* [10] */
__IO uint32_t frfsel11 : 1; /* [11] */
__IO uint32_t frfsel12 : 1; /* [12] */
__IO uint32_t frfsel13 : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} frf_bit;
};
/**
* @brief can reserved register, offset:0x218
*/
__IO uint32_t reserved5;
/**
* @brief can facfg register, offset:0x21C
*/
union
{
__IO uint32_t facfg;
struct
{
__IO uint32_t faen0 : 1; /* [0] */
__IO uint32_t faen1 : 1; /* [1] */
__IO uint32_t faen2 : 1; /* [2] */
__IO uint32_t faen3 : 1; /* [3] */
__IO uint32_t faen4 : 1; /* [4] */
__IO uint32_t faen5 : 1; /* [5] */
__IO uint32_t faen6 : 1; /* [6] */
__IO uint32_t faen7 : 1; /* [7] */
__IO uint32_t faen8 : 1; /* [8] */
__IO uint32_t faen9 : 1; /* [9] */
__IO uint32_t faen10 : 1; /* [10] */
__IO uint32_t faen11 : 1; /* [11] */
__IO uint32_t faen12 : 1; /* [12] */
__IO uint32_t faen13 : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} facfg_bit;
};
/**
* @brief can reserved register, offset:0x220~0x23C
*/
__IO uint32_t reserved6[8];
/**
* @brief can ffb register, offset:0x240~0x2AC
*/
can_filter_register_type ffb[14];
} can_type;
/**
* @}
*/
#define CAN1 ((can_type *) CAN1_BASE)
/** @defgroup CAN_exported_functions
* @{
*/
void can_reset(can_type* can_x);
void can_baudrate_default_para_init(can_baudrate_type* can_baudrate_struct);
error_status can_baudrate_set(can_type* can_x, can_baudrate_type* can_baudrate_struct);
void can_default_para_init(can_base_type* can_base_struct);
error_status can_base_init(can_type* can_x, can_base_type* can_base_struct);
void can_filter_default_para_init(can_filter_init_type* can_filter_init_struct);
void can_filter_init(can_type* can_x, can_filter_init_type* can_filter_init_struct);
void can_debug_transmission_prohibit(can_type* can_x, confirm_state new_state);
void can_ttc_mode_enable(can_type* can_x, confirm_state new_state);
uint8_t can_message_transmit(can_type* can_x, can_tx_message_type* tx_message_struct);
can_transmit_status_type can_transmit_status_get(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
void can_transmit_cancel(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
void can_message_receive(can_type* can_x, can_rx_fifo_num_type fifo_number, can_rx_message_type* rx_message_struct);
void can_receive_fifo_release(can_type* can_x, can_rx_fifo_num_type fifo_number);
uint8_t can_receive_message_pending_get(can_type* can_x, can_rx_fifo_num_type fifo_number);
error_status can_operating_mode_set(can_type* can_x, can_operating_mode_type can_operating_mode);
can_enter_doze_status_type can_doze_mode_enter(can_type* can_x);
can_quit_doze_status_type can_doze_mode_exit(can_type* can_x);
can_error_record_type can_error_type_record_get(can_type* can_x);
uint8_t can_receive_error_counter_get(can_type* can_x);
uint8_t can_transmit_error_counter_get(can_type* can_x);
void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state);
flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag);
flag_status can_flag_get(can_type* can_x, uint32_t can_flag);
void can_flag_clear(can_type* can_x, uint32_t can_flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f415_cmp.h
* @brief at32f415 cmp header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_CMP_H
#define __AT32F415_CMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup CMP
* @{
*/
/** @defgroup CMP_exported_types
* @{
*/
/**
* @brief cmp non-inverting type
*/
typedef enum
{
CMP_NON_INVERTING_PA5_PA7 = 0x00, /*!< comparator1/2 non-inverting connect to pa5/pa7 */
CMP_NON_INVERTING_PA1_PA3 = 0x01, /*!< comparator1/2 non-inverting connect to pa1/pa3 */
CMP_NON_INVERTING_PA0_PA2 = 0x02, /*!< comparator1/2 non-inverting connect to pa0/pa2 */
} cmp_non_inverting_type;
/**
* @brief cmp inverting type
*/
typedef enum
{
CMP_INVERTING_1_4VREFINT = 0x00, /*!< comparator inverting connect to 1_4vrefint */
CMP_INVERTING_1_2VREFINT = 0x01, /*!< comparator inverting connect to 1_2vrefint */
CMP_INVERTING_3_4VREFINT = 0x02, /*!< comparator inverting connect to 3_4vrefint */
CMP_INVERTING_VREFINT = 0x03, /*!< comparator inverting connect to vrefint */
CMP_INVERTING_PA4 = 0x04, /*!< comparator inverting connect to pa4 */
CMP_INVERTING_PA5 = 0x05, /*!< comparator inverting connect to pa5 */
CMP_INVERTING_PA0_PA2 = 0x06, /*!< comparator1/2 inverting connect to pa0/pa2 */
} cmp_inverting_type;
/**
* @brief cmp speed type
*/
typedef enum
{
CMP_SPEED_FAST = 0x00, /*!< comparator selected fast speed */
CMP_SPEED_SLOW = 0x01, /*!< comparator selected slow speed */
} cmp_speed_type;
#define CMP_OUTPUT_TMR1CXORAW_OFF CMP_OUTPUT_TMR1CHCLR
#define CMP_OUTPUT_TMR2CXORAW_OFF CMP_OUTPUT_TMR2CHCLR
#define CMP_OUTPUT_TMR3CXORAW_OFF CMP_OUTPUT_TMR3CHCLR
/**
* @brief cmp output type
*/
typedef enum
{
CMP_OUTPUT_NONE = 0x00, /*!< comparator has no output */
CMP_OUTPUT_TMR1BRK = 0x01, /*!< comparator output connect to tmr1brk */
CMP_OUTPUT_TMR1CH1 = 0x02, /*!< comparator output connect to tmr1ch1 */
CMP_OUTPUT_TMR1CHCLR = 0x03, /*!< comparator output connect to tmr1chclr */
CMP_OUTPUT_TMR2CH4 = 0x04, /*!< comparator output connect to tmr1chclr */
CMP_OUTPUT_TMR2CHCLR = 0x05, /*!< comparator output connect to tmr1chclr */
CMP_OUTPUT_TMR3CH1 = 0x06, /*!< comparator output connect to tmr3ch1 */
CMP_OUTPUT_TMR3CHCLR = 0x07 /*!< comparator output connect to tmr3chclr */
} cmp_output_type;
/**
* @brief cmp polarity type
*/
typedef enum
{
CMP_POL_NON_INVERTING = 0x00, /*!< comparator polarity non-inverting */
CMP_POL_INVERTING = 0x01, /*!< comparator polarity inverting */
} cmp_polarity_type;
/**
* @brief cmp hysteresis type
*/
typedef enum
{
CMP_HYSTERESIS_NONE = 0x00, /*!< comparator selected no hysteresis */
CMP_HYSTERESIS_LOW = 0x01, /*!< comparator selected low hysteresis */
CMP_HYSTERESIS_MEDIUM = 0x02, /*!< comparator selected medium hysteresis */
CMP_HYSTERESIS_HIGH = 0x03 /*!< comparator selected high hysteresis */
} cmp_hysteresis_type;
/**
* @brief cmp selection type
*/
typedef enum
{
CMP1_SELECTION = 0x00, /*!< select comparator 1 */
CMP2_SELECTION = 0x01, /*!< select comparator 2 */
} cmp_sel_type;
/**
* @brief cmp init type
*/
typedef struct
{
cmp_non_inverting_type cmp_non_inverting; /*!< comparator non-inverting input selection */
cmp_inverting_type cmp_inverting; /*!< comparator inverting selection */
cmp_speed_type cmp_speed; /*!< comparator speed selection */
cmp_output_type cmp_output; /*!< comparator output target selection */
cmp_polarity_type cmp_polarity; /*!< comparator polarity selection */
cmp_hysteresis_type cmp_hysteresis; /*!< comparator hysteresis selection */
}cmp_init_type;
/**
* @brief type define cmp register all
*/
typedef struct
{
/**
* @brief cmp control and status register1, offset:0x00
*/
union
{
__IO uint32_t ctrlsts1;
struct
{
__IO uint32_t cmp1en : 1; /* [0] */
__IO uint32_t cmp1is : 1; /* [1] */
__IO uint32_t cmp1ssel : 1; /* [2] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t cmp1invsel : 3; /* [6:4] */
__IO uint32_t reserved2 : 1; /* [7] */
__IO uint32_t cmp1tag : 3; /* [10:8] */
__IO uint32_t cmp1p : 1; /* [11] */
__IO uint32_t cmp1hyst : 2; /* [13:12] */
__IO uint32_t cmp1value : 1; /* [14] */
__IO uint32_t cmp1wp : 1; /* [15] */
__IO uint32_t cmp2en : 1; /* [16] */
__IO uint32_t reserved3 : 1; /* [17] */
__IO uint32_t cmp2ssel : 1; /* [18] */
__IO uint32_t reserved4 : 1; /* [19] */
__IO uint32_t cmp2invsel : 3; /* [22:20] */
__IO uint32_t dcmpen : 1; /* [23] */
__IO uint32_t cmp2tag : 3; /* [26:24] */
__IO uint32_t cmp2p : 1; /* [27] */
__IO uint32_t cmp2hyst : 2; /* [29:28] */
__IO uint32_t cmp2value : 1; /* [30] */
__IO uint32_t cmp2wp : 1; /* [31] */
} ctrlsts1_bit;
};
/**
* @brief cmp control and status register2, offset:0x04
*/
union
{
__IO uint32_t ctrlsts2;
struct
{
__IO uint32_t cmp1ninvsel : 2; /* [1:0] */
__IO uint32_t reserved1 : 14;/* [15:2] */
__IO uint32_t cmp2ninvsel : 2; /* [17:16] */
__IO uint32_t reserved2 : 14;/* [31:18] */
} ctrlsts2_bit;
};
} cmp_type;
/**
* @}
*/
#define CMP ((cmp_type *) (CMP_BASE))
/** @defgroup CMP_exported_functions
* @{
*/
void cmp_reset(void);
void cmp_init(cmp_sel_type cmp_sel, cmp_init_type* cmp_init_struct);
void cmp_default_para_init(cmp_init_type *cmp_init_struct);
void cmp_enable(cmp_sel_type cmp_sel, confirm_state new_state);
void cmp_input_shift_enable(confirm_state new_state);
uint32_t cmp_output_value_get(cmp_sel_type cmp_sel);
void cmp_write_protect_enable(cmp_sel_type cmp_sel);
void cmp_double_mode_enable(confirm_state new_state);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f415_crc.h
* @brief at32f415 crc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_CRC_H
#define __AT32F415_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @defgroup CRC_exported_types
* @{
*/
/**
* @brief crc reverse input data
*/
typedef enum
{
CRC_REVERSE_INPUT_NO_AFFECTE = 0x00, /*!< input data no reverse */
CRC_REVERSE_INPUT_BY_BYTE = 0x01, /*!< input data reverse by byte */
CRC_REVERSE_INPUT_BY_HALFWORD = 0x02, /*!< input data reverse by half word */
CRC_REVERSE_INPUT_BY_WORD = 0x03 /*!< input data reverse by word */
} crc_reverse_input_type;
/**
* @brief crc reverse output data
*/
typedef enum
{
CRC_REVERSE_OUTPUT_NO_AFFECTE = 0x00, /*!< output data no reverse */
CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */
} crc_reverse_output_type;
/**
* @brief crc polynomial size
*/
typedef enum
{
CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */
CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */
CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */
CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */
} crc_poly_size_type;
/**
* @brief type define crc register all
*/
typedef struct
{
/**
* @brief crc dt register, offset:0x00
*/
union
{
__IO uint32_t dt;
struct
{
__IO uint32_t dt : 32; /* [31:0] */
} dt_bit;
};
/**
* @brief crc cdt register, offset:0x04
*/
union
{
__IO uint32_t cdt;
struct
{
__IO uint32_t cdt : 8 ; /* [7:0] */
__IO uint32_t reserved1 : 24 ;/* [31:8] */
} cdt_bit;
};
/**
* @brief crc ctrl register, offset:0x08
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t rst : 1 ; /* [0] */
__IO uint32_t reserved1 : 2 ; /* [2:1] */
__IO uint32_t poly_size : 2 ; /* [4:3] */
__IO uint32_t revid : 2 ; /* [6:5] */
__IO uint32_t revod : 1 ; /* [7] */
__IO uint32_t reserved2 : 24 ;/* [31:8] */
} ctrl_bit;
};
/**
* @brief crm reserved1 register, offset:0x0C
*/
__IO uint32_t reserved1;
/**
* @brief crc idt register, offset:0x10
*/
union
{
__IO uint32_t idt;
struct
{
__IO uint32_t idt : 32; /* [31:0] */
} idt_bit;
};
/**
* @brief crc polynomial register, offset:0x14
*/
union
{
__IO uint32_t poly;
struct
{
__IO uint32_t poly : 32; /* [31:0] */
} poly_bit;
};
} crc_type;
/**
* @}
*/
#define CRC ((crc_type *) CRC_BASE)
/** @defgroup CRC_exported_functions
* @{
*/
void crc_data_reset(void);
uint32_t crc_one_word_calculate(uint32_t data);
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
uint32_t crc_data_get(void);
void crc_common_data_set(uint8_t cdt_value);
uint8_t crc_common_data_get(void);
void crc_init_data_set(uint32_t value);
void crc_reverse_input_data_set(crc_reverse_input_type value);
void crc_reverse_output_data_set(crc_reverse_output_type value);
void crc_poly_value_set(uint32_t value);
uint32_t crc_poly_value_get(void);
void crc_poly_size_set(crc_poly_size_type size);
crc_poly_size_type crc_poly_size_get(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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libraries/drivers/inc/at32f415_crm.h Normal file
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/**
**************************************************************************
* @file at32f415_crm.h
* @brief at32f415 crm header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_CRM_H
#define __AT32F415_CRM_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup CRM
* @{
*/
#define CRM_REG(value) PERIPH_REG(CRM_BASE, value)
#define CRM_REG_BIT(value) PERIPH_REG_BIT(value)
/** @defgroup CRM_flags_definition
* @brief crm flag
* @{
*/
#define CRM_HICK_STABLE_FLAG MAKE_VALUE(0x00, 1) /*!< high speed internal clock stable flag */
#define CRM_HEXT_STABLE_FLAG MAKE_VALUE(0x00, 17) /*!< high speed external crystal stable flag */
#define CRM_PLL_STABLE_FLAG MAKE_VALUE(0x00, 25) /*!< phase locking loop stable flag */
#define CRM_LEXT_STABLE_FLAG MAKE_VALUE(0x20, 1) /*!< low speed external crystal stable flag */
#define CRM_LICK_STABLE_FLAG MAKE_VALUE(0x24, 1) /*!< low speed internal clock stable flag */
#define CRM_ALL_RESET_FLAG MAKE_VALUE(0x24, 24) /*!< all reset flag */
#define CRM_NRST_RESET_FLAG MAKE_VALUE(0x24, 26) /*!< nrst pin reset flag */
#define CRM_POR_RESET_FLAG MAKE_VALUE(0x24, 27) /*!< power on reset flag */
#define CRM_SW_RESET_FLAG MAKE_VALUE(0x24, 28) /*!< software reset flag */
#define CRM_WDT_RESET_FLAG MAKE_VALUE(0x24, 29) /*!< watchdog timer reset flag */
#define CRM_WWDT_RESET_FLAG MAKE_VALUE(0x24, 30) /*!< window watchdog timer reset flag */
#define CRM_LOWPOWER_RESET_FLAG MAKE_VALUE(0x24, 31) /*!< low-power reset flag */
#define CRM_LICK_READY_INT_FLAG MAKE_VALUE(0x08, 0) /*!< low speed internal clock stable interrupt ready flag */
#define CRM_LEXT_READY_INT_FLAG MAKE_VALUE(0x08, 1) /*!< low speed external crystal stable interrupt ready flag */
#define CRM_HICK_READY_INT_FLAG MAKE_VALUE(0x08, 2) /*!< high speed internal clock stable interrupt ready flag */
#define CRM_HEXT_READY_INT_FLAG MAKE_VALUE(0x08, 3) /*!< high speed external crystal stable interrupt ready flag */
#define CRM_PLL_READY_INT_FLAG MAKE_VALUE(0x08, 4) /*!< phase locking loop stable interrupt ready flag */
#define CRM_CLOCK_FAILURE_INT_FLAG MAKE_VALUE(0x08, 7) /*!< clock failure interrupt ready flag */
/**
* @}
*/
/** @defgroup CRM_interrupts_definition
* @brief crm interrupt
* @{
*/
#define CRM_LICK_STABLE_INT ((uint32_t)0x00000100) /*!< low speed internal clock stable interrupt */
#define CRM_LEXT_STABLE_INT ((uint32_t)0x00000200) /*!< low speed external crystal stable interrupt */
#define CRM_HICK_STABLE_INT ((uint32_t)0x00000400) /*!< high speed internal clock stable interrupt */
#define CRM_HEXT_STABLE_INT ((uint32_t)0x00000800) /*!< high speed external crystal stable interrupt */
#define CRM_PLL_STABLE_INT ((uint32_t)0x00001000) /*!< phase locking loop stable interrupt */
#define CRM_CLOCK_FAILURE_INT ((uint32_t)0x00800000) /*!< clock failure interrupt */
/**
* @}
*/
/** @defgroup CRM_exported_types
* @{
*/
/**
* @brief crm periph clock
*/
typedef enum
{
/* ahb periph */
CRM_DMA1_PERIPH_CLOCK = MAKE_VALUE(0x14, 0), /*!< dma1 periph clock */
CRM_DMA2_PERIPH_CLOCK = MAKE_VALUE(0x14, 1), /*!< dma2 periph clock */
CRM_CRC_PERIPH_CLOCK = MAKE_VALUE(0x14, 6), /*!< crc periph clock */
CRM_SDIO1_PERIPH_CLOCK = MAKE_VALUE(0x14, 10), /*!< sdio1 periph clock */
CRM_OTGFS1_PERIPH_CLOCK = MAKE_VALUE(0x14, 12), /*!< otgfs1 periph clock */
/* apb2 periph */
CRM_IOMUX_PERIPH_CLOCK = MAKE_VALUE(0x18, 0), /*!< iomux periph clock */
CRM_GPIOA_PERIPH_CLOCK = MAKE_VALUE(0x18, 2), /*!< gpioa periph clock */
CRM_GPIOB_PERIPH_CLOCK = MAKE_VALUE(0x18, 3), /*!< gpiob periph clock */
CRM_GPIOC_PERIPH_CLOCK = MAKE_VALUE(0x18, 4), /*!< gpioc periph clock */
CRM_GPIOD_PERIPH_CLOCK = MAKE_VALUE(0x18, 5), /*!< gpiod periph clock */
CRM_GPIOF_PERIPH_CLOCK = MAKE_VALUE(0x18, 7), /*!< gpiof periph clock */
CRM_ADC1_PERIPH_CLOCK = MAKE_VALUE(0x18, 9), /*!< adc1 periph clock */
CRM_TMR1_PERIPH_CLOCK = MAKE_VALUE(0x18, 11), /*!< tmr1 periph clock */
CRM_SPI1_PERIPH_CLOCK = MAKE_VALUE(0x18, 12), /*!< spi1 periph clock */
CRM_USART1_PERIPH_CLOCK = MAKE_VALUE(0x18, 14), /*!< usart1 periph clock */
CRM_TMR9_PERIPH_CLOCK = MAKE_VALUE(0x18, 19), /*!< tmr9 periph clock */
CRM_TMR10_PERIPH_CLOCK = MAKE_VALUE(0x18, 20), /*!< tmr10 periph clock */
CRM_TMR11_PERIPH_CLOCK = MAKE_VALUE(0x18, 21), /*!< tmr11 periph clock */
/* apb1 periph */
CRM_TMR2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 0), /*!< tmr2 periph clock */
CRM_TMR3_PERIPH_CLOCK = MAKE_VALUE(0x1C, 1), /*!< tmr3 periph clock */
CRM_TMR4_PERIPH_CLOCK = MAKE_VALUE(0x1C, 2), /*!< tmr4 periph clock */
CRM_TMR5_PERIPH_CLOCK = MAKE_VALUE(0x1C, 3), /*!< tmr5 periph clock */
CRM_CMP_PERIPH_CLOCK = MAKE_VALUE(0x1C, 9), /*!< cmparator periph clock */
CRM_WWDT_PERIPH_CLOCK = MAKE_VALUE(0x1C, 11), /*!< wwdt periph clock */
CRM_SPI2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 14), /*!< spi2 periph clock */
CRM_USART2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 17), /*!< usart2 periph clock */
CRM_USART3_PERIPH_CLOCK = MAKE_VALUE(0x1C, 18), /*!< usart3 periph clock */
CRM_UART4_PERIPH_CLOCK = MAKE_VALUE(0x1C, 19), /*!< uart4 periph clock */
CRM_UART5_PERIPH_CLOCK = MAKE_VALUE(0x1C, 20), /*!< uart5 periph clock */
CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 21), /*!< i2c1 periph clock */
CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 22), /*!< i2c2 periph clock */
CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 25), /*!< can1 periph clock */
CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28) /*!< pwc periph clock */
} crm_periph_clock_type;
/**
* @brief crm periph reset
*/
typedef enum
{
/* ahb periph */
CRM_OTGFS1_PERIPH_RESET = MAKE_VALUE(0x28, 12), /*!< otgfs1 periph reset */
/* apb2 periph */
CRM_IOMUX_PERIPH_RESET = MAKE_VALUE(0x0C, 0), /*!< iomux periph reset */
CRM_EXINT_PERIPH_RESET = MAKE_VALUE(0x0C, 1), /*!< exint periph reset */
CRM_GPIOA_PERIPH_RESET = MAKE_VALUE(0x0C, 2), /*!< gpioa periph reset */
CRM_GPIOB_PERIPH_RESET = MAKE_VALUE(0x0C, 3), /*!< gpiob periph reset */
CRM_GPIOC_PERIPH_RESET = MAKE_VALUE(0x0C, 4), /*!< gpioc periph reset */
CRM_GPIOD_PERIPH_RESET = MAKE_VALUE(0x0C, 5), /*!< gpiod periph reset */
CRM_GPIOF_PERIPH_RESET = MAKE_VALUE(0x0C, 7), /*!< gpiof periph reset */
CRM_ADC1_PERIPH_RESET = MAKE_VALUE(0x0C, 9), /*!< adc1 periph reset */
CRM_TMR1_PERIPH_RESET = MAKE_VALUE(0x0C, 11), /*!< tmr1 periph reset */
CRM_SPI1_PERIPH_RESET = MAKE_VALUE(0x0C, 12), /*!< spi2 periph reset */
CRM_USART1_PERIPH_RESET = MAKE_VALUE(0x0C, 14), /*!< usart1 periph reset */
CRM_TMR9_PERIPH_RESET = MAKE_VALUE(0x0C, 19), /*!< tmr9 periph reset */
CRM_TMR10_PERIPH_RESET = MAKE_VALUE(0x0C, 20), /*!< tmr10 periph reset */
CRM_TMR11_PERIPH_RESET = MAKE_VALUE(0x0C, 21), /*!< tmr11 periph reset */
/* apb1 periph */
CRM_TMR2_PERIPH_RESET = MAKE_VALUE(0x10, 0), /*!< tmr2 periph reset */
CRM_TMR3_PERIPH_RESET = MAKE_VALUE(0x10, 1), /*!< tmr3 periph reset */
CRM_TMR4_PERIPH_RESET = MAKE_VALUE(0x10, 2), /*!< tmr4 periph reset */
CRM_TMR5_PERIPH_RESET = MAKE_VALUE(0x10, 3), /*!< tmr5 periph reset */
CRM_CMP_PERIPH_RESET = MAKE_VALUE(0x10, 9), /*!< comparator periph reset */
CRM_WWDT_PERIPH_RESET = MAKE_VALUE(0x10, 11), /*!< wwdt periph reset */
CRM_SPI2_PERIPH_RESET = MAKE_VALUE(0x10, 14), /*!< spi2 periph reset */
CRM_USART2_PERIPH_RESET = MAKE_VALUE(0x10, 17), /*!< usart2 periph reset */
CRM_USART3_PERIPH_RESET = MAKE_VALUE(0x10, 18), /*!< usart3 periph reset */
CRM_UART4_PERIPH_RESET = MAKE_VALUE(0x10, 19), /*!< uart4 periph reset */
CRM_UART5_PERIPH_RESET = MAKE_VALUE(0x10, 20), /*!< uart5 periph reset */
CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x10, 21), /*!< i2c1 periph reset */
CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< i2c2 periph reset */
CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x10, 25), /*!< can1 periph reset */
CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28) /*!< pwc periph reset */
} crm_periph_reset_type;
/**
* @brief crm periph clock in sleep mode
*/
typedef enum
{
/* ahb periph */
CRM_SRAM_PERIPH_CLOCK_SLEEP_MODE = MAKE_VALUE(0x14, 2), /*!< sram sleep mode periph clock */
CRM_FLASH_PERIPH_CLOCK_SLEEP_MODE = MAKE_VALUE(0x14, 4) /*!< flash sleep mode periph clock */
} crm_periph_clock_sleepmd_type;
/**
* @brief crm pll mult_x
*/
typedef enum
{
CRM_PLL_MULT_2 = 0, /*!< pll multiplication factor 2 */
CRM_PLL_MULT_3 = 1, /*!< pll multiplication factor 3 */
CRM_PLL_MULT_4 = 2, /*!< pll multiplication factor 4 */
CRM_PLL_MULT_5 = 3, /*!< pll multiplication factor 5 */
CRM_PLL_MULT_6 = 4, /*!< pll multiplication factor 6 */
CRM_PLL_MULT_7 = 5, /*!< pll multiplication factor 7 */
CRM_PLL_MULT_8 = 6, /*!< pll multiplication factor 8 */
CRM_PLL_MULT_9 = 7, /*!< pll multiplication factor 9 */
CRM_PLL_MULT_10 = 8, /*!< pll multiplication factor 10 */
CRM_PLL_MULT_11 = 9, /*!< pll multiplication factor 11 */
CRM_PLL_MULT_12 = 10, /*!< pll multiplication factor 12 */
CRM_PLL_MULT_13 = 11, /*!< pll multiplication factor 13 */
CRM_PLL_MULT_14 = 12, /*!< pll multiplication factor 14 */
CRM_PLL_MULT_15 = 13, /*!< pll multiplication factor 15 */
CRM_PLL_MULT_16 = 15, /*!< pll multiplication factor 16 */
CRM_PLL_MULT_17 = 16, /*!< pll multiplication factor 17 */
CRM_PLL_MULT_18 = 17, /*!< pll multiplication factor 18 */
CRM_PLL_MULT_19 = 18, /*!< pll multiplication factor 19 */
CRM_PLL_MULT_20 = 19, /*!< pll multiplication factor 20 */
CRM_PLL_MULT_21 = 20, /*!< pll multiplication factor 21 */
CRM_PLL_MULT_22 = 21, /*!< pll multiplication factor 22 */
CRM_PLL_MULT_23 = 22, /*!< pll multiplication factor 23 */
CRM_PLL_MULT_24 = 23, /*!< pll multiplication factor 24 */
CRM_PLL_MULT_25 = 24, /*!< pll multiplication factor 25 */
CRM_PLL_MULT_26 = 25, /*!< pll multiplication factor 26 */
CRM_PLL_MULT_27 = 26, /*!< pll multiplication factor 27 */
CRM_PLL_MULT_28 = 27, /*!< pll multiplication factor 28 */
CRM_PLL_MULT_29 = 28, /*!< pll multiplication factor 29 */
CRM_PLL_MULT_30 = 29, /*!< pll multiplication factor 30 */
CRM_PLL_MULT_31 = 30, /*!< pll multiplication factor 31 */
CRM_PLL_MULT_32 = 31, /*!< pll multiplication factor 32 */
CRM_PLL_MULT_33 = 32, /*!< pll multiplication factor 33 */
CRM_PLL_MULT_34 = 33, /*!< pll multiplication factor 34 */
CRM_PLL_MULT_35 = 34, /*!< pll multiplication factor 35 */
CRM_PLL_MULT_36 = 35, /*!< pll multiplication factor 36 */
CRM_PLL_MULT_37 = 36, /*!< pll multiplication factor 37 */
CRM_PLL_MULT_38 = 37, /*!< pll multiplication factor 38 */
CRM_PLL_MULT_39 = 38, /*!< pll multiplication factor 39 */
CRM_PLL_MULT_40 = 39, /*!< pll multiplication factor 40 */
CRM_PLL_MULT_41 = 40, /*!< pll multiplication factor 41 */
CRM_PLL_MULT_42 = 41, /*!< pll multiplication factor 42 */
CRM_PLL_MULT_43 = 42, /*!< pll multiplication factor 43 */
CRM_PLL_MULT_44 = 43, /*!< pll multiplication factor 44 */
CRM_PLL_MULT_45 = 44, /*!< pll multiplication factor 45 */
CRM_PLL_MULT_46 = 45, /*!< pll multiplication factor 46 */
CRM_PLL_MULT_47 = 46, /*!< pll multiplication factor 47 */
CRM_PLL_MULT_48 = 47, /*!< pll multiplication factor 48 */
CRM_PLL_MULT_49 = 48, /*!< pll multiplication factor 49 */
CRM_PLL_MULT_50 = 49, /*!< pll multiplication factor 50 */
CRM_PLL_MULT_51 = 50, /*!< pll multiplication factor 51 */
CRM_PLL_MULT_52 = 51, /*!< pll multiplication factor 52 */
CRM_PLL_MULT_53 = 52, /*!< pll multiplication factor 53 */
CRM_PLL_MULT_54 = 53, /*!< pll multiplication factor 54 */
CRM_PLL_MULT_55 = 54, /*!< pll multiplication factor 55 */
CRM_PLL_MULT_56 = 55, /*!< pll multiplication factor 56 */
CRM_PLL_MULT_57 = 56, /*!< pll multiplication factor 57 */
CRM_PLL_MULT_58 = 57, /*!< pll multiplication factor 58 */
CRM_PLL_MULT_59 = 58, /*!< pll multiplication factor 59 */
CRM_PLL_MULT_60 = 59, /*!< pll multiplication factor 60 */
CRM_PLL_MULT_61 = 60, /*!< pll multiplication factor 61 */
CRM_PLL_MULT_62 = 61, /*!< pll multiplication factor 62 */
CRM_PLL_MULT_63 = 62, /*!< pll multiplication factor 63 */
CRM_PLL_MULT_64 = 63 /*!< pll multiplication factor 64 */
} crm_pll_mult_type;
/**
* @brief crm pll fref_x
*/
typedef enum
{
CRM_PLL_FREF_4M = 0, /*!< pll refrence clock between 3.9 mhz and 5 mhz */
CRM_PLL_FREF_6M = 1, /*!< pll refrence clock between 5.2 mhz and 6.25 mhz */
CRM_PLL_FREF_8M = 2, /*!< pll refrence clock between 7.8125 mhz and 8.33 mhz */
CRM_PLL_FREF_12M = 3, /*!< pll refrence clock between 8.33 mhz and 12.5 mhz */
CRM_PLL_FREF_16M = 4, /*!< pll refrence clock between 15.625 mhz and 20.83 mhz */
CRM_PLL_FREF_25M = 5 /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */
} crm_pll_fref_type;
/**
* @brief crm pll clock source
*/
typedef enum
{
CRM_PLL_SOURCE_HICK = 0x00, /*!< high speed internal clock as pll reference clock source */
CRM_PLL_SOURCE_HEXT = 0x01, /*!< high speed external crystal as pll reference clock source */
CRM_PLL_SOURCE_HEXT_DIV = 0x02 /*!< high speed external crystal div as pll reference clock source */
} crm_pll_clock_source_type;
/**
* @brief crm pll fr
*/
typedef enum
{
CRM_PLL_FR_1 = 0x00, /*!< pll post-division div1 */
CRM_PLL_FR_2 = 0x01, /*!< pll post-division div2 */
CRM_PLL_FR_4 = 0x02, /*!< pll post-division div4 */
CRM_PLL_FR_8 = 0x03, /*!< pll post-division div8 */
CRM_PLL_FR_16 = 0x04, /*!< pll post-division div16 */
CRM_PLL_FR_32 = 0x05 /*!< pll post-division div32 */
} crm_pll_fr_type;
/**
* @brief crm clock source
*/
typedef enum
{
CRM_CLOCK_SOURCE_HICK = 0x00, /*!< high speed internal clock */
CRM_CLOCK_SOURCE_HEXT = 0x01, /*!< high speed external crystal */
CRM_CLOCK_SOURCE_PLL = 0x02, /*!< phase locking loop */
CRM_CLOCK_SOURCE_LEXT = 0x03, /*!< low speed external crystal */
CRM_CLOCK_SOURCE_LICK = 0x04 /*!< low speed internal clock */
} crm_clock_source_type;
/**
* @brief crm ahb division
*/
typedef enum
{
CRM_AHB_DIV_1 = 0x00, /*!< sclk div1 to ahbclk */
CRM_AHB_DIV_2 = 0x08, /*!< sclk div2 to ahbclk */
CRM_AHB_DIV_4 = 0x09, /*!< sclk div4 to ahbclk */
CRM_AHB_DIV_8 = 0x0A, /*!< sclk div8 to ahbclk */
CRM_AHB_DIV_16 = 0x0B, /*!< sclk div16 to ahbclk */
CRM_AHB_DIV_64 = 0x0C, /*!< sclk div64 to ahbclk */
CRM_AHB_DIV_128 = 0x0D, /*!< sclk div128 to ahbclk */
CRM_AHB_DIV_256 = 0x0E, /*!< sclk div256 to ahbclk */
CRM_AHB_DIV_512 = 0x0F /*!< sclk div512 to ahbclk */
} crm_ahb_div_type;
/**
* @brief crm apb1 division
*/
typedef enum
{
CRM_APB1_DIV_1 = 0x00, /*!< ahbclk div1 to apb1clk */
CRM_APB1_DIV_2 = 0x04, /*!< ahbclk div2 to apb1clk */
CRM_APB1_DIV_4 = 0x05, /*!< ahbclk div4 to apb1clk */
CRM_APB1_DIV_8 = 0x06, /*!< ahbclk div8 to apb1clk */
CRM_APB1_DIV_16 = 0x07 /*!< ahbclk div16 to apb1clk */
} crm_apb1_div_type;
/**
* @brief crm apb2 division
*/
typedef enum
{
CRM_APB2_DIV_1 = 0x00, /*!< ahbclk div1 to apb2clk */
CRM_APB2_DIV_2 = 0x04, /*!< ahbclk div2 to apb2clk */
CRM_APB2_DIV_4 = 0x05, /*!< ahbclk div4 to apb2clk */
CRM_APB2_DIV_8 = 0x06, /*!< ahbclk div8 to apb2clk */
CRM_APB2_DIV_16 = 0x07 /*!< ahbclk div16 to apb2clk */
} crm_apb2_div_type;
/**
* @brief crm adc division
*/
typedef enum
{
CRM_ADC_DIV_2 = 0x00, /*!< apb2clk div2 to adcclk */
CRM_ADC_DIV_4 = 0x01, /*!< apb2clk div4 to adcclk */
CRM_ADC_DIV_6 = 0x02, /*!< apb2clk div6 to adcclk */
CRM_ADC_DIV_8 = 0x03, /*!< apb2clk div8 to adcclk */
CRM_ADC_DIV_12 = 0x05, /*!< apb2clk div12 to adcclk */
CRM_ADC_DIV_16 = 0x07 /*!< apb2clk div16 to adcclk */
} crm_adc_div_type;
/**
* @brief crm usb division
*/
typedef enum
{
CRM_USB_DIV_1_5 = 0x00, /*!< pllclk div1.5 to usbclk */
CRM_USB_DIV_1 = 0x01, /*!< pllclk div1 to usbclk */
CRM_USB_DIV_2_5 = 0x02, /*!< pllclk div2.5 to usbclk */
CRM_USB_DIV_2 = 0x03, /*!< pllclk div2 to usbclk */
CRM_USB_DIV_3_5 = 0x04, /*!< pllclk div3.5 to usbclk */
CRM_USB_DIV_3 = 0x05, /*!< pllclk div3 to usbclk */
CRM_USB_DIV_4 = 0x06 /*!< pllclk div4 to usbclk */
} crm_usb_div_type;
/**
* @brief crm ertc clock
*/
typedef enum
{
CRM_ERTC_CLOCK_NOCLK = 0x00, /*!< no clock as ertc clock source */
CRM_ERTC_CLOCK_LEXT = 0x01, /*!< low speed external crystal as ertc clock source */
CRM_ERTC_CLOCK_LICK = 0x02, /*!< low speed internal clock as ertc clock source */
CRM_ERTC_CLOCK_HEXT_DIV = 0x03 /*!< high speed external crystal div as ertc clock source */
} crm_ertc_clock_type;
/**
* @brief crm hick 48mhz division
*/
typedef enum
{
CRM_HICK48_DIV6 = 0x00, /*!< high speed internal clock (48 mhz) div6 */
CRM_HICK48_NODIV = 0x01 /*!< high speed internal clock (48 mhz) no div */
} crm_hick_div_6_type;
/**
* @brief crm sclk select
*/
typedef enum
{
CRM_SCLK_HICK = 0x00, /*!< select high speed internal clock as sclk */
CRM_SCLK_HEXT = 0x01, /*!< select high speed external crystal as sclk */
CRM_SCLK_PLL = 0x02 /*!< select phase locking loop clock as sclk */
} crm_sclk_type;
/**
* @brief crm clkout select
*/
typedef enum
{
CRM_CLKOUT_NOCLK = 0x00, /*!< output no clock to clkout pin */
CRM_CLKOUT_LICK = 0x02, /*!< output low speed internal clock to clkout pin */
CRM_CLKOUT_LEXT = 0x03, /*!< output low speed external crystal to clkout pin */
CRM_CLKOUT_SCLK = 0x04, /*!< output system clock to clkout pin */
CRM_CLKOUT_HICK = 0x05, /*!< output high speed internal clock to clkout pin */
CRM_CLKOUT_HEXT = 0x06, /*!< output high speed external crystal to clkout pin */
CRM_CLKOUT_PLL_DIV_2 = 0x07, /*!< output phase locking loop clock div2 to clkout pin */
CRM_CLKOUT_PLL_DIV_4 = 0x0C, /*!< output phase locking loop clock div4 to clkout pin */
CRM_CLKOUT_USB = 0x0D, /*!< output usbclk to clkout pin */
CRM_CLKOUT_ADC = 0x0E /*!< output adcclk to clkout pin */
} crm_clkout_select_type;
/**
* @brief crm clkout division
*/
typedef enum
{
CRM_CLKOUT_DIV_1 = 0x00, /*!< clkout div1 */
CRM_CLKOUT_DIV_2 = 0x08, /*!< clkout div2 */
CRM_CLKOUT_DIV_4 = 0x09, /*!< clkout div4 */
CRM_CLKOUT_DIV_8 = 0x0A, /*!< clkout div8 */
CRM_CLKOUT_DIV_16 = 0x0B, /*!< clkout div16 */
CRM_CLKOUT_DIV_64 = 0x0C, /*!< clkout div64 */
CRM_CLKOUT_DIV_128 = 0x0D, /*!< clkout div128 */
CRM_CLKOUT_DIV_256 = 0x0E, /*!< clkout div256 */
CRM_CLKOUT_DIV_512 = 0x0F /*!< clkout div512 */
} crm_clkout_div_type;
/**
* @brief crm auto step mode
*/
typedef enum
{
CRM_AUTO_STEP_MODE_DISABLE = 0x00, /*!< disable auto step mode */
CRM_AUTO_STEP_MODE_ENABLE = 0x03 /*!< enable auto step mode */
} crm_auto_step_mode_type;
/**
* @brief crm usb 48 mhz clock source select
*/
typedef enum
{
CRM_USB_CLOCK_SOURCE_PLL = 0x00, /*!< select phase locking loop clock as usb clock source */
CRM_USB_CLOCK_SOURCE_HICK = 0x01 /*!< select high speed internal clock as usb clock source */
} crm_usb_clock_source_type;
/**
* @brief crm hick as system clock frequency select
*/
typedef enum
{
CRM_HICK_SCLK_8MHZ = 0x00, /*!< fixed 8 mhz when hick is selected as sclk */
CRM_HICK_SCLK_48MHZ = 0x01 /*!< 8 mhz or 48 mhz depend on hickdiv when hick is selected as sclk */
} crm_hick_sclk_frequency_type;
/**
* @brief crm clocks freqency structure
*/
typedef struct
{
uint32_t sclk_freq; /*!< system clock frequency */
uint32_t ahb_freq; /*!< ahb bus clock frequency */
uint32_t apb2_freq; /*!< apb2 bus clock frequency */
uint32_t apb1_freq; /*!< apb1 bus clock frequency */
uint32_t adc_freq; /*!< adc clock frequency */
} crm_clocks_freq_type;
/**
* @brief type define crm register all
*/
typedef struct
{
/**
* @brief crm ctrl register, offset:0x00
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t hicken : 1; /* [0] */
__IO uint32_t hickstbl : 1; /* [1] */
__IO uint32_t hicktrim : 6; /* [7:2] */
__IO uint32_t hickcal : 8; /* [15:8] */
__IO uint32_t hexten : 1; /* [16] */
__IO uint32_t hextstbl : 1; /* [17] */
__IO uint32_t hextbyps : 1; /* [18] */
__IO uint32_t cfden : 1; /* [19] */
__IO uint32_t reserved1 : 4; /* [23:20] */
__IO uint32_t pllen : 1; /* [24] */
__IO uint32_t pllstbl : 1; /* [25] */
__IO uint32_t reserved2 : 6; /* [31:26] */
} ctrl_bit;
};
/**
* @brief crm cfg register, offset:0x04
*/
union
{
__IO uint32_t cfg;
struct
{
__IO uint32_t sclksel : 2; /* [1:0] */
__IO uint32_t sclksts : 2; /* [3:2] */
__IO uint32_t ahbdiv : 4; /* [7:4] */
__IO uint32_t apb1div : 3; /* [10:8] */
__IO uint32_t apb2div : 3; /* [13:11] */
__IO uint32_t adcdiv_l : 2; /* [15:14] */
__IO uint32_t pllrcs : 1; /* [16] */
__IO uint32_t pllhextdiv : 1; /* [17] */
__IO uint32_t pllmult_l : 4; /* [21:18] */
__IO uint32_t usbdiv_l : 2; /* [23:22] */
__IO uint32_t clkout_sel : 3; /* [26:24] */
__IO uint32_t usbdiv_h : 1; /* [27] */
__IO uint32_t adcdiv_h : 1; /* [28] */
__IO uint32_t pllmult_h : 2; /* [30:29] */
__IO uint32_t reserved1 : 1; /* [31] */
} cfg_bit;
};
/**
* @brief crm clkint register, offset:0x08
*/
union
{
__IO uint32_t clkint;
struct
{
__IO uint32_t lickstblf : 1; /* [0] */
__IO uint32_t lextstblf : 1; /* [1] */
__IO uint32_t hickstblf : 1; /* [2] */
__IO uint32_t hextstblf : 1; /* [3] */
__IO uint32_t pllstblf : 1; /* [4] */
__IO uint32_t reserved1 : 2; /* [6:5] */
__IO uint32_t cfdf : 1; /* [7] */
__IO uint32_t lickstblien : 1; /* [8] */
__IO uint32_t lextstblien : 1; /* [9] */
__IO uint32_t hickstblien : 1; /* [10] */
__IO uint32_t hextstblien : 1; /* [11] */
__IO uint32_t pllstblien : 1; /* [12] */
__IO uint32_t reserved2 : 3; /* [15:13] */
__IO uint32_t lickstblfc : 1; /* [16] */
__IO uint32_t lextstblfc : 1; /* [17] */
__IO uint32_t hickstblfc : 1; /* [18] */
__IO uint32_t hextstblfc : 1; /* [19] */
__IO uint32_t pllstblfc : 1; /* [20] */
__IO uint32_t reserved3 : 2; /* [22:21] */
__IO uint32_t cfdfc : 1; /* [23] */
__IO uint32_t reserved4 : 8; /* [31:24] */
} clkint_bit;
};
/**
* @brief crm apb2rst register, offset:0x0C
*/
union
{
__IO uint32_t apb2rst;
struct
{
__IO uint32_t iomuxrst : 1; /* [0] */
__IO uint32_t exintrst : 1; /* [1] */
__IO uint32_t gpioarst : 1; /* [2] */
__IO uint32_t gpiobrst : 1; /* [3] */
__IO uint32_t gpiocrst : 1; /* [4] */
__IO uint32_t gpiodrst : 1; /* [5] */
__IO uint32_t reserved1 : 1; /* [6] */
__IO uint32_t gpiofrst : 1; /* [7] */
__IO uint32_t reserved2 : 1; /* [8] */
__IO uint32_t adc1rst : 1; /* [9] */
__IO uint32_t reserved3 : 1; /* [10] */
__IO uint32_t tmr1rst : 1; /* [11] */
__IO uint32_t spi1rst : 1; /* [12] */
__IO uint32_t reserved4 : 1; /* [13] */
__IO uint32_t usart1rst : 1; /* [14] */
__IO uint32_t reserved5 : 4; /* [18:15] */
__IO uint32_t tmr9rst : 1; /* [19] */
__IO uint32_t tmr10rst : 1; /* [20] */
__IO uint32_t tmr11rst : 1; /* [21] */
__IO uint32_t reserved6 : 10;/* [31:22] */
} apb2rst_bit;
};
/**
* @brief crm apb1rst register, offset:0x10
*/
union
{
__IO uint32_t apb1rst;
struct
{
__IO uint32_t tmr2rst : 1; /* [0] */
__IO uint32_t tmr3rst : 1; /* [1] */
__IO uint32_t tmr4rst : 1; /* [2] */
__IO uint32_t tmr5rst : 1; /* [3] */
__IO uint32_t reserved1 : 5; /* [8:4] */
__IO uint32_t cmprst : 1; /* [9] */
__IO uint32_t reserved2 : 1; /* [10] */
__IO uint32_t wwdtrst : 1; /* [11] */
__IO uint32_t reserved3 : 2; /* [13:12] */
__IO uint32_t spi2rst : 1; /* [14] */
__IO uint32_t reserved4 : 2; /* [16:15] */
__IO uint32_t usart2rst : 1; /* [17] */
__IO uint32_t usart3rst : 1; /* [18] */
__IO uint32_t uart4rst : 1; /* [19] */
__IO uint32_t uart5rst : 1; /* [20] */
__IO uint32_t i2c1rst : 1; /* [21] */
__IO uint32_t i2c2rst : 1; /* [22] */
__IO uint32_t reserved5 : 2; /* [24:23] */
__IO uint32_t can1rst : 1; /* [25] */
__IO uint32_t reserved6 : 2; /* [27:26] */
__IO uint32_t pwcrst : 1; /* [28] */
__IO uint32_t reserved7 : 3; /* [31:29] */
} apb1rst_bit;
};
/**
* @brief crm ahben register, offset:0x14
*/
union
{
__IO uint32_t ahben;
struct
{
__IO uint32_t dma1en : 1; /* [0] */
__IO uint32_t dma2en : 1; /* [1] */
__IO uint32_t sramen : 1; /* [2] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t flashen : 1; /* [4] */
__IO uint32_t reserved2 : 1; /* [5] */
__IO uint32_t crcen : 1; /* [6] */
__IO uint32_t reserved3 : 3; /* [9:7] */
__IO uint32_t sdio1en : 1; /* [10] */
__IO uint32_t reserved4 : 1; /* [11] */
__IO uint32_t usben : 1; /* [12] */
__IO uint32_t reserved5 : 19;/* [31:13] */
} ahben_bit;
};
/**
* @brief crm apb2en register, offset:0x18
*/
union
{
__IO uint32_t apb2en;
struct
{
__IO uint32_t iomuxen : 1; /* [0] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t gpioaen : 1; /* [2] */
__IO uint32_t gpioben : 1; /* [3] */
__IO uint32_t gpiocen : 1; /* [4] */
__IO uint32_t gpioden : 1; /* [5] */
__IO uint32_t reserved2 : 1; /* [6] */
__IO uint32_t gpiofen : 1; /* [7] */
__IO uint32_t reserved3 : 1; /* [8] */
__IO uint32_t adc1en : 1; /* [9] */
__IO uint32_t reserved4 : 1; /* [10] */
__IO uint32_t tmr1en : 1; /* [11] */
__IO uint32_t spi1en : 1; /* [12] */
__IO uint32_t reserved5 : 1; /* [13] */
__IO uint32_t usart1en : 1; /* [14] */
__IO uint32_t reserved6 : 4; /* [18:15] */
__IO uint32_t tmr9en : 1; /* [19] */
__IO uint32_t tmr10en : 1; /* [20] */
__IO uint32_t tmr11en : 1; /* [21] */
__IO uint32_t reserved7 : 10;/* [31:22] */
} apb2en_bit;
};
/**
* @brief crm apb1en register, offset:0x1C
*/
union
{
__IO uint32_t apb1en;
struct
{
__IO uint32_t tmr2en : 1; /* [0] */
__IO uint32_t tmr3en : 1; /* [1] */
__IO uint32_t tmr4en : 1; /* [2] */
__IO uint32_t tmr5en : 1; /* [3] */
__IO uint32_t reserved1 : 5; /* [8:4] */
__IO uint32_t cmpen : 1; /* [9] */
__IO uint32_t reserved2 : 1; /* [10] */
__IO uint32_t wwdten : 1; /* [11] */
__IO uint32_t reserved3 : 2; /* [13:12] */
__IO uint32_t spi2en : 1; /* [14] */
__IO uint32_t reserved4 : 2; /* [16:15] */
__IO uint32_t usart2en : 1; /* [17] */
__IO uint32_t usart3en : 1; /* [18] */
__IO uint32_t uart4en : 1; /* [19] */
__IO uint32_t uart5en : 1; /* [20] */
__IO uint32_t i2c1en : 1; /* [21] */
__IO uint32_t i2c2en : 1; /* [22] */
__IO uint32_t reserved5 : 2; /* [24:23] */
__IO uint32_t can1en : 1; /* [25] */
__IO uint32_t reserved6 : 1; /* [26] */
__IO uint32_t bpren : 1; /* [27] */
__IO uint32_t pwcen : 1; /* [28] */
__IO uint32_t reserved7 : 2; /* [31:29] */
} apb1en_bit;
};
/**
* @brief crm bpdc register, offset:0x20
*/
union
{
__IO uint32_t bpdc;
struct
{
__IO uint32_t lexten : 1; /* [0] */
__IO uint32_t lextstbl : 1; /* [1] */
__IO uint32_t lextbyps : 1; /* [2] */
__IO uint32_t reserved1 : 5; /* [7:3] */
__IO uint32_t ertcsel : 2; /* [9:8] */
__IO uint32_t reserved2 : 5; /* [14:10] */
__IO uint32_t ertcen : 1; /* [15] */
__IO uint32_t bpdrst : 1; /* [16] */
__IO uint32_t reserved3 : 15;/* [31:17] */
} bpdc_bit;
};
/**
* @brief crm ctrlsts register, offset:0x24
*/
union
{
__IO uint32_t ctrlsts;
struct
{
__IO uint32_t licken : 1; /* [0] */
__IO uint32_t lickstbl : 1; /* [1] */
__IO uint32_t reserved1 : 22;/* [23:2] */
__IO uint32_t rstfc : 1; /* [24] */
__IO uint32_t reserved2 : 1; /* [25] */
__IO uint32_t nrstf : 1; /* [26] */
__IO uint32_t porrstf : 1; /* [27] */
__IO uint32_t swrstf : 1; /* [28] */
__IO uint32_t wdtrstf : 1; /* [29] */
__IO uint32_t wwdtrstf : 1; /* [30] */
__IO uint32_t lprstf : 1; /* [31] */
} ctrlsts_bit;
};
/**
* @brief crm ahbrst register, offset:0x28
*/
union
{
__IO uint32_t ahbrst;
struct
{
__IO uint32_t reserved1 : 12;/* [11:0] */
__IO uint32_t usbrst : 1; /* [12] */
__IO uint32_t reserved2 : 19;/* [31:13] */
} ahbrst_bit;
};
/**
* @brief crm pll register, offset:0x2C
*/
union
{
__IO uint32_t pll;
struct
{
__IO uint32_t pllfr : 3; /* [2:0] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t pllms : 4; /* [7:4] */
__IO uint32_t pllns : 9; /* [16:8] */
__IO uint32_t reserved2 : 7; /* [23:17] */
__IO uint32_t pllfref : 3; /* [26:24] */
__IO uint32_t reserved3 : 4; /* [30:27] */
__IO uint32_t pllcfgen : 1; /* [31] */
} pll_bit;
};
/**
* @brief crm misc1 register, offset:0x30
*/
union
{
__IO uint32_t misc1;
struct
{
__IO uint32_t hickcal_key : 8; /* [7:0] */
__IO uint32_t reserved1 : 8; /* [15:8] */
__IO uint32_t clkout_sel : 1; /* [16] */
__IO uint32_t reserved2 : 7; /* [23:17] */
__IO uint32_t usbbufs : 1; /* [24] */
__IO uint32_t hickdiv : 1; /* [25] */
__IO uint32_t reserved3 : 2; /* [27:26] */
__IO uint32_t clkoutdiv : 4; /* [31:28] */
} misc1_bit;
};
/**
* @brief crm reserved2 register, offset:0x40~0x34
*/
__IO uint32_t reserved2[4];
/**
* @brief crm otg_extctrl register, offset:0x44
*/
union
{
__IO uint32_t otg_extctrl;
struct
{
__IO uint32_t reserved1 : 30;/* [29:0] */
__IO uint32_t usbdivrst : 1; /* [30] */
__IO uint32_t ep3_rmpen : 1; /* [31] */
} otg_extctrl_bit;
};
/**
* @brief crm reserved3 register, offset:0x50~0x48
*/
__IO uint32_t reserved3[3];
/**
* @brief crm misc2 register, offset:0x54
*/
union
{
__IO uint32_t misc2;
struct
{
__IO uint32_t reserved1 : 4; /* [3:0] */
__IO uint32_t auto_step_en : 2; /* [5:4] */
__IO uint32_t reserved2 : 2; /* [7:6] */
__IO uint32_t hick_to_usb : 1; /* [8] */
__IO uint32_t hick_to_sclk : 1; /* [9] */
__IO uint32_t reserved3 : 22;/* [31:10] */
} misc2_bit;
};
} crm_type;
/**
* @}
*/
#define CRM ((crm_type *) CRM_BASE)
/** @defgroup CRM_exported_functions
* @{
*/
void crm_reset(void);
void crm_lext_bypass(confirm_state new_state);
void crm_hext_bypass(confirm_state new_state);
flag_status crm_flag_get(uint32_t flag);
flag_status crm_interrupt_flag_get(uint32_t flag);
error_status crm_hext_stable_wait(void);
void crm_hick_clock_trimming_set(uint8_t trim_value);
void crm_hick_clock_calibration_set(uint8_t cali_value);
void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state);
void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state);
void crm_periph_sleep_mode_clock_enable(crm_periph_clock_sleepmd_type value, confirm_state new_state);
void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state);
void crm_flag_clear(uint32_t flag);
void crm_ertc_clock_select(crm_ertc_clock_type value);
void crm_ertc_clock_enable(confirm_state new_state);
void crm_ahb_div_set(crm_ahb_div_type value);
void crm_apb1_div_set(crm_apb1_div_type value);
void crm_apb2_div_set(crm_apb2_div_type value);
void crm_adc_clock_div_set(crm_adc_div_type div_value);
void crm_usb_clock_div_set(crm_usb_div_type div_value);
void crm_clock_failure_detection_enable(confirm_state new_state);
void crm_battery_powered_domain_reset(confirm_state new_state);
void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mult_value);
void crm_pll_config2(crm_pll_clock_source_type clock_source, uint16_t pll_ns, uint16_t pll_ms, crm_pll_fr_type pll_fr);
void crm_sysclk_switch(crm_sclk_type value);
crm_sclk_type crm_sysclk_switch_status_get(void);
void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct);
void crm_clock_out_set(crm_clkout_select_type clkout);
void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state);
void crm_auto_step_mode_enable(confirm_state new_state);
void crm_hick_divider_select(crm_hick_div_6_type value);
void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value);
void crm_usb_clock_source_select(crm_usb_clock_source_type value);
void crm_clkout_div_set(crm_clkout_div_type clkout_div);
void crm_otgfs_ep3_remap_enable(confirm_state new_state);
void crm_usbdiv_reset(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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libraries/drivers/inc/at32f415_debug.h Normal file
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/**
**************************************************************************
* @file at32f415_debug.h
* @brief at32f415 debug header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_DEBUG_H
#define __AT32F415_DEBUG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup DEBUG
* @{
*/
/** @defgroup DEBUG_mode_definition
* @{
*/
#define DEBUG_SLEEP ((uint32_t)0x00000001) /*!< debug sleep mode */
#define DEBUG_DEEPSLEEP ((uint32_t)0x00000002) /*!< debug deepsleep mode */
#define DEBUG_STANDBY ((uint32_t)0x00000004) /*!< debug standby mode */
#define DEBUG_WDT_PAUSE ((uint32_t)0x00000100) /*!< debug watchdog timer pause */
#define DEBUG_WWDT_PAUSE ((uint32_t)0x00000200) /*!< debug window watchdog timer pause */
#define DEBUG_TMR1_PAUSE ((uint32_t)0x00000400) /*!< debug timer1 pause */
#define DEBUG_TMR3_PAUSE ((uint32_t)0x00001000) /*!< debug timer3 pause */
#define DEBUG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< debug i2c1 smbus timeout */
#define DEBUG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< debug i2c2 smbus timeout */
#define DEBUG_TMR2_PAUSE ((uint32_t)0x00000800) /*!< debug timer2 pause */
#define DEBUG_TMR4_PAUSE ((uint32_t)0x00002000) /*!< debug timer4 pause */
#define DEBUG_CAN1_PAUSE ((uint32_t)0x00004000) /*!< debug can1 pause */
#define DEBUG_TMR5_PAUSE ((uint32_t)0x00040000) /*!< debug timer5 pause */
#define DEBUG_TMR9_PAUSE ((uint32_t)0x10000000) /*!< debug timer9 pause */
#define DEBUG_TMR10_PAUSE ((uint32_t)0x20000000) /*!< debug timer10 pause */
#define DEBUG_TMR11_PAUSE ((uint32_t)0x40000000) /*!< debug timer11 pause */
/**
* @}
*/
/** @defgroup DEBUG_exported_types
* @{
*/
/**
* @brief type define debug register all
*/
typedef struct
{
/**
* @brief debug idcode register, offset:0x00
*/
union
{
__IO uint32_t pid;
struct
{
__IO uint32_t pid : 32;/* [31:0] */
} idcode_bit;
};
/**
* @brief debug ctrl register, offset:0x04
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t sleep_debug : 1;/* [0] */
__IO uint32_t deepsleep_debug : 1;/* [1] */
__IO uint32_t standby_debug : 1;/* [2] */
__IO uint32_t reserved1 : 2;/* [4:3] */
__IO uint32_t trace_ioen : 1;/* [5] */
__IO uint32_t trace_mode : 2;/* [7:6] */
__IO uint32_t wdt_pause : 1;/* [8] */
__IO uint32_t wwdt_pause : 1;/* [9] */
__IO uint32_t tmr1_pause : 1;/* [10] */
__IO uint32_t tmr2_pause : 1;/* [11] */
__IO uint32_t tmr3_pause : 1;/* [12] */
__IO uint32_t tmr4_pause : 1;/* [13] */
__IO uint32_t can1_pause : 1;/* [14] */
__IO uint32_t i2c1_smbus_timeout : 1;/* [15] */
__IO uint32_t i2c2_smbus_timeout : 1;/* [16] */
__IO uint32_t tmr8_pause : 1;/* [17] */
__IO uint32_t tmr5_pause : 1;/* [18] */
__IO uint32_t tmr6_pause : 1;/* [19] */
__IO uint32_t tmr7_pause : 1;/* [20] */
__IO uint32_t can2_pause : 1;/* [21] */
__IO uint32_t reserved2 : 3;/* [24:22] */
__IO uint32_t tmr12_pause : 1;/* [25] */
__IO uint32_t tmr13_pause : 1;/* [26] */
__IO uint32_t tmr14_pause : 1;/* [27] */
__IO uint32_t tmr9_pause : 1;/* [28] */
__IO uint32_t tmr10_pause : 1;/* [29] */
__IO uint32_t tmr11_pause : 1;/* [30] */
__IO uint32_t i2c3_smbus_timeout : 1;/* [31] */
} ctrl_bit;
};
} debug_type;
/**
* @}
*/
#define DEBUGMCU ((debug_type *) DEBUG_BASE)
/** @defgroup DEBUG_exported_functions
* @{
*/
uint32_t debug_device_id_get(void);
void debug_periph_mode_set(uint32_t periph_debug_mode, confirm_state new_state);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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libraries/drivers/inc/at32f415_def.h Normal file
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/**
**************************************************************************
* @file at32f415_def.h
* @brief at32f415 macros header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_DEF_H
#define __AT32F415_DEF_H
#ifdef __cplusplus
extern "C" {
#endif
/* gnu compiler */
#if defined (__GNUC__)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL __attribute__ ((aligned (4)))
#endif
#endif
/* arm compiler */
#if defined (__CC_ARM)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD __align(4)
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL
#endif
#endif
/* iar compiler */
#if defined (__ICCARM__)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL
#endif
#endif
#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */
#ifdef __cplusplus
}
#endif
#endif

521
libraries/drivers/inc/at32f415_dma.h Normal file
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/**
**************************************************************************
* @file at32f415_dma.h
* @brief at32f415 dma header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_DMA_H
#define __AT32F415_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/** @defgroup DMA_interrupts_definition
* @brief dma interrupt
* @{
*/
#define DMA_FDT_INT ((uint32_t)0x00000002) /*!< dma full data transfer interrupt */
#define DMA_HDT_INT ((uint32_t)0x00000004) /*!< dma half data transfer interrupt */
#define DMA_DTERR_INT ((uint32_t)0x00000008) /*!< dma errorr interrupt */
/**
* @}
*/
/** @defgroup DMA_flexible_channel
* @{
*/
#define FLEX_CHANNEL1 ((uint8_t)0x01) /*!< dma flexible channel1 */
#define FLEX_CHANNEL2 ((uint8_t)0x02) /*!< dma flexible channel2 */
#define FLEX_CHANNEL3 ((uint8_t)0x03) /*!< dma flexible channel3 */
#define FLEX_CHANNEL4 ((uint8_t)0x04) /*!< dma flexible channel4 */
#define FLEX_CHANNEL5 ((uint8_t)0x05) /*!< dma flexible channel5 */
#define FLEX_CHANNEL6 ((uint8_t)0x06) /*!< dma flexible channel6 */
#define FLEX_CHANNEL7 ((uint8_t)0x07) /*!< dma flexible channel7 */
/**
* @}
*/
/** @defgroup DMA_flags_definition
* @brief dma flag
* @{
*/
#define DMA1_GL1_FLAG ((uint32_t)0x00000001) /*!< dma1 channel1 global flag */
#define DMA1_FDT1_FLAG ((uint32_t)0x00000002) /*!< dma1 channel1 full data transfer flag */
#define DMA1_HDT1_FLAG ((uint32_t)0x00000004) /*!< dma1 channel1 half data transfer flag */
#define DMA1_DTERR1_FLAG ((uint32_t)0x00000008) /*!< dma1 channel1 error flag */
#define DMA1_GL2_FLAG ((uint32_t)0x00000010) /*!< dma1 channel2 global flag */
#define DMA1_FDT2_FLAG ((uint32_t)0x00000020) /*!< dma1 channel2 full data transfer flag */
#define DMA1_HDT2_FLAG ((uint32_t)0x00000040) /*!< dma1 channel2 half data transfer flag */
#define DMA1_DTERR2_FLAG ((uint32_t)0x00000080) /*!< dma1 channel2 error flag */
#define DMA1_GL3_FLAG ((uint32_t)0x00000100) /*!< dma1 channel3 global flag */
#define DMA1_FDT3_FLAG ((uint32_t)0x00000200) /*!< dma1 channel3 full data transfer flag */
#define DMA1_HDT3_FLAG ((uint32_t)0x00000400) /*!< dma1 channel3 half data transfer flag */
#define DMA1_DTERR3_FLAG ((uint32_t)0x00000800) /*!< dma1 channel3 error flag */
#define DMA1_GL4_FLAG ((uint32_t)0x00001000) /*!< dma1 channel4 global flag */
#define DMA1_FDT4_FLAG ((uint32_t)0x00002000) /*!< dma1 channel4 full data transfer flag */
#define DMA1_HDT4_FLAG ((uint32_t)0x00004000) /*!< dma1 channel4 half data transfer flag */
#define DMA1_DTERR4_FLAG ((uint32_t)0x00008000) /*!< dma1 channel4 error flag */
#define DMA1_GL5_FLAG ((uint32_t)0x00010000) /*!< dma1 channel5 global flag */
#define DMA1_FDT5_FLAG ((uint32_t)0x00020000) /*!< dma1 channel5 full data transfer flag */
#define DMA1_HDT5_FLAG ((uint32_t)0x00040000) /*!< dma1 channel5 half data transfer flag */
#define DMA1_DTERR5_FLAG ((uint32_t)0x00080000) /*!< dma1 channel5 error flag */
#define DMA1_GL6_FLAG ((uint32_t)0x00100000) /*!< dma1 channel6 global flag */
#define DMA1_FDT6_FLAG ((uint32_t)0x00200000) /*!< dma1 channel6 full data transfer flag */
#define DMA1_HDT6_FLAG ((uint32_t)0x00400000) /*!< dma1 channel6 half data transfer flag */
#define DMA1_DTERR6_FLAG ((uint32_t)0x00800000) /*!< dma1 channel6 error flag */
#define DMA1_GL7_FLAG ((uint32_t)0x01000000) /*!< dma1 channel7 global flag */
#define DMA1_FDT7_FLAG ((uint32_t)0x02000000) /*!< dma1 channel7 full data transfer flag */
#define DMA1_HDT7_FLAG ((uint32_t)0x04000000) /*!< dma1 channel7 half data transfer flag */
#define DMA1_DTERR7_FLAG ((uint32_t)0x08000000) /*!< dma1 channel7 error flag */
#define DMA2_GL1_FLAG ((uint32_t)0x10000001) /*!< dma2 channel1 global flag */
#define DMA2_FDT1_FLAG ((uint32_t)0x10000002) /*!< dma2 channel1 full data transfer flag */
#define DMA2_HDT1_FLAG ((uint32_t)0x10000004) /*!< dma2 channel1 half data transfer flag */
#define DMA2_DTERR1_FLAG ((uint32_t)0x10000008) /*!< dma2 channel1 error flag */
#define DMA2_GL2_FLAG ((uint32_t)0x10000010) /*!< dma2 channel2 global flag */
#define DMA2_FDT2_FLAG ((uint32_t)0x10000020) /*!< dma2 channel2 full data transfer flag */
#define DMA2_HDT2_FLAG ((uint32_t)0x10000040) /*!< dma2 channel2 half data transfer flag */
#define DMA2_DTERR2_FLAG ((uint32_t)0x10000080) /*!< dma2 channel2 error flag */
#define DMA2_GL3_FLAG ((uint32_t)0x10000100) /*!< dma2 channel3 global flag */
#define DMA2_FDT3_FLAG ((uint32_t)0x10000200) /*!< dma2 channel3 full data transfer flag */
#define DMA2_HDT3_FLAG ((uint32_t)0x10000400) /*!< dma2 channel3 half data transfer flag */
#define DMA2_DTERR3_FLAG ((uint32_t)0x10000800) /*!< dma2 channel3 error flag */
#define DMA2_GL4_FLAG ((uint32_t)0x10001000) /*!< dma2 channel4 global flag */
#define DMA2_FDT4_FLAG ((uint32_t)0x10002000) /*!< dma2 channel4 full data transfer flag */
#define DMA2_HDT4_FLAG ((uint32_t)0x10004000) /*!< dma2 channel4 half data transfer flag */
#define DMA2_DTERR4_FLAG ((uint32_t)0x10008000) /*!< dma2 channel4 error flag */
#define DMA2_GL5_FLAG ((uint32_t)0x10010000) /*!< dma2 channel5 global flag */
#define DMA2_FDT5_FLAG ((uint32_t)0x10020000) /*!< dma2 channel5 full data transfer flag */
#define DMA2_HDT5_FLAG ((uint32_t)0x10040000) /*!< dma2 channel5 half data transfer flag */
#define DMA2_DTERR5_FLAG ((uint32_t)0x10080000) /*!< dma2 channel5 error flag */
#define DMA2_GL6_FLAG ((uint32_t)0x10100000) /*!< dma2 channel6 global flag */
#define DMA2_FDT6_FLAG ((uint32_t)0x10200000) /*!< dma2 channel6 full data transfer flag */
#define DMA2_HDT6_FLAG ((uint32_t)0x10400000) /*!< dma2 channel6 half data transfer flag */
#define DMA2_DTERR6_FLAG ((uint32_t)0x10800000) /*!< dma2 channel6 error flag */
#define DMA2_GL7_FLAG ((uint32_t)0x11000000) /*!< dma2 channel7 global flag */
#define DMA2_FDT7_FLAG ((uint32_t)0x12000000) /*!< dma2 channel7 full data transfer flag */
#define DMA2_HDT7_FLAG ((uint32_t)0x14000000) /*!< dma2 channel7 half data transfer flag */
#define DMA2_DTERR7_FLAG ((uint32_t)0x18000000) /*!< dma2 channel7 error flag */
/**
* @}
*/
/** @defgroup DMA_exported_types
* @{
*/
/**
* @brief dma flexible request type
*/
typedef enum
{
DMA_FLEXIBLE_ADC1 = 0x01, /*!< adc1 flexible request id */
DMA_FLEXIBLE_SPI1_RX = 0x09, /*!< spi1_rx flexible request id */
DMA_FLEXIBLE_SPI1_TX = 0x0A, /*!< spi1_tx flexible request id */
DMA_FLEXIBLE_SPI2_RX = 0x0B, /*!< spi2_rx flexible request id */
DMA_FLEXIBLE_SPI2_TX = 0x0C, /*!< spi2_tx flexible request id */
DMA_FLEXIBLE_UART1_RX = 0x19, /*!< uart1_rx flexible request id */
DMA_FLEXIBLE_UART1_TX = 0x1A, /*!< uart1_tx flexible request id */
DMA_FLEXIBLE_UART2_RX = 0x1B, /*!< uart2_rx flexible request id */
DMA_FLEXIBLE_UART2_TX = 0x1C, /*!< uart2_tx flexible request id */
DMA_FLEXIBLE_UART3_RX = 0x1D, /*!< uart3_rx flexible request id */
DMA_FLEXIBLE_UART3_TX = 0x1E, /*!< uart3_tx flexible request id */
DMA_FLEXIBLE_UART4_RX = 0x1F, /*!< uart4_rx flexible request id */
DMA_FLEXIBLE_UART4_TX = 0x20, /*!< uart4_tx flexible request id */
DMA_FLEXIBLE_UART5_RX = 0x21, /*!< uart5_rx flexible request id */
DMA_FLEXIBLE_UART5_TX = 0x22, /*!< uart5_tx flexible request id */
DMA_FLEXIBLE_I2C1_RX = 0x29, /*!< i2c1_rx flexible request id */
DMA_FLEXIBLE_I2C1_TX = 0x2A, /*!< i2c1_tx flexible request id */
DMA_FLEXIBLE_I2C2_RX = 0x2B, /*!< i2c2_rx flexible request id */
DMA_FLEXIBLE_I2C2_TX = 0x2C, /*!< i2c2_tx flexible request id */
DMA_FLEXIBLE_SDIO1 = 0x31, /*!< sdio1 flexible request id */
DMA_FLEXIBLE_TMR1_TRIG = 0x35, /*!< tmr1_trig flexible request id */
DMA_FLEXIBLE_TMR1_HALL = 0x36, /*!< tmr1_hall flexible request id */
DMA_FLEXIBLE_TMR1_OVERFLOW = 0x37, /*!< tmr1_overflow flexible request id */
DMA_FLEXIBLE_TMR1_CH1 = 0x38, /*!< tmr1_ch1 flexible request id */
DMA_FLEXIBLE_TMR1_CH2 = 0x39, /*!< tmr1_ch2 flexible request id */
DMA_FLEXIBLE_TMR1_CH3 = 0x3A, /*!< tmr1_ch3 flexible request id */
DMA_FLEXIBLE_TMR1_CH4 = 0x3B, /*!< tmr1_ch4 flexible request id */
DMA_FLEXIBLE_TMR2_TRIG = 0x3D, /*!< tmr2_trig flexible request id */
DMA_FLEXIBLE_TMR2_OVERFLOW = 0x3F, /*!< tmr2_overflow flexible request id */
DMA_FLEXIBLE_TMR2_CH1 = 0x40, /*!< tmr2_ch1 flexible request id */
DMA_FLEXIBLE_TMR2_CH2 = 0x41, /*!< tmr2_ch2 flexible request id */
DMA_FLEXIBLE_TMR2_CH3 = 0x42, /*!< tmr2_ch3 flexible request id */
DMA_FLEXIBLE_TMR2_CH4 = 0x43, /*!< tmr2_ch4 flexible request id */
DMA_FLEXIBLE_TMR3_TRIG = 0x45, /*!< tmr3_trig flexible request id */
DMA_FLEXIBLE_TMR3_OVERFLOW = 0x47, /*!< tmr3_overflow flexible request id */
DMA_FLEXIBLE_TMR3_CH1 = 0x48, /*!< tmr3_ch1 flexible request id */
DMA_FLEXIBLE_TMR3_CH2 = 0x49, /*!< tmr3_ch2 flexible request id */
DMA_FLEXIBLE_TMR3_CH3 = 0x4A, /*!< tmr3_ch3 flexible request id */
DMA_FLEXIBLE_TMR3_CH4 = 0x4B, /*!< tmr3_ch4 flexible request id */
DMA_FLEXIBLE_TMR4_TRIG = 0x4D, /*!< tmr4_trig flexible request id */
DMA_FLEXIBLE_TMR4_OVERFLOW = 0x4F, /*!< tmr4_overflow flexible request id */
DMA_FLEXIBLE_TMR4_CH1 = 0x50, /*!< tmr4_ch1 flexible request id */
DMA_FLEXIBLE_TMR4_CH2 = 0x51, /*!< tmr4_ch2 flexible request id */
DMA_FLEXIBLE_TMR4_CH3 = 0x52, /*!< tmr4_ch3 flexible request id */
DMA_FLEXIBLE_TMR4_CH4 = 0x53, /*!< tmr4_ch4 flexible request id */
DMA_FLEXIBLE_TMR5_TRIG = 0x55, /*!< tmr5_trig flexible request id */
DMA_FLEXIBLE_TMR5_OVERFLOW = 0x57, /*!< tmr5_overflow flexible request id */
DMA_FLEXIBLE_TMR5_CH1 = 0x58, /*!< tmr5_ch1 flexible request id */
DMA_FLEXIBLE_TMR5_CH2 = 0x59, /*!< tmr5_ch2 flexible request id */
DMA_FLEXIBLE_TMR5_CH3 = 0x5A, /*!< tmr5_ch3 flexible request id */
DMA_FLEXIBLE_TMR5_CH4 = 0x5B, /*!< tmr5_ch4 flexible request id */
} dma_flexible_request_type;
/**
* @brief dma direction type
*/
typedef enum
{
DMA_DIR_PERIPHERAL_TO_MEMORY = 0x0000, /*!< dma data transfer direction:peripheral to memory */
DMA_DIR_MEMORY_TO_PERIPHERAL = 0x0010, /*!< dma data transfer direction:memory to peripheral */
DMA_DIR_MEMORY_TO_MEMORY = 0x4000 /*!< dma data transfer direction:memory to memory */
} dma_dir_type;
/**
* @brief dma peripheral incremented type
*/
typedef enum
{
DMA_PERIPHERAL_INC_DISABLE = 0x00, /*!< dma peripheral increment mode disable */
DMA_PERIPHERAL_INC_ENABLE = 0x01 /*!< dma peripheral increment mode enable */
} dma_peripheral_inc_type;
/**
* @brief dma memory incremented type
*/
typedef enum
{
DMA_MEMORY_INC_DISABLE = 0x00, /*!< dma memory increment mode disable */
DMA_MEMORY_INC_ENABLE = 0x01 /*!< dma memory increment mode enable */
} dma_memory_inc_type;
/**
* @brief dma peripheral data size type
*/
typedef enum
{
DMA_PERIPHERAL_DATA_WIDTH_BYTE = 0x00, /*!< dma peripheral databus width 8bit */
DMA_PERIPHERAL_DATA_WIDTH_HALFWORD = 0x01, /*!< dma peripheral databus width 16bit */
DMA_PERIPHERAL_DATA_WIDTH_WORD = 0x02 /*!< dma peripheral databus width 32bit */
} dma_peripheral_data_size_type;
/**
* @brief dma memory data size type
*/
typedef enum
{
DMA_MEMORY_DATA_WIDTH_BYTE = 0x00, /*!< dma memory databus width 8bit */
DMA_MEMORY_DATA_WIDTH_HALFWORD = 0x01, /*!< dma memory databus width 16bit */
DMA_MEMORY_DATA_WIDTH_WORD = 0x02 /*!< dma memory databus width 32bit */
} dma_memory_data_size_type;
/**
* @brief dma priority level type
*/
typedef enum
{
DMA_PRIORITY_LOW = 0x00, /*!< dma channel priority: low */
DMA_PRIORITY_MEDIUM = 0x01, /*!< dma channel priority: mediue */
DMA_PRIORITY_HIGH = 0x02, /*!< dma channel priority: high */
DMA_PRIORITY_VERY_HIGH = 0x03 /*!< dma channel priority: very high */
} dma_priority_level_type;
/**
* @brief dma init type
*/
typedef struct
{
uint32_t peripheral_base_addr; /*!< base addrress for peripheral */
uint32_t memory_base_addr; /*!< base addrress for memory */
dma_dir_type direction; /*!< dma transmit direction, peripheral as source or as destnation */
uint16_t buffer_size; /*!< counter to transfer */
confirm_state peripheral_inc_enable; /*!< periphera address increment after one transmit */
confirm_state memory_inc_enable; /*!< memory address increment after one transmit */
dma_peripheral_data_size_type peripheral_data_width; /*!< peripheral data width for transmit */
dma_memory_data_size_type memory_data_width; /*!< memory data width for transmit */
confirm_state loop_mode_enable; /*!< when circular mode enable, buffer size will reload if count to 0 */
dma_priority_level_type priority; /*!< dma priority can choose from very high, high, dedium or low */
} dma_init_type;
/**
* @brief type define dma register
*/
typedef struct
{
/**
* @brief dma sts register, offset:0x00
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t gf1 : 1; /* [0] */
__IO uint32_t fdtf1 : 1; /* [1] */
__IO uint32_t hdtf1 : 1; /* [2] */
__IO uint32_t dterrf1 : 1; /* [3] */
__IO uint32_t gf2 : 1; /* [4] */
__IO uint32_t fdtf2 : 1; /* [5] */
__IO uint32_t hdtf2 : 1; /* [6] */
__IO uint32_t dterrf2 : 1; /* [7] */
__IO uint32_t gf3 : 1; /* [8] */
__IO uint32_t fdtf3 : 1; /* [9] */
__IO uint32_t hdtf3 : 1; /* [10] */
__IO uint32_t dterrf3 : 1; /* [11] */
__IO uint32_t gf4 : 1; /* [12] */
__IO uint32_t fdtf4 : 1; /* [13] */
__IO uint32_t hdtf4 : 1; /* [14] */
__IO uint32_t dterrf4 : 1; /* [15] */
__IO uint32_t gf5 : 1; /* [16] */
__IO uint32_t fdtf5 : 1; /* [17] */
__IO uint32_t hdtf5 : 1; /* [18] */
__IO uint32_t dterrf5 : 1; /* [19] */
__IO uint32_t gf6 : 1; /* [20] */
__IO uint32_t fdtf6 : 1; /* [21] */
__IO uint32_t hdtf6 : 1; /* [22] */
__IO uint32_t dterrf6 : 1; /* [23] */
__IO uint32_t gf7 : 1; /* [24] */
__IO uint32_t fdtf7 : 1; /* [25] */
__IO uint32_t hdtf7 : 1; /* [26] */
__IO uint32_t dterrf7 : 1; /* [27] */
__IO uint32_t reserved1 : 4; /* [31:28] */
} sts_bit;
};
/**
* @brief dma clr register, offset:0x04
*/
union
{
__IO uint32_t clr;
struct
{
__IO uint32_t gfc1 : 1; /* [0] */
__IO uint32_t fdtfc1 : 1; /* [1] */
__IO uint32_t hdtfc1 : 1; /* [2] */
__IO uint32_t dterrfc1 : 1; /* [3] */
__IO uint32_t gfc2 : 1; /* [4] */
__IO uint32_t fdtfc2 : 1; /* [5] */
__IO uint32_t hdtfc2 : 1; /* [6] */
__IO uint32_t dterrfc2 : 1; /* [7] */
__IO uint32_t gfc3 : 1; /* [8] */
__IO uint32_t fdtfc3 : 1; /* [9] */
__IO uint32_t hdtfc3 : 1; /* [10] */
__IO uint32_t dterrfc3 : 1; /* [11] */
__IO uint32_t gfc4 : 1; /* [12] */
__IO uint32_t fdtfc4 : 1; /* [13] */
__IO uint32_t hdtfc4 : 1; /* [14] */
__IO uint32_t dterrfc4 : 1; /* [15] */
__IO uint32_t gfc5 : 1; /* [16] */
__IO uint32_t fdtfc5 : 1; /* [17] */
__IO uint32_t hdtfc5 : 1; /* [18] */
__IO uint32_t dterrfc5 : 1; /* [19] */
__IO uint32_t gfc6 : 1; /* [20] */
__IO uint32_t fdtfc6 : 1; /* [21] */
__IO uint32_t hdtfc6 : 1; /* [22] */
__IO uint32_t dterrfc6 : 1; /* [23] */
__IO uint32_t gfc7 : 1; /* [24] */
__IO uint32_t fdtfc7 : 1; /* [25] */
__IO uint32_t hdtfc7 : 1; /* [26] */
__IO uint32_t dterrfc7 : 1; /* [27] */
__IO uint32_t reserved1 : 4; /* [31:28] */
} clr_bit;
};
/**
* @brief reserved, offset:0x08~0x9C
*/
__IO uint32_t reserved1[38];
/**
* @brief dma src_sel0 register, offset:0xA0
*/
union
{
__IO uint32_t src_sel0;
struct
{
__IO uint32_t ch1_src : 8; /* [7:0] */
__IO uint32_t ch2_src : 8; /* [15:8] */
__IO uint32_t ch3_src : 8; /* [23:16] */
__IO uint32_t ch4_src : 8; /* [31:24] */
} src_sel0_bit;
};
/**
* @brief dma src_sel1 register, offset:0xA4
*/
union
{
__IO uint32_t src_sel1;
struct
{
__IO uint32_t ch5_src : 8; /* [7:0] */
__IO uint32_t ch6_src : 8; /* [15:8] */
__IO uint32_t ch7_src : 8; /* [23:16] */
__IO uint32_t dma_flex_en : 1; /* [24] */
__IO uint32_t reserved1 : 7; /* [31:25] */
} src_sel1_bit;
};
} dma_type;
/**
* @brief type define dma channel register all
*/
typedef struct
{
/**
* @brief dma ctrl register, offset:0x08+20*(x-1) x=1...7
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t chen : 1; /* [0] */
__IO uint32_t fdtien : 1; /* [1] */
__IO uint32_t hdtien : 1; /* [2] */
__IO uint32_t dterrien : 1; /* [3] */
__IO uint32_t dtd : 1; /* [4] */
__IO uint32_t lm : 1; /* [5] */
__IO uint32_t pincm : 1; /* [6] */
__IO uint32_t mincm : 1; /* [7] */
__IO uint32_t pwidth : 2; /* [9:8] */
__IO uint32_t mwidth : 2; /* [11:10] */
__IO uint32_t chpl : 2; /* [13:12] */
__IO uint32_t m2m : 1; /* [14] */
__IO uint32_t reserved1 : 17;/* [31:15] */
} ctrl_bit;
};
/**
* @brief dma dtcnt register, offset:0x0C+20*(x-1) x=1...7
*/
union
{
__IO uint32_t dtcnt;
struct
{
__IO uint32_t cnt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} dtcnt_bit;
};
/**
* @brief dma cpba register, offset:0x10+20*(x-1) x=1...7
*/
union
{
__IO uint32_t paddr;
struct
{
__IO uint32_t paddr : 32;/* [31:0] */
} paddr_bit;
};
/**
* @brief dma cmba register, offset:0x14+20*(x-1) x=1...7
*/
union
{
__IO uint32_t maddr;
struct
{
__IO uint32_t maddr : 32;/* [31:0] */
} maddr_bit;
};
} dma_channel_type;
/**
* @}
*/
#define DMA1 ((dma_type *) DMA1_BASE)
#define DMA1_CHANNEL1 ((dma_channel_type *) DMA1_CHANNEL1_BASE)
#define DMA1_CHANNEL2 ((dma_channel_type *) DMA1_CHANNEL2_BASE)
#define DMA1_CHANNEL3 ((dma_channel_type *) DMA1_CHANNEL3_BASE)
#define DMA1_CHANNEL4 ((dma_channel_type *) DMA1_CHANNEL4_BASE)
#define DMA1_CHANNEL5 ((dma_channel_type *) DMA1_CHANNEL5_BASE)
#define DMA1_CHANNEL6 ((dma_channel_type *) DMA1_CHANNEL6_BASE)
#define DMA1_CHANNEL7 ((dma_channel_type *) DMA1_CHANNEL7_BASE)
#define DMA2 ((dma_type *) DMA2_BASE)
#define DMA2_CHANNEL1 ((dma_channel_type *) DMA2_CHANNEL1_BASE)
#define DMA2_CHANNEL2 ((dma_channel_type *) DMA2_CHANNEL2_BASE)
#define DMA2_CHANNEL3 ((dma_channel_type *) DMA2_CHANNEL3_BASE)
#define DMA2_CHANNEL4 ((dma_channel_type *) DMA2_CHANNEL4_BASE)
#define DMA2_CHANNEL5 ((dma_channel_type *) DMA2_CHANNEL5_BASE)
#define DMA2_CHANNEL6 ((dma_channel_type *) DMA2_CHANNEL6_BASE)
#define DMA2_CHANNEL7 ((dma_channel_type *) DMA2_CHANNEL7_BASE)
/** @defgroup DMA_exported_functions
* @{
*/
void dma_reset(dma_channel_type* dmax_channely);
void dma_default_para_init(dma_init_type* dma_init_struct);
void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct);
void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state);
void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request);
void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number);
uint16_t dma_data_number_get(dma_channel_type* dmax_channely);
void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state);
flag_status dma_flag_get(uint32_t dmax_flag);
flag_status dma_interrupt_flag_get(uint32_t dmax_flag);
void dma_flag_clear(uint32_t dmax_flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f415_exint.h
* @brief at32f415 exint header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_EXINT_H
#define __AT32F415_EXINT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup EXINT
* @{
*/
/** @defgroup EXINT_lines
* @{
*/
#define EXINT_LINE_NONE ((uint32_t)0x000000)
#define EXINT_LINE_0 ((uint32_t)0x000001) /*!< external interrupt line 0 */
#define EXINT_LINE_1 ((uint32_t)0x000002) /*!< external interrupt line 1 */
#define EXINT_LINE_2 ((uint32_t)0x000004) /*!< external interrupt line 2 */
#define EXINT_LINE_3 ((uint32_t)0x000008) /*!< external interrupt line 3 */
#define EXINT_LINE_4 ((uint32_t)0x000010) /*!< external interrupt line 4 */
#define EXINT_LINE_5 ((uint32_t)0x000020) /*!< external interrupt line 5 */
#define EXINT_LINE_6 ((uint32_t)0x000040) /*!< external interrupt line 6 */
#define EXINT_LINE_7 ((uint32_t)0x000080) /*!< external interrupt line 7 */
#define EXINT_LINE_8 ((uint32_t)0x000100) /*!< external interrupt line 8 */
#define EXINT_LINE_9 ((uint32_t)0x000200) /*!< external interrupt line 9 */
#define EXINT_LINE_10 ((uint32_t)0x000400) /*!< external interrupt line 10 */
#define EXINT_LINE_11 ((uint32_t)0x000800) /*!< external interrupt line 11 */
#define EXINT_LINE_12 ((uint32_t)0x001000) /*!< external interrupt line 12 */
#define EXINT_LINE_13 ((uint32_t)0x002000) /*!< external interrupt line 13 */
#define EXINT_LINE_14 ((uint32_t)0x004000) /*!< external interrupt line 14 */
#define EXINT_LINE_15 ((uint32_t)0x008000) /*!< external interrupt line 15 */
#define EXINT_LINE_16 ((uint32_t)0x010000) /*!< external interrupt line 16 connected to the pvm output */
#define EXINT_LINE_17 ((uint32_t)0x020000) /*!< external interrupt line 17 connected to the rtc alarm event */
#define EXINT_LINE_18 ((uint32_t)0x040000) /*!< external interrupt line 18 connected to the otg fs wakeup from suspend event */
#define EXINT_LINE_19 ((uint32_t)0x080000) /*!< external interrupt line 19 connected to the comp1*/
#define EXINT_LINE_20 ((uint32_t)0x100000) /*!< external interrupt line 20 connected to the comp1*/
#define EXINT_LINE_21 ((uint32_t)0x200000) /*!< external interrupt line 21 connected to the rtc temper and timestamp event */
#define EXINT_LINE_22 ((uint32_t)0x400000) /*!< external interrupt line 22 connected to the rtc wakeup event */
/**
* @}
*/
/** @defgroup EXINT_exported_types
* @{
*/
/**
* @brief exint line mode type
*/
typedef enum
{
EXINT_LINE_INTERRUPUT = 0x00, /*!< external interrupt line interrupt mode */
EXINT_LINE_EVENT = 0x01 /*!< external interrupt line event mode */
} exint_line_mode_type;
/**
* @brief exint polarity configuration type
*/
typedef enum
{
EXINT_TRIGGER_RISING_EDGE = 0x00, /*!< external interrupt line rising trigger mode */
EXINT_TRIGGER_FALLING_EDGE = 0x01, /*!< external interrupt line falling trigger mode */
EXINT_TRIGGER_BOTH_EDGE = 0x02 /*!< external interrupt line both rising and falling trigger mode */
} exint_polarity_config_type;
/**
* @brief exint init type
*/
typedef struct
{
exint_line_mode_type line_mode; /*!< choose mode event or interrupt mode */
uint32_t line_select; /*!< select the exint line, availiable for single line or multiple lines */
exint_polarity_config_type line_polarity; /*!< select the tregger polarity, with rising edge, falling edge or both edge */
confirm_state line_enable; /*!< enable or disable exint */
} exint_init_type;
/**
* @brief type define exint register all
*/
typedef struct
{
/**
* @brief exint inten register, offset:0x00
*/
union
{
__IO uint32_t inten;
struct
{
__IO uint32_t intenx : 23;/* [22:0] */
__IO uint32_t reserved1 : 9;/* [31:23] */
} inten_bit;
};
/**
* @brief exint evten register, offset:0x04
*/
union
{
__IO uint32_t evten;
struct
{
__IO uint32_t evtenx : 23;/* [22:0] */
__IO uint32_t reserved1 : 9;/* [31:23] */
} evten_bit;
};
/**
* @brief exint polcfg1 register, offset:0x08
*/
union
{
__IO uint32_t polcfg1;
struct
{
__IO uint32_t rpx : 23;/* [22:0] */
__IO uint32_t reserved1 : 9;/* [31:23] */
} polcfg1_bit;
};
/**
* @brief exint polcfg2 register, offset:0x0C
*/
union
{
__IO uint32_t polcfg2;
struct
{
__IO uint32_t fpx : 23;/* [22:0] */
__IO uint32_t reserved1 : 9;/* [31:23] */
} polcfg2_bit;
};
/**
* @brief exint swtrg register, offset:0x10
*/
union
{
__IO uint32_t swtrg;
struct
{
__IO uint32_t swtx : 23;/* [22:0] */
__IO uint32_t reserved1 : 9;/* [31:23] */
} swtrg_bit;
};
/**
* @brief exint intsts register, offset:0x14
*/
union
{
__IO uint32_t intsts;
struct
{
__IO uint32_t linex : 23;/* [22:0] */
__IO uint32_t reserved1 : 9;/* [31:23] */
} intsts_bit;
};
} exint_type;
/**
* @}
*/
#define EXINT ((exint_type *) EXINT_BASE)
/** @defgroup EXINT_exported_functions
* @{
*/
void exint_reset(void);
void exint_default_para_init(exint_init_type *exint_struct);
void exint_init(exint_init_type *exint_struct);
void exint_flag_clear(uint32_t exint_line);
flag_status exint_flag_get(uint32_t exint_line);
flag_status exint_interrupt_flag_get(uint32_t exint_line);
void exint_software_interrupt_event_generate(uint32_t exint_line);
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state);
void exint_event_enable(uint32_t exint_line, confirm_state new_state);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f415_flash.h
* @brief at32f415 flash header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_FLASH_H
#define __AT32F415_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/** @defgroup FLASH_keys
* @brief flash keys
* @{
*/
#define FLASH_UNLOCK_KEY1 ((uint32_t)0x45670123) /*!< flash operation unlock order key1 */
#define FLASH_UNLOCK_KEY2 ((uint32_t)0xCDEF89AB) /*!< flash operation unlock order key2 */
#define FAP_RELIEVE_KEY ((uint16_t)0x00A5) /*!< flash fap relieve key val */
#define FAP_HIGH_LEVEL_KEY ((uint16_t)0x00CC) /*!< flash fap high level enable key val */
#define SLIB_UNLOCK_KEY ((uint32_t)0xA35F6D24) /*!< flash slib operation unlock order key */
/**
* @}
*/
/** @defgroup FLASH_flags
* @brief flash flag
* @{
*/
#define FLASH_OBF_FLAG ((uint32_t)0x00000001) /*!< flash operate busy flag */
#define FLASH_ODF_FLAG ((uint32_t)0x00000020) /*!< flash operate done flag */
#define FLASH_PRGMERR_FLAG ((uint32_t)0x00000004) /*!< flash program error flag */
#define FLASH_EPPERR_FLAG ((uint32_t)0x00000010) /*!< flash erase/program protection error flag */
#define FLASH_USDERR_FLAG ((uint32_t)0x40000001) /*!< flash user system data error flag */
/**
* @}
*/
/** @defgroup FLASH_interrupts
* @brief flash interrupts
* @{
*/
#define FLASH_ERR_INT ((uint32_t)0x00000001) /*!< flash error interrupt */
#define FLASH_ODF_INT ((uint32_t)0x00000002) /*!< flash operate done interrupt */
/**
* @}
*/
/** @defgroup FLASH_slib_mask
* @brief flash slib mask
* @{
*/
#define FLASH_SLIB_START_SECTOR ((uint32_t)0x000007FF) /*!< flash slib start sector */
#define FLASH_SLIB_DATA_START_SECTOR ((uint32_t)0x003FF800) /*!< flash slib d-bus area start sector */
#define FLASH_SLIB_END_SECTOR ((uint32_t)0xFFC00000) /*!< flash slib end sector */
/**
* @}
*/
/** @defgroup FLASH_user_system_data
* @brief flash user system data
* @{
*/
#define USD_WDT_ATO_DISABLE ((uint16_t)0x0001) /*!< wdt auto start disabled */
#define USD_WDT_ATO_ENABLE ((uint16_t)0x0000) /*!< wdt auto start enabled */
#define USD_DEPSLP_NO_RST ((uint16_t)0x0002) /*!< no reset generated when entering in deepsleep */
#define USD_DEPSLP_RST ((uint16_t)0x0000) /*!< reset generated when entering in deepsleep */
#define USD_STDBY_NO_RST ((uint16_t)0x0004) /*!< no reset generated when entering in standby */
#define USD_STDBY_RST ((uint16_t)0x0000) /*!< reset generated when entering in standby */
/**
* @}
*/
/** @defgroup FLASH_timeout_definition
* @brief flash timeout definition
* @{
*/
#define ERASE_TIMEOUT ((uint32_t)0x40000000) /*!< internal flash erase operation timeout */
#define PROGRAMMING_TIMEOUT ((uint32_t)0x00100000) /*!< internal flash program operation timeout */
#define OPERATION_TIMEOUT ((uint32_t)0x10000000) /*!< flash common operation timeout */
/**
* @}
*/
/**
* @brief set the flash psr register
* @param wtcyc: the flash wait cycle.
* this parameter can be one of the following values:
* - FLASH_WAIT_CYCLE_0
* - FLASH_WAIT_CYCLE_1
* - FLASH_WAIT_CYCLE_2
* - FLASH_WAIT_CYCLE_3
* - FLASH_WAIT_CYCLE_4
*/
#define flash_psr_set(wtcyc) (FLASH->psr = (uint32_t)(0x10 | wtcyc))
/** @defgroup FLASH_exported_types
* @{
*/
/**
* @brief flash status type
*/
typedef enum
{
FLASH_OPERATE_BUSY = 0x00, /*!< flash status is operate busy */
FLASH_PROGRAM_ERROR = 0x01, /*!< flash status is program error */
FLASH_EPP_ERROR = 0x02, /*!< flash status is epp error */
FLASH_OPERATE_DONE = 0x03, /*!< flash status is operate done */
FLASH_OPERATE_TIMEOUT = 0x04 /*!< flash status is operate timeout */
} flash_status_type;
/**
* @brief flash wait cycle type
*/
typedef enum
{
FLASH_WAIT_CYCLE_0 = 0x00, /*!< sysclk 1~32mhz */
FLASH_WAIT_CYCLE_1 = 0x01, /*!< sysclk 33~64mhz */
FLASH_WAIT_CYCLE_2 = 0x02, /*!< sysclk 65~96mhz */
FLASH_WAIT_CYCLE_3 = 0x03, /*!< sysclk 97~120mhz */
FLASH_WAIT_CYCLE_4 = 0x04 /*!< sysclk 121~150mhz */
} flash_wait_cycle_type;
/**
* @brief type define flash register all
*/
typedef struct
{
/**
* @brief flash psr register, offset:0x00
*/
union
{
__IO uint32_t psr;
struct
{
__IO uint32_t wtcyc : 3; /* [2:0] */
__IO uint32_t hfcyc_en : 1; /* [3] */
__IO uint32_t pft_en : 1; /* [4] */
__IO uint32_t pft_enf : 1; /* [5] */
__IO uint32_t reserved1 : 26;/* [31:6] */
} psr_bit;
};
/**
* @brief flash unlock register, offset:0x04
*/
union
{
__IO uint32_t unlock;
struct
{
__IO uint32_t ukval : 32;/* [31:0] */
} unlock_bit;
};
/**
* @brief flash usd unlock register, offset:0x08
*/
union
{
__IO uint32_t usd_unlock;
struct
{
__IO uint32_t usd_ukval : 32;/* [31:0] */
} usd_unlock_bit;
};
/**
* @brief flash sts register, offset:0x0C
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t obf : 1; /* [0] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t prgmerr : 1; /* [2] */
__IO uint32_t reserved2 : 1; /* [3] */
__IO uint32_t epperr : 1; /* [4] */
__IO uint32_t odf : 1; /* [5] */
__IO uint32_t reserved3 : 26;/* [31:6] */
} sts_bit;
};
/**
* @brief flash ctrl register, offset:0x10
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t fprgm : 1; /* [0] */
__IO uint32_t secers : 1; /* [1] */
__IO uint32_t bankers : 1; /* [2] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t usdprgm : 1; /* [4] */
__IO uint32_t usders : 1; /* [5] */
__IO uint32_t erstr : 1; /* [6] */
__IO uint32_t oplk : 1; /* [7] */
__IO uint32_t reserved2 : 1; /* [8] */
__IO uint32_t usdulks : 1; /* [9] */
__IO uint32_t errie : 1; /* [10] */
__IO uint32_t reserved3 : 1; /* [11] */
__IO uint32_t odfie : 1; /* [12] */
__IO uint32_t reserved4 : 3; /* [15:13] */
__IO uint32_t fap_hl_dis : 1; /* [16] */
__IO uint32_t reserved5 : 15;/* [31:17] */
} ctrl_bit;
};
/**
* @brief flash addr register, offset:0x14
*/
union
{
__IO uint32_t addr;
struct
{
__IO uint32_t fa : 32;/* [31:0] */
} addr_bit;
};
/**
* @brief flash reserved1 register, offset:0x18
*/
__IO uint32_t reserved1;
/**
* @brief flash usd register, offset:0x1C
*/
union
{
__IO uint32_t usd;
struct
{
__IO uint32_t usderr : 1; /* [0] */
__IO uint32_t fap : 1; /* [1] */
__IO uint32_t wdt_ato_en : 1; /* [2] */
__IO uint32_t depslp_rst : 1; /* [3] */
__IO uint32_t stdby_rst : 1; /* [4] */
__IO uint32_t reserved1 : 5; /* [9:5] */
__IO uint32_t user_d0 : 8; /* [17:10] */
__IO uint32_t user_d1 : 8; /* [25:18] */
__IO uint32_t fap_hl : 1; /* [26] */
__IO uint32_t reserved2 : 5; /* [31:27] */
} usd_bit;
};
/**
* @brief flash epps register, offset:0x20
*/
union
{
__IO uint32_t epps;
struct
{
__IO uint32_t epps : 32;/* [31:0] */
} epps_bit;
};
/**
* @brief flash reserved2 register, offset:0x70~0x24
*/
__IO uint32_t reserved2[20];
/**
* @brief flash slib_sts0 register, offset:0x74
*/
union
{
__IO uint32_t slib_sts0;
struct
{
__IO uint32_t btm_ap_enf : 1; /* [0] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t em_slib_enf : 1; /* [2] */
__IO uint32_t slib_enf : 1; /* [3] */
__IO uint32_t reserved2 : 12;/* [15:4] */
__IO uint32_t em_slib_dat_ss : 8; /* [23:16] */
__IO uint32_t reserved3 : 8; /* [31:24] */
} slib_sts0_bit;
};
/**
* @brief flash slib_sts1 register, offset:0x78
*/
union
{
__IO uint32_t slib_sts1;
struct
{
__IO uint32_t slib_ss : 11;/* [10:0] */
__IO uint32_t slib_dat_ss : 11;/* [21:11] */
__IO uint32_t slib_es : 10;/* [31:22] */
} slib_sts1_bit;
};
/**
* @brief flash slib_pwd_clr register, offset:0x7C
*/
union
{
__IO uint32_t slib_pwd_clr;
struct
{
__IO uint32_t slib_pclr_val : 32;/* [31:0] */
} slib_pwd_clr_bit;
};
/**
* @brief flash slib_misc_sts register, offset:0x80
*/
union
{
__IO uint32_t slib_misc_sts;
struct
{
__IO uint32_t slib_pwd_err : 1; /* [0] */
__IO uint32_t slib_pwd_ok : 1; /* [1] */
__IO uint32_t slib_ulkf : 1; /* [2] */
__IO uint32_t reserved1 : 29;/* [31:3] */
} slib_misc_sts_bit;
};
/**
* @brief flash crc_addr register, offset:0x84
*/
union
{
__IO uint32_t crc_addr;
struct
{
__IO uint32_t crc_addr : 32;/* [31:0] */
} crc_addr_bit;
};
/**
* @brief flash crc_ctrl register, offset:0x88
*/
union
{
__IO uint32_t crc_ctrl;
struct
{
__IO uint32_t crc_sn : 16;/* [15:0] */
__IO uint32_t crc_strt : 1; /* [16] */
__IO uint32_t reserved1 : 15;/* [31:17] */
} crc_ctrl_bit;
};
/**
* @brief flash crc_chkr register, offset:0x8C
*/
union
{
__IO uint32_t crc_chkr;
struct
{
__IO uint32_t crc_chkr : 32;/* [31:0] */
} crc_chkr_bit;
};
/**
* @brief flash reserved3 register, offset:0x15C~0x90
*/
__IO uint32_t reserved3[52];
/**
* @brief flash slib_set_pwd register, offset:0x160
*/
union
{
__IO uint32_t slib_set_pwd;
struct
{
__IO uint32_t slib_pset_val : 32;/* [31:0] */
} slib_set_pwd_bit;
};
/**
* @brief flash slib_set_range register, offset:0x164
*/
union
{
__IO uint32_t slib_set_range;
struct
{
__IO uint32_t slib_ss_set : 11;/* [10:0] */
__IO uint32_t slib_dss_set : 11;/* [21:11] */
__IO uint32_t slib_es_set : 10;/* [31:22] */
} slib_set_range_bit;
};
/**
* @brief flash em_slib_set register, offset:0x168
*/
union
{
__IO uint32_t em_slib_set;
struct
{
__IO uint32_t em_slib_set : 16;/* [15:0] */
__IO uint32_t em_slib_iss_set : 8; /* [23:16] */
__IO uint32_t reserved1 : 8; /* [31:24] */
} em_slib_set_bit;
};
/**
* @brief flash btm_mode_set register, offset:0x16C
*/
union
{
__IO uint32_t btm_mode_set;
struct
{
__IO uint32_t btm_mode_set : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} btm_mode_set_bit;
};
/**
* @brief flash slib_unlock register, offset:0x170
*/
union
{
__IO uint32_t slib_unlock;
struct
{
__IO uint32_t slib_ukval : 32;/* [31:0] */
} slib_unlock_bit;
};
} flash_type;
/**
* @brief user system data
*/
typedef struct
{
__IO uint16_t fap;
__IO uint16_t ssb;
__IO uint16_t data0;
__IO uint16_t data1;
__IO uint16_t epp0;
__IO uint16_t epp1;
__IO uint16_t epp2;
__IO uint16_t epp3;
} usd_type;
/**
* @}
*/
#define FLASH ((flash_type *) FLASH_REG_BASE)
#define USD ((usd_type *) USD_BASE)
/** @defgroup FLASH_exported_functions
* @{
*/
flag_status flash_flag_get(uint32_t flash_flag);
void flash_flag_clear(uint32_t flash_flag);
flash_status_type flash_operation_status_get(void);
flash_status_type flash_operation_wait_for(uint32_t time_out);
void flash_unlock(void);
void flash_lock(void);
flash_status_type flash_sector_erase(uint32_t sector_address);
flash_status_type flash_internal_all_erase(void);
flash_status_type flash_user_system_data_erase(void);
flash_status_type flash_word_program(uint32_t address, uint32_t data);
flash_status_type flash_halfword_program(uint32_t address, uint16_t data);
flash_status_type flash_byte_program(uint32_t address, uint8_t data);
flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data);
flash_status_type flash_epp_set(uint32_t *sector_bits);
void flash_epp_status_get(uint32_t *sector_bits);
flash_status_type flash_fap_enable(confirm_state new_state);
flag_status flash_fap_status_get(void);
flash_status_type flash_fap_high_level_enable(confirm_state new_state);
flag_status flash_fap_high_level_status_get(void);
flash_status_type flash_ssb_set(uint8_t usd_ssb);
uint8_t flash_ssb_status_get(void);
void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t data_start_sector, uint16_t end_sector);
error_status flash_slib_disable(uint32_t pwd);
flag_status flash_slib_state_get(void);
uint16_t flash_slib_start_sector_get(void);
uint16_t flash_slib_datastart_sector_get(void);
uint16_t flash_slib_end_sector_get(void);
uint32_t flash_crc_calibrate(uint32_t start_addr, uint32_t sector_cnt);
void flash_boot_memory_extension_mode_enable(void);
flash_status_type flash_extension_memory_slib_enable(uint32_t pwd, uint16_t data_start_sector);
flag_status flash_extension_memory_slib_state_get(void);
uint16_t flash_em_slib_datastart_sector_get(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f415_gpio.h
* @brief at32f415 gpio header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_GPIO_H
#define __AT32F415_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/** @defgroup GPIO_pins_number_definition
* @{
*/
#define GPIO_PINS_0 0x0001 /*!< gpio pins number 0 */
#define GPIO_PINS_1 0x0002 /*!< gpio pins number 1 */
#define GPIO_PINS_2 0x0004 /*!< gpio pins number 2 */
#define GPIO_PINS_3 0x0008 /*!< gpio pins number 3 */
#define GPIO_PINS_4 0x0010 /*!< gpio pins number 4 */
#define GPIO_PINS_5 0x0020 /*!< gpio pins number 5 */
#define GPIO_PINS_6 0x0040 /*!< gpio pins number 6 */
#define GPIO_PINS_7 0x0080 /*!< gpio pins number 7 */
#define GPIO_PINS_8 0x0100 /*!< gpio pins number 8 */
#define GPIO_PINS_9 0x0200 /*!< gpio pins number 9 */
#define GPIO_PINS_10 0x0400 /*!< gpio pins number 10 */
#define GPIO_PINS_11 0x0800 /*!< gpio pins number 11 */
#define GPIO_PINS_12 0x1000 /*!< gpio pins number 12 */
#define GPIO_PINS_13 0x2000 /*!< gpio pins number 13 */
#define GPIO_PINS_14 0x4000 /*!< gpio pins number 14 */
#define GPIO_PINS_15 0x8000 /*!< gpio pins number 15 */
#define GPIO_PINS_ALL 0xFFFF /*!< gpio all pins */
/**
* @}
*/
#define IOMUX_MAKE_VALUE(reg_offset, bit_addr ,bit_num, bit_val) \
(uint32_t)(((reg_offset) << 24) | ((bit_addr) << 16) | ((bit_num) << 8) | (bit_val))
/** @defgroup IOMUX_map_definition
* @brief iomux map definitions
* @{
*/
#define SPI1_MUX_01 SPI1_GMUX_0001 /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb6) */
#define I2C1_MUX I2C1_GMUX_0001 /*!< i2c1_scl(pb8), i2c1_sda(pb9), i2c1_smba(pb5) */
#define USART1_MUX USART1_GMUX_0001 /*!< usart1_tx(pb6), usart1_rx(pb7) */
#define USART3_MUX_01 USART3_GMUX_0001 /*!< usart3_tx(pc10), usart3_rx(pc11), usart3_ck(pc12), usart3_cts(pb13), usart3_rts(pb14) */
#define USART3_MUX_10 USART3_GMUX_0010 /*!< usart3_tx(pa7), usart3_rx(pa6), usart3_ck(pa5), usart3_cts(pb1), usart3_rts(pb0) */
#define TMR1_MUX_01 TMR1_GMUX_0001 /*!< tmr1_ext(pa12), tmr1_ch1(pa8), tmr1_ch2(pa9), tmr1_ch3(pa10), tmr1_ch4(pa11), tmr1_brkin(pa6), tmr1_ch1c(pa7), tmr1_ch2c(pb0), tmr1_ch3c(pb1) */
#define TMR2_MUX_01 TMR2_GMUX_001 /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pa2), tmr2_ch4(pa3) */
#define TMR2_MUX_10 TMR2_GMUX_010 /*!< tmr2_ch1_ext(pa0), tmr2_ch2(pa1), tmr2_ch3(pb10), tmr2_ch4(pb11) */
#define TMR2_MUX_11 TMR2_GMUX_011 /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pb10), tmr2_ch4(pb11) */
#define TMR3_MUX_10 TMR3_GMUX_0010 /*!< tmr3_ch1(pb4), tmr3_ch2(pb5), tmr3_ch3(pb0), tmr3_ch4(pb1) */
#define TMR3_MUX_11 TMR3_GMUX_0011 /*!< tmr3_ch1(pc6), tmr3_ch2(pc7), tmr3_ch3(pc8), tmr3_ch4(pc9) */
#define CAN_MUX_10 CAN1_GMUX_0010 /*!< can_rx(pb8), can_tx(pb9) */
#define PD01_MUX PD01_GMUX /*!< pd0/pd1 mapping on osc_in/osc_out */
#define TMR5CH4_MUX TMR5CH4_GMUX /*!< lick connected to tmr5_ch4 input capture for calibration */
#define ADC1_ETP_MUX ADC1_ETP_GMUX /*!< adc1 external trigger preempted conversion muxing */
#define ADC1_ETO_MUX ADC1_ETO_GMUX /*!< adc1 external trigger ordinary conversion muxing */
#define SWJTAG_MUX_001 SWJTAG_GMUX_001 /*!< full swj enabled (jtag-dp + sw-dp) but without jtrst */
#define SWJTAG_MUX_010 SWJTAG_GMUX_010 /*!< jtag-dp disabled and sw-dp enabled */
#define SWJTAG_MUX_100 SWJTAG_GMUX_100 /*!< full swj disabled (jtag-dp + sw-dp) */
/**
* @}
*/
/** @defgroup IOMUX_map2_definition
* @brief iomux map2 definitions
* @{
*/
#define CMP_MUX_01 IOMUX_MAKE_VALUE(0x1C, 26, 2, 0x01) /*!< cmp1_out connect pa6, cmp2_out connect pa7 */
#define CMP_MUX_10 IOMUX_MAKE_VALUE(0x1C, 26, 2, 0x02) /*!< cmp1_out connect pa11, cmp2_out connect pa12 */
/**
* @}
*/
/** @defgroup IOMUX_map3_definition
* @brief iomux map3 definitions
* @{
*/
#define TMR9_GMUX IOMUX_MAKE_VALUE(0x20, 0, 4, 0x02) /*!< tmr9_ch1(pb14), tmr9_ch2(pb15) */
#define TMR10_GMUX IOMUX_MAKE_VALUE(0x20, 4, 4, 0x02) /*!< tmr10_ch1(pa6) */
#define TMR11_GMUX IOMUX_MAKE_VALUE(0x20, 8, 4, 0x02) /*!< tmr11_ch1(pa7) */
/**
* @}
*/
/** @defgroup IOMUX_map4_definition
* @brief iomux map4 definitions
* @{
*/
#define TMR1_GMUX_0001 IOMUX_MAKE_VALUE(0x24, 0, 4, 0x01) /*!< tmr1_ext(pa12), tmr1_ch1(pa8), tmr1_ch2(pa9), tmr1_ch3(pa10), tmr1_ch4(pa11), tmr1_brkin(pa6), tmr1_ch1c(pa7), tmr1_ch2c(pb0), tmr1_ch3c(pb1) */
#define TMR1_GMUX_0010 IOMUX_MAKE_VALUE(0x24, 0, 4, 0x02) /*!< tmr1_ext(pa0), tmr1_ch1(pc6), tmr1_ch2(pc7), tmr1_ch3(pc8), tmr1_ch4(pc9), tmr1_brkin(pa6), tmr1_ch1c(pa7), tmr1_ch2c(pb0), tmr1_ch3c(pb1) */
#define TMR2_GMUX_001 IOMUX_MAKE_VALUE(0x24, 4, 3, 0x01) /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pa2), tmr2_ch4(pa3) */
#define TMR2_GMUX_010 IOMUX_MAKE_VALUE(0x24, 4, 3, 0x02) /*!< tmr2_ch1_ext(pa0), tmr2_ch2(pa1), tmr2_ch3(pb10), tmr2_ch4(pb11) */
#define TMR2_GMUX_011 IOMUX_MAKE_VALUE(0x24, 4, 3, 0x03) /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pb10), tmr2_ch4(pb11) */
#define TMR3_GMUX_0010 IOMUX_MAKE_VALUE(0x24, 8, 4, 0x02) /*!< tmr3_ch1(pb4), tmr3_ch2(pb5), tmr3_ch3(pb0), tmr3_ch4(pb1) */
#define TMR3_GMUX_0011 IOMUX_MAKE_VALUE(0x24, 8, 4, 0x03) /*!< tmr3_ch1(pc6), tmr3_ch2(pc7), tmr3_ch3(pc8), tmr3_ch4(pc9) */
#define TMR5_GMUX_001 IOMUX_MAKE_VALUE(0x24, 16, 3, 0x01) /*!< tmr5_ch1(pf4), tmr5_ch2(pf5), tmr5_ch3(pa2), tmr5_ch4(pa3) */
#define TMR5CH4_GMUX IOMUX_MAKE_VALUE(0x24, 19, 1, 0x01) /*!< lick connected to tmr5_ch4 input capture for calibration */
/**
* @}
*/
/** @defgroup IOMUX_map5_definition
* @brief iomux map5 definitions
* @{
*/
#define I2C1_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 4, 4, 0x01) /*!< i2c1_scl(pb8), i2c1_sda(pb9), i2c1_smba(pb5) */
#define I2C1_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 4, 4, 0x02) /*!< i2c1_scl(pf6), i2c1_sda(pf7), i2c1_smba(pb5) */
#define I2C2_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 8, 4, 0x01) /*!< i2c2_scl(pa8), i2c2_sda(pc9), i2c2_smba(pa9) */
#define I2C2_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 8, 4, 0x02) /*!< i2c2_scl(pa8), i2c2_sda(pb4), i2c2_smba(pa9) */
#define I2C2_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 8, 4, 0x03) /*!< i2c2_scl(pf6), i2c2_sda(pf7), i2c2_smba(pa9) */
#define SPI1_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 16, 4, 0x01) /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb6) */
#define SPI2_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 20, 4, 0x01) /*!< spi2_cs/i2s2_ws(pa15), spi2_sck/i2s2_ck(pb3), spi2_miso(pb4), spi2_mosi/i2s2_sd(pb5), i2s2_mck(pc7) */
/**
* @}
*/
/** @defgroup IOMUX_map6_definition
* @brief iomux map6 definitions
* @{
*/
#define CAN1_GMUX_0010 IOMUX_MAKE_VALUE(0x2C, 0, 4, 0x02) /*!< can_rx(pb8), can_tx(pb9) */
#define SDIO1_GMUX_0100 IOMUX_MAKE_VALUE(0x2C, 8, 4, 0x04) /*!< sdio1_ck(pc4), sdio1_cmd(pc5), sdio1_d0(pc0), sdio1_d1(pc1), sdio1_d2(pc2), sdio1_d3(pc3), sdio1_d4(pa4), sdio1_d5(pa5), sdio1_d6(pa6), sdio1_d7(pa7) */
#define SDIO1_GMUX_0101 IOMUX_MAKE_VALUE(0x2C, 8, 4, 0x05) /*!< sdio1_ck(pc4), sdio1_cmd(pc5), sdio1_d0(pa4), sdio1_d1(pa5), sdio1_d2(pa6), sdio1_d3(pa7) */
#define SDIO1_GMUX_0110 IOMUX_MAKE_VALUE(0x2C, 8, 4, 0x06) /*!< sdio1_ck(pa2), sdio1_cmd(pa3), sdio1_d0(pc0), sdio1_d1(pc1), sdio1_d2(pc2), sdio1_d3(pc3), sdio1_d4(pa4), sdio1_d5(pa5), sdio1_d6(pa6), sdio1_d7(pa7) */
#define SDIO1_GMUX_0111 IOMUX_MAKE_VALUE(0x2C, 8, 4, 0x07) /*!< sdio1_ck(pa2), sdio1_cmd(pa3), sdio1_d0(pa4), sdio1_d1(pa5), sdio1_d2(pa6), sdio1_d3(pa7) */
#define USART1_GMUX_0001 IOMUX_MAKE_VALUE(0x2C, 16, 4, 0x01) /*!< usart1_tx(pb6), usart1_rx(pb7) */
#define USART3_GMUX_0001 IOMUX_MAKE_VALUE(0x2C, 24, 4, 0x01) /*!< usart3_tx(pc10), usart3_rx(pc11), usart3_ck(pc12), usart3_cts(pb13), usart3_rts(pb14) */
#define USART3_GMUX_0010 IOMUX_MAKE_VALUE(0x2C, 24, 4, 0x02) /*!< usart3_tx(pa7), usart3_rx(pa6), usart3_ck(pa5), usart3_cts(pb1), usart3_rts(pb0) */
#define UART4_GMUX_0001 IOMUX_MAKE_VALUE(0x2C, 28, 4, 0x01) /*!< uart4_tx(pf4), uart4_rx(pf5) */
/**
* @}
*/
/** @defgroup IOMUX_map7_definition
* @brief iomux map7 definitions
* @{
*/
#define ADC1_ETP_GMUX IOMUX_MAKE_VALUE(0x30, 4, 1, 0x01) /*!< adc1 external trigger preempted conversion muxing */
#define ADC1_ETO_GMUX IOMUX_MAKE_VALUE(0x30, 5, 1, 0x01) /*!< adc1 external trigger ordinary conversion muxing */
#define SWJTAG_GMUX_001 IOMUX_MAKE_VALUE(0x30, 16, 3, 0x01) /*!< full swj enabled (jtag-dp + sw-dp) but without jtrst */
#define SWJTAG_GMUX_010 IOMUX_MAKE_VALUE(0x30, 16, 3, 0x02) /*!< jtag-dp disabled and sw-dp enabled */
#define SWJTAG_GMUX_100 IOMUX_MAKE_VALUE(0x30, 16, 3, 0x04) /*!< full swj disabled (jtag-dp + sw-dp) */
#define PD01_GMUX IOMUX_MAKE_VALUE(0x30, 20, 1, 0x01) /*!< pd0/pd1 mapping on osc_in/osc_out */
/**
* @}
*/
/** @defgroup IOMUX_map8_definition
* @brief iomux map8 definitions
* @{
*/
#define TMR1_BK1_CMP_GMUX_10 IOMUX_MAKE_VALUE(0x34, 0, 2, 0x02) /*!< cmp tmr1_bpr1 connect tmr1 bk1 */
#define TMR1_BK1_CMP_GMUX_11 IOMUX_MAKE_VALUE(0x34, 0, 2, 0x03) /*!< cmp tmr1_bpr1 and io connect tmr1 bk1 */
#define TMR1_CH1_CMP_GMUX_10 IOMUX_MAKE_VALUE(0x34, 2, 2, 0x02) /*!< cmp connect tmr1 ch1 */
#define TMR1_CH1_CMP_GMUX_11 IOMUX_MAKE_VALUE(0x34, 2, 2, 0x03) /*!< cmp and io connect tmr1 ch1 */
#define TMR2_CH4_CMP_GMUX_10 IOMUX_MAKE_VALUE(0x34, 4, 2, 0x02) /*!< cmp connect tmr2 ch4 */
#define TMR2_CH4_CMP_GMUX_11 IOMUX_MAKE_VALUE(0x34, 4, 2, 0x03) /*!< cmp and io connect tmr2 ch4 */
#define TMR3_CH1_CMP_GMUX_10 IOMUX_MAKE_VALUE(0x34, 6, 2, 0x02) /*!< cmp connect tmr3 ch1 */
#define TMR3_CH1_CMP_GMUX_11 IOMUX_MAKE_VALUE(0x34, 6, 2, 0x03) /*!< cmp and io connect tmr3 ch1 */
/**
* @}
*/
/** @defgroup GPIO_exported_types
* @{
*/
/**
* @brief gpio mode select
*/
typedef enum
{
GPIO_MODE_INPUT = 0x00, /*!< gpio input mode */
GPIO_MODE_OUTPUT = 0x10, /*!< gpio output mode */
GPIO_MODE_MUX = 0x08, /*!< gpio mux function mode */
GPIO_MODE_ANALOG = 0x03 /*!< gpio analog in/out mode */
} gpio_mode_type;
/**
* @brief gpio output drive strength select
*/
typedef enum
{
GPIO_DRIVE_STRENGTH_STRONGER = 0x01, /*!< stronger sourcing/sinking strength */
GPIO_DRIVE_STRENGTH_MODERATE = 0x02, /*!< moderate sourcing/sinking strength */
GPIO_DRIVE_STRENGTH_MAXIMUM = 0x03 /*!< maximum sourcing/sinking strength */
} gpio_drive_type;
/**
* @brief gpio output type
*/
typedef enum
{
GPIO_OUTPUT_PUSH_PULL = 0x00, /*!< output push-pull */
GPIO_OUTPUT_OPEN_DRAIN = 0x04 /*!< output open-drain */
} gpio_output_type;
/**
* @brief gpio pull type
*/
typedef enum
{
GPIO_PULL_NONE = 0x0004, /*!< floating for input, no pull for output */
GPIO_PULL_UP = 0x0018, /*!< pull-up */
GPIO_PULL_DOWN = 0x0028 /*!< pull-down */
} gpio_pull_type;
/**
* @brief gpio pins source type
*/
typedef enum
{
GPIO_PINS_SOURCE0 = 0x00, /*!< gpio pins source number 0 */
GPIO_PINS_SOURCE1 = 0x01, /*!< gpio pins source number 1 */
GPIO_PINS_SOURCE2 = 0x02, /*!< gpio pins source number 2 */
GPIO_PINS_SOURCE3 = 0x03, /*!< gpio pins source number 3 */
GPIO_PINS_SOURCE4 = 0x04, /*!< gpio pins source number 4 */
GPIO_PINS_SOURCE5 = 0x05, /*!< gpio pins source number 5 */
GPIO_PINS_SOURCE6 = 0x06, /*!< gpio pins source number 6 */
GPIO_PINS_SOURCE7 = 0x07, /*!< gpio pins source number 7 */
GPIO_PINS_SOURCE8 = 0x08, /*!< gpio pins source number 8 */
GPIO_PINS_SOURCE9 = 0x09, /*!< gpio pins source number 9 */
GPIO_PINS_SOURCE10 = 0x0A, /*!< gpio pins source number 10 */
GPIO_PINS_SOURCE11 = 0x0B, /*!< gpio pins source number 11 */
GPIO_PINS_SOURCE12 = 0x0C, /*!< gpio pins source number 12 */
GPIO_PINS_SOURCE13 = 0x0D, /*!< gpio pins source number 13 */
GPIO_PINS_SOURCE14 = 0x0E, /*!< gpio pins source number 14 */
GPIO_PINS_SOURCE15 = 0x0F /*!< gpio pins source number 15 */
} gpio_pins_source_type;
/**
* @brief gpio port source type
*/
typedef enum
{
GPIO_PORT_SOURCE_GPIOA = 0x00, /*!< gpio port source gpioa */
GPIO_PORT_SOURCE_GPIOB = 0x01, /*!< gpio port source gpiob */
GPIO_PORT_SOURCE_GPIOC = 0x02, /*!< gpio port source gpioc */
GPIO_PORT_SOURCE_GPIOD = 0x03, /*!< gpio port source gpiod */
GPIO_PORT_SOURCE_GPIOF = 0x05, /*!< gpio port source gpiof */
} gpio_port_source_type;
/**
* @brief gpio init type
*/
typedef struct
{
uint32_t gpio_pins; /*!< pins number selection */
gpio_output_type gpio_out_type; /*!< output type selection */
gpio_pull_type gpio_pull; /*!< pull type selection */
gpio_mode_type gpio_mode; /*!< mode selection */
gpio_drive_type gpio_drive_strength; /*!< drive strength selection */
} gpio_init_type;
/**
* @brief type define gpio register all
*/
typedef struct
{
/**
* @brief gpio cfglr register, offset:0x00
*/
union
{
__IO uint32_t cfglr;
struct
{
__IO uint32_t iomc0 : 2; /* [1:0] */
__IO uint32_t iofc0 : 2; /* [3:2] */
__IO uint32_t iomc1 : 2; /* [5:4] */
__IO uint32_t iofc1 : 2; /* [7:6] */
__IO uint32_t iomc2 : 2; /* [9:8] */
__IO uint32_t iofc2 : 2; /* [11:10] */
__IO uint32_t iomc3 : 2; /* [13:12] */
__IO uint32_t iofc3 : 2; /* [15:14] */
__IO uint32_t iomc4 : 2; /* [17:16] */
__IO uint32_t iofc4 : 2; /* [19:18] */
__IO uint32_t iomc5 : 2; /* [21:20] */
__IO uint32_t iofc5 : 2; /* [23:22] */
__IO uint32_t iomc6 : 2; /* [25:24] */
__IO uint32_t iofc6 : 2; /* [27:26] */
__IO uint32_t iomc7 : 2; /* [29:28] */
__IO uint32_t iofc7 : 2; /* [31:30] */
} cfglr_bit;
};
/**
* @brief gpio cfghr register, offset:0x04
*/
union
{
__IO uint32_t cfghr;
struct
{
__IO uint32_t iomc8 : 2; /* [1:0] */
__IO uint32_t iofc8 : 2; /* [3:2] */
__IO uint32_t iomc9 : 2; /* [5:4] */
__IO uint32_t iofc9 : 2; /* [7:6] */
__IO uint32_t iomc10 : 2; /* [9:8] */
__IO uint32_t iofc10 : 2; /* [11:10] */
__IO uint32_t iomc11 : 2; /* [13:12] */
__IO uint32_t iofc11 : 2; /* [15:14] */
__IO uint32_t iomc12 : 2; /* [17:16] */
__IO uint32_t iofc12 : 2; /* [19:18] */
__IO uint32_t iomc13 : 2; /* [21:20] */
__IO uint32_t iofc13 : 2; /* [23:22] */
__IO uint32_t iomc14 : 2; /* [25:24] */
__IO uint32_t iofc14 : 2; /* [27:26] */
__IO uint32_t iomc15 : 2; /* [29:28] */
__IO uint32_t iofc15 : 2; /* [31:30] */
} cfghr_bit;
};
/**
* @brief gpio idt register, offset:0x08
*/
union
{
__IO uint32_t idt;
struct
{
__IO uint32_t idt0 : 1; /* [0] */
__IO uint32_t idt1 : 1; /* [1] */
__IO uint32_t idt2 : 1; /* [2] */
__IO uint32_t idt3 : 1; /* [3] */
__IO uint32_t idt4 : 1; /* [4] */
__IO uint32_t idt5 : 1; /* [5] */
__IO uint32_t idt6 : 1; /* [6] */
__IO uint32_t idt7 : 1; /* [7] */
__IO uint32_t idt8 : 1; /* [8] */
__IO uint32_t idt9 : 1; /* [9] */
__IO uint32_t idt10 : 1; /* [10] */
__IO uint32_t idt11 : 1; /* [11] */
__IO uint32_t idt12 : 1; /* [12] */
__IO uint32_t idt13 : 1; /* [13] */
__IO uint32_t idt14 : 1; /* [14] */
__IO uint32_t idt15 : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} idt_bit;
};
/**
* @brief gpio odt register, offset:0x0C
*/
union
{
__IO uint32_t odt;
struct
{
__IO uint32_t odt0 : 1; /* [0] */
__IO uint32_t odt1 : 1; /* [1] */
__IO uint32_t odt2 : 1; /* [2] */
__IO uint32_t odt3 : 1; /* [3] */
__IO uint32_t odt4 : 1; /* [4] */
__IO uint32_t odt5 : 1; /* [5] */
__IO uint32_t odt6 : 1; /* [6] */
__IO uint32_t odt7 : 1; /* [7] */
__IO uint32_t odt8 : 1; /* [8] */
__IO uint32_t odt9 : 1; /* [9] */
__IO uint32_t odt10 : 1; /* [10] */
__IO uint32_t odt11 : 1; /* [11] */
__IO uint32_t odt12 : 1; /* [12] */
__IO uint32_t odt13 : 1; /* [13] */
__IO uint32_t odt14 : 1; /* [14] */
__IO uint32_t odt15 : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} odt_bit;
};
/**
* @brief gpio scr register, offset:0x10
*/
union
{
__IO uint32_t scr;
struct
{
__IO uint32_t iosb0 : 1; /* [0] */
__IO uint32_t iosb1 : 1; /* [1] */
__IO uint32_t iosb2 : 1; /* [2] */
__IO uint32_t iosb3 : 1; /* [3] */
__IO uint32_t iosb4 : 1; /* [4] */
__IO uint32_t iosb5 : 1; /* [5] */
__IO uint32_t iosb6 : 1; /* [6] */
__IO uint32_t iosb7 : 1; /* [7] */
__IO uint32_t iosb8 : 1; /* [8] */
__IO uint32_t iosb9 : 1; /* [9] */
__IO uint32_t iosb10 : 1; /* [10] */
__IO uint32_t iosb11 : 1; /* [11] */
__IO uint32_t iosb12 : 1; /* [12] */
__IO uint32_t iosb13 : 1; /* [13] */
__IO uint32_t iosb14 : 1; /* [14] */
__IO uint32_t iosb15 : 1; /* [15] */
__IO uint32_t iocb0 : 1; /* [16] */
__IO uint32_t iocb1 : 1; /* [17] */
__IO uint32_t iocb2 : 1; /* [18] */
__IO uint32_t iocb3 : 1; /* [19] */
__IO uint32_t iocb4 : 1; /* [20] */
__IO uint32_t iocb5 : 1; /* [21] */
__IO uint32_t iocb6 : 1; /* [22] */
__IO uint32_t iocb7 : 1; /* [23] */
__IO uint32_t iocb8 : 1; /* [24] */
__IO uint32_t iocb9 : 1; /* [25] */
__IO uint32_t iocb10 : 1; /* [26] */
__IO uint32_t iocb11 : 1; /* [27] */
__IO uint32_t iocb12 : 1; /* [28] */
__IO uint32_t iocb13 : 1; /* [29] */
__IO uint32_t iocb14 : 1; /* [30] */
__IO uint32_t iocb15 : 1; /* [31] */
} scr_bit;
};
/**
* @brief gpio clr register, offset:0x14
*/
union
{
__IO uint32_t clr;
struct
{
__IO uint32_t iocb0 : 1; /* [0] */
__IO uint32_t iocb1 : 1; /* [1] */
__IO uint32_t iocb2 : 1; /* [2] */
__IO uint32_t iocb3 : 1; /* [3] */
__IO uint32_t iocb4 : 1; /* [4] */
__IO uint32_t iocb5 : 1; /* [5] */
__IO uint32_t iocb6 : 1; /* [6] */
__IO uint32_t iocb7 : 1; /* [7] */
__IO uint32_t iocb8 : 1; /* [8] */
__IO uint32_t iocb9 : 1; /* [9] */
__IO uint32_t iocb10 : 1; /* [10] */
__IO uint32_t iocb11 : 1; /* [11] */
__IO uint32_t iocb12 : 1; /* [12] */
__IO uint32_t iocb13 : 1; /* [13] */
__IO uint32_t iocb14 : 1; /* [14] */
__IO uint32_t iocb15 : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} clr_bit;
};
/**
* @brief gpio wpr register, offset:0x18
*/
union
{
__IO uint32_t wpr;
struct
{
__IO uint32_t wpen0 : 1; /* [0] */
__IO uint32_t wpen1 : 1; /* [1] */
__IO uint32_t wpen2 : 1; /* [2] */
__IO uint32_t wpen3 : 1; /* [3] */
__IO uint32_t wpen4 : 1; /* [4] */
__IO uint32_t wpen5 : 1; /* [5] */
__IO uint32_t wpen6 : 1; /* [6] */
__IO uint32_t wpen7 : 1; /* [7] */
__IO uint32_t wpen8 : 1; /* [8] */
__IO uint32_t wpen9 : 1; /* [9] */
__IO uint32_t wpen10 : 1; /* [10] */
__IO uint32_t wpen11 : 1; /* [11] */
__IO uint32_t wpen12 : 1; /* [12] */
__IO uint32_t wpen13 : 1; /* [13] */
__IO uint32_t wpen14 : 1; /* [14] */
__IO uint32_t wpen15 : 1; /* [15] */
__IO uint32_t wpseq : 1; /* [16] */
__IO uint32_t reserved1 : 15;/* [31:17] */
} wpr_bit;
};
} gpio_type;
/**
* @brief type define iomux register all
*/
typedef struct
{
/**
* @brief mux event control register, offset:0x00
*/
union
{
__IO uint32_t evtout;
struct
{
__IO uint32_t selpin : 4; /* [3:0] */
__IO uint32_t selport : 3; /* [6:4] */
__IO uint32_t evoen : 1; /* [7] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} evtout_bit;
};
/**
* @brief iomux remap register, offset:0x04
*/
union
{
__IO uint32_t remap;
struct
{
__IO uint32_t spi1_mux_l : 1; /* [0] */
__IO uint32_t i2c1_mux : 1; /* [1] */
__IO uint32_t usart1_mux : 1; /* [2] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t usart3_mux : 2; /* [5:4] */
__IO uint32_t tmr1_mux : 2; /* [7:6] */
__IO uint32_t tmr2_mux : 2; /* [9:8] */
__IO uint32_t tmr3_mux : 2; /* [11:10] */
__IO uint32_t reserved2 : 1; /* [12] */
__IO uint32_t can_mux : 2; /* [14:13] */
__IO uint32_t pd01_mux : 1; /* [15] */
__IO uint32_t tmr5ch4_mux : 1; /* [16] */
__IO uint32_t adc1_extrgpre_mux : 1; /* [17] */
__IO uint32_t adc1_extrgord_mux : 1; /* [18] */
__IO uint32_t reserved3 : 5; /* [23:19] */
__IO uint32_t swjtag_conf : 3; /* [26:24] */
__IO uint32_t reserved4 : 4; /* [30:27] */
__IO uint32_t spi1_mux_h : 1; /* [31] */
} remap_bit;
};
/**
* @brief mux external interrupt configuration register 1, offset:0x08
*/
union
{
__IO uint32_t exintc1;
struct
{
__IO uint32_t exint0 : 4; /* [3:0] */
__IO uint32_t exint1 : 4; /* [7:4] */
__IO uint32_t exint2 : 4; /* [11:8] */
__IO uint32_t exint3 : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} exintc1_bit;
};
/**
* @brief mux external interrupt configuration register 2, offset:0x0c
*/
union
{
__IO uint32_t exintc2;
struct
{
__IO uint32_t exint4 : 4; /* [3:0] */
__IO uint32_t exint5 : 4; /* [7:4] */
__IO uint32_t exint6 : 4; /* [11:8] */
__IO uint32_t exint7 : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} exintc2_bit;
};
/**
* @brief mux external interrupt configuration register 3, offset:0x10
*/
union
{
__IO uint32_t exintc3;
struct
{
__IO uint32_t exint8 : 4; /* [3:0] */
__IO uint32_t exint9 : 4; /* [7:4] */
__IO uint32_t exint10 : 4; /* [11:8] */
__IO uint32_t exint11 : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} exintc3_bit;
};
/**
* @brief mux external interrupt configuration register 4, offset:0x14
*/
union
{
__IO uint32_t exintc4;
struct
{
__IO uint32_t exint12 : 4; /* [3:0] */
__IO uint32_t exint13 : 4; /* [7:4] */
__IO uint32_t exint14 : 4; /* [11:8] */
__IO uint32_t exint15 : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} exintc4_bit;
};
/**
* @brief iomux reserved1 register, offset:0x18
*/
__IO uint32_t reserved1;
/**
* @brief iomux remap register 2, offset:0x1C
*/
union
{
__IO uint32_t remap2;
struct
{
__IO uint32_t reserved1 : 26;/* [25:0] */
__IO uint32_t cmp_mux : 2; /* [27:26] */
__IO uint32_t reserved2 : 4; /* [31:28] */
} remap2_bit;
};
/**
* @brief iomux remap register 3, offset:0x20
*/
union
{
__IO uint32_t remap3;
struct
{
__IO uint32_t tmr9_gmux : 4; /* [3:0] */
__IO uint32_t tmr10_gmux : 4; /* [7:4] */
__IO uint32_t tmr11_gmux : 4; /* [11:8] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} remap3_bit;
};
/**
* @brief iomux remap register 4, offset:0x24
*/
union
{
__IO uint32_t remap4;
struct
{
__IO uint32_t tmr1_gmux : 4; /* [3:0] */
__IO uint32_t tmr2_gmux : 3; /* [6:4] */
__IO uint32_t reserved1 : 1; /* [7] */
__IO uint32_t tmr3_gmux : 4; /* [11:8] */
__IO uint32_t reserved2 : 4; /* [15:12] */
__IO uint32_t tmr5_gmux : 3; /* [18:16] */
__IO uint32_t tmr5ch4_gmux : 1; /* [19] */
__IO uint32_t reserved3 : 12;/* [31:20] */
} remap4_bit;
};
/**
* @brief iomux remap register 5, offset:0x28
*/
union
{
__IO uint32_t remap5;
struct
{
__IO uint32_t reserved1 : 4; /* [3:0] */
__IO uint32_t i2c1_gmux : 4; /* [7:4] */
__IO uint32_t i2c2_gmux : 4; /* [11:8] */
__IO uint32_t reserved2 : 4; /* [15:12] */
__IO uint32_t spi1_gmux : 4; /* [19:16] */
__IO uint32_t spi2_gmux : 4; /* [23:20] */
__IO uint32_t reserved3 : 8; /* [31:24] */
} remap5_bit;
};
/**
* @brief iomux remap register 6, offset:0x2C
*/
union
{
__IO uint32_t remap6;
struct
{
__IO uint32_t can1_gmux : 4; /* [3:0] */
__IO uint32_t reserved1 : 4; /* [7:4] */
__IO uint32_t sdio1_gmux : 4; /* [11:8] */
__IO uint32_t reserved2 : 4; /* [15:12] */
__IO uint32_t usart1_gmux : 4; /* [19:16] */
__IO uint32_t reserved3 : 4; /* [23:20] */
__IO uint32_t usart3_gmux : 4; /* [27:24] */
__IO uint32_t uart4_gmux : 4; /* [31:28] */
} remap6_bit;
};
/**
* @brief iomux remap register 7, offset:0x30
*/
union
{
__IO uint32_t remap7;
struct
{
__IO uint32_t reserved1 : 4; /* [3:0] */
__IO uint32_t adc1_etp_gmux : 1; /* [4] */
__IO uint32_t adc1_eto_gmux : 1; /* [5] */
__IO uint32_t reserved2 : 10;/* [15:6] */
__IO uint32_t swjtag_gmux : 3; /* [18:16] */
__IO uint32_t reserved3 : 1; /* [19] */
__IO uint32_t pd01_gmux : 1; /* [20] */
__IO uint32_t reserved4 : 11;/* [31:21] */
} remap7_bit;
};
/**
* @brief iomux remap register 8, offset:0x34
*/
union
{
__IO uint32_t remap8;
struct
{
__IO uint32_t tmr1_bk1_cmp_gmux : 2; /* [1:0] */
__IO uint32_t tmr1_ch1_cmp_gmux : 2; /* [3:2] */
__IO uint32_t tmr2_ch4_cmp_gmux : 2; /* [5:4] */
__IO uint32_t tmr3_ch1_cmp_gmux : 2; /* [7:6] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} remap8_bit;
};
} iomux_type;
/**
* @}
*/
#define GPIOA ((gpio_type *) GPIOA_BASE)
#define GPIOB ((gpio_type *) GPIOB_BASE)
#define GPIOC ((gpio_type *) GPIOC_BASE)
#define GPIOD ((gpio_type *) GPIOD_BASE)
#define GPIOF ((gpio_type *) GPIOF_BASE)
#define IOMUX ((iomux_type *) IOMUX_BASE)
/** @defgroup GPIO_exported_functions
* @{
*/
void gpio_reset(gpio_type *gpio_x);
void gpio_iomux_reset(void);
void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
void gpio_default_para_init(gpio_init_type *gpio_init_struct);
flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
uint16_t gpio_input_data_read(gpio_type *gpio_x);
flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
uint16_t gpio_output_data_read(gpio_type *gpio_x);
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value);
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source);
void gpio_event_output_enable(confirm_state new_state);
void gpio_pin_remap_config(uint32_t gpio_remap, confirm_state new_state);
void gpio_exint_line_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

400
libraries/drivers/inc/at32f415_i2c.h Normal file
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@@ -0,0 +1,400 @@
/**
**************************************************************************
* @file at32f415_i2c.h
* @brief at32f415 i2c header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_I2C_H
#define __AT32F415_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/** @defgroup I2C_sts1_flags_definition
* @brief i2c sts1 flag
* @{
*/
#define I2C_STARTF_FLAG ((uint32_t)0x00000001) /*!< i2c start condition generation complete flag */
#define I2C_ADDR7F_FLAG ((uint32_t)0x00000002) /*!< i2c 0~7 bit address match flag */
#define I2C_TDC_FLAG ((uint32_t)0x00000004) /*!< i2c transmit data complete flag */
#define I2C_ADDRHF_FLAG ((uint32_t)0x00000008) /*!< i2c master 9~8 bit address header match flag */
#define I2C_STOPF_FLAG ((uint32_t)0x00000010) /*!< i2c stop condition generation complete flag */
#define I2C_RDBF_FLAG ((uint32_t)0x00000040) /*!< i2c receive data buffer full flag */
#define I2C_TDBE_FLAG ((uint32_t)0x00000080) /*!< i2c transmit data buffer empty flag */
#define I2C_BUSERR_FLAG ((uint32_t)0x00000100) /*!< i2c bus error flag */
#define I2C_ARLOST_FLAG ((uint32_t)0x00000200) /*!< i2c arbitration lost flag */
#define I2C_ACKFAIL_FLAG ((uint32_t)0x00000400) /*!< i2c acknowledge failure flag */
#define I2C_OUF_FLAG ((uint32_t)0x00000800) /*!< i2c overflow or underflow flag */
#define I2C_PECERR_FLAG ((uint32_t)0x00001000) /*!< i2c pec receive error flag */
#define I2C_TMOUT_FLAG ((uint32_t)0x00004000) /*!< i2c smbus timeout flag */
#define I2C_ALERTF_FLAG ((uint32_t)0x00008000) /*!< i2c smbus alert flag */
/**
* @}
*/
/** @defgroup I2C_sts2_flags_definition
* @brief i2c sts2 flag
* @{
*/
#define I2C_TRMODE_FLAG ((uint32_t)0x10010000) /*!< i2c transmission mode */
#define I2C_BUSYF_FLAG ((uint32_t)0x10020000) /*!< i2c bus busy flag transmission mode */
#define I2C_DIRF_FLAG ((uint32_t)0x10040000) /*!< i2c transmission direction flag */
#define I2C_GCADDRF_FLAG ((uint32_t)0x10100000) /*!< i2c general call address received flag */
#define I2C_DEVADDRF_FLAG ((uint32_t)0x10200000) /*!< i2c smbus device address received flag */
#define I2C_HOSTADDRF_FLAG ((uint32_t)0x10400000) /*!< i2c smbus host address received flag */
#define I2C_ADDR2_FLAG ((uint32_t)0x10800000) /*!< i2c own address 2 received flag */
/**
* @}
*/
/** @defgroup I2C_interrupts_definition
* @brief i2c interrupt
* @{
*/
#define I2C_DATA_INT ((uint16_t)0x0400) /*!< i2c data transmission interrupt */
#define I2C_EVT_INT ((uint16_t)0x0200) /*!< i2c event interrupt */
#define I2C_ERR_INT ((uint16_t)0x0100) /*!< i2c error interrupt */
/**
* @}
*/
/** @defgroup I2C_exported_types
* @{
*/
/**
* @brief i2c master receiving mode acknowledge control
*/
typedef enum
{
I2C_MASTER_ACK_CURRENT = 0x00, /*!< acken bit acts on the current byte */
I2C_MASTER_ACK_NEXT = 0x01 /*!< acken bit acts on the next byte */
} i2c_master_ack_type;
/**
* @brief i2c pec position set
*/
typedef enum
{
I2C_PEC_POSITION_CURRENT = 0x00, /*!< the current byte is pec */
I2C_PEC_POSITION_NEXT = 0x01 /*!< the next byte is pec */
} i2c_pec_position_type;
/**
* @brief i2c smbus alert pin set
*/
typedef enum
{
I2C_SMBUS_ALERT_HIGH = 0x00, /*!< smbus alert pin set high */
I2C_SMBUS_ALERT_LOW = 0x01 /*!< smbus alert pin set low */
} i2c_smbus_alert_set_type;
/**
* @brief i2c smbus mode set
*/
typedef enum
{
I2C_SMBUS_MODE_DEVICE = 0x00, /*!< smbus device mode */
I2C_SMBUS_MODE_HOST = 0x01 /*!< smbus host mode */
} i2c_smbus_mode_set_type;
/**
* @brief i2c fast mode duty cycle
*/
typedef enum
{
I2C_FSMODE_DUTY_2_1 = 0x00, /*!< duty cycle is 2:1 in fast mode */
I2C_FSMODE_DUTY_16_9 = 0x01 /*!< duty cycle is 16:9 in fast mode */
} i2c_fsmode_duty_cycle_type;
/**
* @brief i2c address mode
*/
typedef enum
{
I2C_ADDRESS_MODE_7BIT = 0x00, /*!< 7bit address mode */
I2C_ADDRESS_MODE_10BIT = 0x01 /*!< 10bit address mode */
} i2c_address_mode_type;
/**
* @brief i2c address direction
*/
typedef enum
{
I2C_DIRECTION_TRANSMIT = 0x00, /*!< transmit mode */
I2C_DIRECTION_RECEIVE = 0x01 /*!< receive mode */
} i2c_direction_type;
/**
* @brief type define i2c register all
*/
typedef struct
{
/**
* @brief i2c ctrl1 register, offset:0x00
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t i2cen : 1; /* [0] */
__IO uint32_t permode : 1; /* [1] */
__IO uint32_t reserved1 : 1; /* [2] */
__IO uint32_t smbmode : 1; /* [3] */
__IO uint32_t arpen : 1; /* [4] */
__IO uint32_t pecen : 1; /* [5] */
__IO uint32_t gcaen : 1; /* [6] */
__IO uint32_t stretch : 1; /* [7] */
__IO uint32_t genstart : 1; /* [8] */
__IO uint32_t genstop : 1; /* [9] */
__IO uint32_t acken : 1; /* [10] */
__IO uint32_t mackctrl : 1; /* [11] */
__IO uint32_t pecten : 1; /* [12] */
__IO uint32_t smbalert : 1; /* [13] */
__IO uint32_t reserved2 : 1; /* [14] */
__IO uint32_t reset : 1; /* [15] */
__IO uint32_t reserved3 : 16;/* [31:16] */
} ctrl1_bit;
};
/**
* @brief i2c ctrl2 register, offset:0x04
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t clkfreq : 8; /* [7:0] */
__IO uint32_t errien : 1; /* [8] */
__IO uint32_t evtien : 1; /* [9] */
__IO uint32_t dataien : 1; /* [10] */
__IO uint32_t dmaen : 1; /* [11] */
__IO uint32_t dmaend : 1; /* [12] */
__IO uint32_t reserved1 : 19;/* [31:13] */
} ctrl2_bit;
};
/**
* @brief i2c oaddr1 register, offset:0x08
*/
union
{
__IO uint32_t oaddr1;
struct
{
__IO uint32_t addr1 : 10;/* [9:0] */
__IO uint32_t reserved1 : 5; /* [14:10] */
__IO uint32_t addr1mode : 1; /* [15] */
__IO uint32_t reserved2 : 16;/* [31:16] */
} oaddr1_bit;
};
/**
* @brief i2c oaddr2 register, offset:0x0C
*/
union
{
__IO uint32_t oaddr2;
struct
{
__IO uint32_t addr2en : 1; /* [0] */
__IO uint32_t addr2 : 7; /* [7:1] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} oaddr2_bit;
};
/**
* @brief i2c dt register, offset:0x10
*/
union
{
__IO uint32_t dt;
struct
{
__IO uint32_t dt : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} dt_bit;
};
/**
* @brief i2c sts1 register, offset:0x14
*/
union
{
__IO uint32_t sts1;
struct
{
__IO uint32_t startf : 1; /* [0] */
__IO uint32_t addr7f : 1; /* [1] */
__IO uint32_t tdc : 1; /* [2] */
__IO uint32_t addrhf : 1; /* [3] */
__IO uint32_t stopf : 1; /* [4] */
__IO uint32_t reserved1 : 1; /* [5] */
__IO uint32_t rdbf : 1; /* [6] */
__IO uint32_t tdbe : 1; /* [7] */
__IO uint32_t buserr : 1; /* [8] */
__IO uint32_t arlost : 1; /* [9] */
__IO uint32_t ackfail : 1; /* [10] */
__IO uint32_t ouf : 1; /* [11] */
__IO uint32_t pecerr : 1; /* [12] */
__IO uint32_t reserved2 : 1; /* [13] */
__IO uint32_t tmout : 1; /* [14] */
__IO uint32_t alertf : 1; /* [15] */
__IO uint32_t reserved3 : 16; /* [31:16] */
} sts1_bit;
};
/**
* @brief i2c sts2 register, offset:0x18
*/
union
{
__IO uint32_t sts2;
struct
{
__IO uint32_t trmode : 1; /* [0] */
__IO uint32_t busyf : 1; /* [1] */
__IO uint32_t dirf : 1; /* [2] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t gcaddrf : 1; /* [4] */
__IO uint32_t devaddrf : 1; /* [5] */
__IO uint32_t hostaddrf : 1; /* [6] */
__IO uint32_t addr2 : 1; /* [7] */
__IO uint32_t pecval : 8; /* [15:8] */
__IO uint32_t reserved2 : 16;/* [31:16] */
} sts2_bit;
};
/**
* @brief i2c clkctrl register, offset:0x1C
*/
union
{
__IO uint32_t clkctrl;
struct
{
__IO uint32_t speed : 12;/* [11:0] */
__IO uint32_t reserved1 : 2; /* [13:12] */
__IO uint32_t dutymode : 1; /* [14] */
__IO uint32_t speedmode : 1; /* [15] */
__IO uint32_t reserved2 : 16;/* [31:16] */
} clkctrl_bit;
};
/**
* @brief i2c tmrise register, offset:0x20
*/
union
{
__IO uint32_t tmrise;
struct
{
__IO uint32_t risetime : 6; /* [5:0] */
__IO uint32_t reserved1 : 26;/* [31:6] */
} tmrise_bit;
};
} i2c_type;
/**
* @}
*/
#define I2C1 ((i2c_type *) I2C1_BASE)
#define I2C2 ((i2c_type *) I2C2_BASE)
/** @defgroup I2C_exported_functions
* @{
*/
void i2c_reset(i2c_type *i2c_x);
void i2c_software_reset(i2c_type *i2c_x, confirm_state new_state);
void i2c_init(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty, uint32_t speed);
void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address);
void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address);
void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_smbus_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_fast_mode_duty_set(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty);
void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_master_receive_ack_set(i2c_type *i2c_x, i2c_master_ack_type pos);
void i2c_pec_position_set(i2c_type *i2c_x, i2c_pec_position_type pos);
void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_arp_mode_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_smbus_mode_set(i2c_type *i2c_x, i2c_smbus_mode_set_type mode);
void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level);
void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state);
uint8_t i2c_pec_value_get(i2c_type *i2c_x);
void i2c_dma_end_transfer_set(i2c_type *i2c_x, confirm_state new_state);
void i2c_dma_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_interrupt_enable(i2c_type *i2c_x, uint16_t source, confirm_state new_state);
void i2c_start_generate(i2c_type *i2c_x);
void i2c_stop_generate(i2c_type *i2c_x);
void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type direction);
void i2c_data_send(i2c_type *i2c_x, uint8_t data);
uint8_t i2c_data_receive(i2c_type *i2c_x);
flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag);
void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f415_misc.h
* @brief at32f415 misc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_MISC_H
#define __AT32F415_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup MISC
* @{
*/
/** @defgroup MISC_vector_table_base_address
* @{
*/
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< nvic vector table based ram address */
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< nvic vector table based flash address */
/**
* @}
*/
/** @defgroup MISC_exported_types
* @{
*/
/**
* @brief nvic interrupt priority group
*/
typedef enum
{
NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
} nvic_priority_group_type;
/**
* @brief nvic low power mode
*/
typedef enum
{
NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */
NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */
} nvic_lowpower_mode_type;
/**
* @brief systick clock source
*/
typedef enum
{
SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8 = ((uint32_t)0x00000000), /*!< systick clock source from core clock div8 */
SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV = ((uint32_t)0x00000004) /*!< systick clock source from core clock */
} systick_clock_source_type;
/**
* @}
*/
/** @defgroup MISC_exported_functions
* @{
*/
void nvic_system_reset(void);
void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority);
void nvic_irq_disable(IRQn_Type irqn);
void nvic_priority_group_config(nvic_priority_group_type priority_group);
void nvic_vector_table_set(uint32_t base, uint32_t offset);
void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
void systick_clock_source_config(systick_clock_source_type source);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f415_pwc.h
* @brief at32f415 pwc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_PWC_H
#define __AT32F415_PWC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup PWC
* @{
*/
/** @defgroup PWC_flags_definition
* @brief pwc flag
* @{
*/
#define PWC_WAKEUP_FLAG ((uint32_t)0x00000001) /*!< wakeup flag */
#define PWC_STANDBY_FLAG ((uint32_t)0x00000002) /*!< standby flag */
#define PWC_PVM_OUTPUT_FLAG ((uint32_t)0x00000004) /*!< pvm output flag */
/**
* @}
*/
/**
* @brief pwc wakeup pin num definition
*/
#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */
/** @defgroup PWC_exported_types
* @{
*/
/**
* @brief pwc pvm voltage type
*/
typedef enum
{
PWC_PVM_VOLTAGE_2V3 = 0x01, /*!< power voltage monitoring boundary 2.3v */
PWC_PVM_VOLTAGE_2V4 = 0x02, /*!< power voltage monitoring boundary 2.4v */
PWC_PVM_VOLTAGE_2V5 = 0x03, /*!< power voltage monitoring boundary 2.5v */
PWC_PVM_VOLTAGE_2V6 = 0x04, /*!< power voltage monitoring boundary 2.6v */
PWC_PVM_VOLTAGE_2V7 = 0x05, /*!< power voltage monitoring boundary 2.7v */
PWC_PVM_VOLTAGE_2V8 = 0x06, /*!< power voltage monitoring boundary 2.8v */
PWC_PVM_VOLTAGE_2V9 = 0x07 /*!< power voltage monitoring boundary 2.9v */
} pwc_pvm_voltage_type;
/**
* @brief pwc sleep enter type
*/
typedef enum
{
PWC_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter sleep mode */
PWC_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter sleep mode */
} pwc_sleep_enter_type;
/**
* @brief pwc deep sleep enter type
*/
typedef enum
{
PWC_DEEP_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter deepsleep mode */
PWC_DEEP_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter deepsleep mode */
} pwc_deep_sleep_enter_type;
/**
* @brief pwc regulator type
*/
typedef enum
{
PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */
PWC_REGULATOR_LOW_POWER = 0x01 /*!< voltage regulator state low power when deepsleep mode */
} pwc_regulator_type;
/**
* @brief type define pwc register all
*/
typedef struct
{
/**
* @brief pwc ctrl register, offset:0x00
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t vrsel : 1; /* [0] */
__IO uint32_t lpsel : 1; /* [1] */
__IO uint32_t clswef : 1; /* [2] */
__IO uint32_t clsef : 1; /* [3] */
__IO uint32_t pvmen : 1; /* [4] */
__IO uint32_t pvmsel : 3; /* [7:5] */
__IO uint32_t bpwen : 1; /* [8] */
__IO uint32_t reserved1 : 23;/* [31:9] */
} ctrl_bit;
};
/**
* @brief pwc ctrlsts register, offset:0x04
*/
union
{
__IO uint32_t ctrlsts;
struct
{
__IO uint32_t swef : 1; /* [0] */
__IO uint32_t sef : 1; /* [1] */
__IO uint32_t pvmof : 1; /* [2] */
__IO uint32_t reserved1 : 5; /* [7:3] */
__IO uint32_t swpen : 1; /* [8] */
__IO uint32_t reserved2 : 23;/* [31:9] */
} ctrlsts_bit;
};
} pwc_type;
/**
* @}
*/
#define PWC ((pwc_type *) PWC_BASE)
/** @defgroup PWC_exported_functions
* @{
*/
void pwc_reset(void);
void pwc_battery_powered_domain_access(confirm_state new_state);
void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
void pwc_power_voltage_monitor_enable(confirm_state new_state);
void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
void pwc_flag_clear(uint32_t pwc_flag);
flag_status pwc_flag_get(uint32_t pwc_flag);
void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);
void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter);
void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator);
void pwc_standby_mode_enter(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f415_sdio.h
* @brief at32f415 sdio header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_SDIO_H
#define __AT32F415_SDIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup SDIO
* @{
*/
/** @defgroup SDIO_interrupts_definition
* @brief sdio interrupt
* @{
*/
#define SDIO_CMDFAIL_INT ((uint32_t)0x00000001) /*!< command response received check failed interrupt */
#define SDIO_DTFAIL_INT ((uint32_t)0x00000002) /*!< data block sent/received check failed interrupt */
#define SDIO_CMDTIMEOUT_INT ((uint32_t)0x00000004) /*!< command response timerout interrupt */
#define SDIO_DTTIMEOUT_INT ((uint32_t)0x00000008) /*!< data timeout interrupt */
#define SDIO_TXERRU_INT ((uint32_t)0x00000010) /*!< transmit underrun error interrupt */
#define SDIO_RXERRO_INT ((uint32_t)0x00000020) /*!< received overrun error interrupt */
#define SDIO_CMDRSPCMPL_INT ((uint32_t)0x00000040) /*!< command response received interrupt */
#define SDIO_CMDCMPL_INT ((uint32_t)0x00000080) /*!< command sent interrupt */
#define SDIO_DTCMP_INT ((uint32_t)0x00000100) /*!< data sent interrupt */
#define SDIO_SBITERR_INT ((uint32_t)0x00000200) /*!< start bit not detected on data bus interrupt */
#define SDIO_DTBLKCMPL_INT ((uint32_t)0x00000400) /*!< data block sent/received interrupt */
#define SDIO_DOCMD_INT ((uint32_t)0x00000800) /*!< command transfer in progress interrupt */
#define SDIO_DOTX_INT ((uint32_t)0x00001000) /*!< data transmit in progress interrupt */
#define SDIO_DORX_INT ((uint32_t)0x00002000) /*!< data receive in progress interrupt */
#define SDIO_TXBUFH_INT ((uint32_t)0x00004000) /*!< transmit buf half empty interrupt */
#define SDIO_RXBUFH_INT ((uint32_t)0x00008000) /*!< receive buf half full interrupt */
#define SDIO_TXBUFF_INT ((uint32_t)0x00010000) /*!< transmit buf full interrupt */
#define SDIO_RXBUFF_INT ((uint32_t)0x00020000) /*!< receive buf full interrupt */
#define SDIO_TXBUFE_INT ((uint32_t)0x00040000) /*!< transmit buf empty interrupt */
#define SDIO_RXBUFE_INT ((uint32_t)0x00080000) /*!< receive buf empty interrupt */
#define SDIO_TXBUF_INT ((uint32_t)0x00100000) /*!< data available in transmit interrupt */
#define SDIO_RXBUF_INT ((uint32_t)0x00200000) /*!< data available in receive interrupt */
#define SDIO_SDIOIF_INT ((uint32_t)0x00400000) /*!< sdio interface received interrupt */
/**
* @}
*/
/** @defgroup SDIO_flags_definition
* @brief sdio flag
* @{
*/
#define SDIO_CMDFAIL_FLAG ((uint32_t)0x00000001) /*!< command response received check failed flag */
#define SDIO_DTFAIL_FLAG ((uint32_t)0x00000002) /*!< data block sent/received check failed flag */
#define SDIO_CMDTIMEOUT_FLAG ((uint32_t)0x00000004) /*!< command response timerout flag */
#define SDIO_DTTIMEOUT_FLAG ((uint32_t)0x00000008) /*!< data timeout flag */
#define SDIO_TXERRU_FLAG ((uint32_t)0x00000010) /*!< transmit underrun error flag */
#define SDIO_RXERRO_FLAG ((uint32_t)0x00000020) /*!< received overrun error flag */
#define SDIO_CMDRSPCMPL_FLAG ((uint32_t)0x00000040) /*!< command response received flag */
#define SDIO_CMDCMPL_FLAG ((uint32_t)0x00000080) /*!< command sent flag */
#define SDIO_DTCMPL_FLAG ((uint32_t)0x00000100) /*!< data sent flag */
#define SDIO_SBITERR_FLAG ((uint32_t)0x00000200) /*!< start bit not detected on data bus flag */
#define SDIO_DTBLKCMPL_FLAG ((uint32_t)0x00000400) /*!< data block sent/received flag */
#define SDIO_DOCMD_FLAG ((uint32_t)0x00000800) /*!< command transfer in progress flag */
#define SDIO_DOTX_FLAG ((uint32_t)0x00001000) /*!< data transmit in progress flag */
#define SDIO_DORX_FLAG ((uint32_t)0x00002000) /*!< data receive in progress flag */
#define SDIO_TXBUFH_FLAG ((uint32_t)0x00004000) /*!< transmit buf half empty flag */
#define SDIO_RXBUFH_FLAG ((uint32_t)0x00008000) /*!< receive buf half full flag */
#define SDIO_TXBUFF_FLAG ((uint32_t)0x00010000) /*!< transmit buf full flag */
#define SDIO_RXBUFF_FLAG ((uint32_t)0x00020000) /*!< receive buf full flag */
#define SDIO_TXBUFE_FLAG ((uint32_t)0x00040000) /*!< transmit buf empty flag */
#define SDIO_RXBUFE_FLAG ((uint32_t)0x00080000) /*!< receive buf empty flag */
#define SDIO_TXBUF_FLAG ((uint32_t)0x00100000) /*!< data available in transmit flag */
#define SDIO_RXBUF_FLAG ((uint32_t)0x00200000) /*!< data available in receive flag */
#define SDIO_SDIOIF_FLAG ((uint32_t)0x00400000) /*!< sdio interface received flag */
/**
* @}
*/
/** @defgroup SDIO_exported_types
* @{
*/
/**
* @brief sdio power state
*/
typedef enum
{
SDIO_POWER_OFF = 0x00, /*!< power-off, clock to card is stopped */
SDIO_POWER_ON = 0x03 /*!< power-on, the card is clocked */
} sdio_power_state_type;
/**
* @brief sdio edge phase
*/
typedef enum
{
SDIO_CLOCK_EDGE_RISING = 0x00, /*!< sdio bus clock generated on the rising edge of the master clock */
SDIO_CLOCK_EDGE_FALLING = 0x01 /*!< sdio bus clock generated on the falling edge of the master clock */
} sdio_edge_phase_type;
/**
* @brief sdio bus width
*/
typedef enum
{
SDIO_BUS_WIDTH_D1 = 0x00, /*!< sdio wide bus select 1-bit */
SDIO_BUS_WIDTH_D4 = 0x01, /*!< sdio wide bus select 4-bit */
SDIO_BUS_WIDTH_D8 = 0x02 /*!< sdio wide bus select 8-bit */
} sdio_bus_width_type;
/**
* @brief sdio response type
*/
typedef enum
{
SDIO_RESPONSE_NO = 0x00, /*!< no response */
SDIO_RESPONSE_SHORT = 0x01, /*!< short response */
SDIO_RESPONSE_LONG = 0x03 /*!< long response */
} sdio_reponse_type;
/**
* @brief sdio wait type
*/
typedef enum
{
SDIO_WAIT_FOR_NO = 0x00, /*!< no wait */
SDIO_WAIT_FOR_INT = 0x01, /*!< wait interrupt request */
SDIO_WAIT_FOR_PEND = 0x02 /*!< wait end of transfer */
} sdio_wait_type;
/**
* @brief sdio response register index
*/
typedef enum
{
SDIO_RSP1_INDEX = 0x00, /*!< response index 1, corresponding to sdio_rsp register 1 */
SDIO_RSP2_INDEX = 0x01, /*!< response index 2, corresponding to sdio_rsp register 2 */
SDIO_RSP3_INDEX = 0x02, /*!< response index 3, corresponding to sdio_rsp register 3 */
SDIO_RSP4_INDEX = 0x03 /*!< response index 4, corresponding to sdio_rsp register 4 */
} sdio_rsp_index_type;
/**
* @brief sdio data block size
*/
typedef enum
{
SDIO_DATA_BLOCK_SIZE_1B = 0x00, /*!< data block size 1 byte */
SDIO_DATA_BLOCK_SIZE_2B = 0x01, /*!< data block size 2 bytes */
SDIO_DATA_BLOCK_SIZE_4B = 0x02, /*!< data block size 4 bytes */
SDIO_DATA_BLOCK_SIZE_8B = 0x03, /*!< data block size 8 bytes */
SDIO_DATA_BLOCK_SIZE_16B = 0x04, /*!< data block size 16 bytes */
SDIO_DATA_BLOCK_SIZE_32B = 0x05, /*!< data block size 32 bytes */
SDIO_DATA_BLOCK_SIZE_64B = 0x06, /*!< data block size 64 bytes */
SDIO_DATA_BLOCK_SIZE_128B = 0x07, /*!< data block size 128 bytes */
SDIO_DATA_BLOCK_SIZE_256B = 0x08, /*!< data block size 256 bytes */
SDIO_DATA_BLOCK_SIZE_512B = 0x09, /*!< data block size 512 bytes */
SDIO_DATA_BLOCK_SIZE_1024B = 0x0A, /*!< data block size 1024 bytes */
SDIO_DATA_BLOCK_SIZE_2048B = 0x0B, /*!< data block size 2048 bytes */
SDIO_DATA_BLOCK_SIZE_4096B = 0x0C, /*!< data block size 4096 bytes */
SDIO_DATA_BLOCK_SIZE_8192B = 0x0D, /*!< data block size 8192 bytes */
SDIO_DATA_BLOCK_SIZE_16384B = 0x0E /*!< data block size 16384 bytes */
} sdio_block_size_type;
/**
* @brief sdio data transfer mode
*/
typedef enum
{
SDIO_DATA_BLOCK_TRANSFER = 0x00, /*!< the sdio block transfer mode */
SDIO_DATA_STREAM_TRANSFER = 0x01 /*!< the sdio stream transfer mode */
} sdio_transfer_mode_type;
/**
* @brief sdio data transfer direction
*/
typedef enum
{
SDIO_DATA_TRANSFER_TO_CARD = 0x00, /*!< the sdio controller write */
SDIO_DATA_TRANSFER_TO_CONTROLLER = 0x01 /*!< the sdio controller read */
} sdio_transfer_direction_type;
/**
* @brief sdio read wait mode
*/
typedef enum
{
SDIO_READ_WAIT_CONTROLLED_BY_D2 = 0x00, /*!< the sdio read wait on data2 line */
SDIO_READ_WAIT_CONTROLLED_BY_CK = 0x01 /*!< the sdio read wait on clock line */
} sdio_read_wait_mode_type;
/**
* @brief sdio command structure
*/
typedef struct
{
uint32_t argument; /*!< the sdio command argument is sent to a card as part of command message */
uint8_t cmd_index; /*!< the sdio command index */
sdio_reponse_type rsp_type; /*!< the sdio response type */
sdio_wait_type wait_type; /*!< the sdio wait for interrupt request is enabled or disable */
} sdio_command_struct_type;
/**
* @brief sdio data structure
*/
typedef struct
{
uint32_t timeout; /*!< the sdio data timeout period in car bus clock periods */
uint32_t data_length; /*!< the sdio data length */
sdio_block_size_type block_size; /*!< the sdio data block size of block transfer mode */
sdio_transfer_mode_type transfer_mode; /*!< the sdio transfer mode, block or stream */
sdio_transfer_direction_type transfer_direction; /*!< the sdio data transfer direction */
} sdio_data_struct_type;
/**
* @brief type define sdio register all
*/
typedef struct
{
/**
* @brief sdio pwrctrl register, offset:0x00
*/
union
{
__IO uint32_t pwrctrl;
struct
{
__IO uint32_t ps : 2; /* [1:0] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} pwrctrl_bit;
};
/**
* @brief sdio clkctrl register, offset:0x04
*/
union
{
__IO uint32_t clkctrl;
struct
{
__IO uint32_t clkdiv_l : 8; /* [7:0] */
__IO uint32_t clkoen : 1; /* [8] */
__IO uint32_t pwrsven : 1; /* [9] */
__IO uint32_t bypsen : 1; /* [10] */
__IO uint32_t busws : 2; /* [12:11] */
__IO uint32_t clkegs : 1; /* [13] */
__IO uint32_t hfcen : 1; /* [14] */
__IO uint32_t clkdiv_h : 2; /* [16:15] */
__IO uint32_t reserved1 : 15;/* [31:17] */
} clkctrl_bit;
};
/**
* @brief sdio argu register, offset:0x08
*/
union
{
__IO uint32_t argu;
struct
{
__IO uint32_t argu : 32;/* [31:0] */
} argu_bit;
};
/**
* @brief sdio cmdctrl register, offset:0x0C
*/
union
{
__IO uint32_t cmdctrl;
struct
{
__IO uint32_t cmdidx : 6; /* [5:0] */
__IO uint32_t rspwt : 2; /* [7:6] */
__IO uint32_t intwt : 1; /* [8] */
__IO uint32_t pndwt : 1; /* [9] */
__IO uint32_t ccsmen : 1; /* [10] */
__IO uint32_t iosusp : 1; /* [11] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} cmdctrl_bit;
};
/**
* @brief sdio rspcmd register, offset:0x10
*/
union
{
__IO uint32_t rspcmd;
struct
{
__IO uint32_t rspcmd : 6; /* [5:0] */
__IO uint32_t reserved1 : 26;/* [31:6] */
} rspcmd_bit;
};
/**
* @brief sdio rsp1 register, offset:0x14
*/
union
{
__IO uint32_t rsp1;
struct
{
__IO uint32_t cardsts1 : 32;/* [31:0] */
} rsp1_bit;
};
/**
* @brief sdio rsp2 register, offset:0x18
*/
union
{
__IO uint32_t rsp2;
struct
{
__IO uint32_t cardsts2 : 32;/* [31:0] */
} rsp2_bit;
};
/**
* @brief sdio rsp3 register, offset:0x1C
*/
union
{
__IO uint32_t rsp3;
struct
{
__IO uint32_t cardsts3 : 32;/* [31:0] */
} rsp3_bit;
};
/**
* @brief sdio rsp4 register, offset:0x20
*/
union
{
__IO uint32_t rsp4;
struct
{
__IO uint32_t cardsts4 : 32;/* [31:0] */
} rsp4_bit;
};
/**
* @brief sdio dttmr register, offset:0x24
*/
union
{
__IO uint32_t dttmr;
struct
{
__IO uint32_t timeout : 32;/* [31:0] */
} dttmr_bit;
};
/**
* @brief sdio dtlen register, offset:0x28
*/
union
{
__IO uint32_t dtlen;
struct
{
__IO uint32_t dtlen : 25;/* [24:0] */
__IO uint32_t reserved1 : 7; /* [31:25] */
} dtlen_bit;
};
/**
* @brief sdio dtctrl register, offset:0x2C
*/
union
{
__IO uint32_t dtctrl;
struct
{
__IO uint32_t tfren : 1; /* [0] */
__IO uint32_t tfrdir : 1; /* [1] */
__IO uint32_t tfrmode : 1; /* [2] */
__IO uint32_t dmaen : 1; /* [3] */
__IO uint32_t blksize : 4; /* [7:4] */
__IO uint32_t rdwtstart : 1; /* [8] */
__IO uint32_t rdwtstop : 1; /* [9] */
__IO uint32_t rdwtmode : 1; /* [10] */
__IO uint32_t ioen : 1; /* [11] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} dtctrl_bit;
};
/**
* @brief sdio dtcnt register, offset:0x30
*/
union
{
__IO uint32_t dtcnt;
struct
{
__IO uint32_t cnt : 25;/* [24:0] */
__IO uint32_t reserved1 : 7; /* [31:25] */
} dtcnt_bit;
};
/**
* @brief sdio sts register, offset:0x34
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t cmdfail : 1; /* [0] */
__IO uint32_t dtfail : 1; /* [1] */
__IO uint32_t cmdtimeout : 1; /* [2] */
__IO uint32_t dttimeout : 1; /* [3] */
__IO uint32_t txerru : 1; /* [4] */
__IO uint32_t rxerro : 1; /* [5] */
__IO uint32_t cmdrspcmpl : 1; /* [6] */
__IO uint32_t cmdcmpl : 1; /* [7] */
__IO uint32_t dtcmpl : 1; /* [8] */
__IO uint32_t sbiterr : 1; /* [9] */
__IO uint32_t dtblkcmpl : 1; /* [10] */
__IO uint32_t docmd : 1; /* [11] */
__IO uint32_t dotx : 1; /* [12] */
__IO uint32_t dorx : 1; /* [13] */
__IO uint32_t txbufh : 1; /* [14] */
__IO uint32_t rxbufh : 1; /* [15] */
__IO uint32_t txbuff : 1; /* [16] */
__IO uint32_t rxbuff : 1; /* [17] */
__IO uint32_t txbufe : 1; /* [18] */
__IO uint32_t rxbufe : 1; /* [19] */
__IO uint32_t txbuf : 1; /* [20] */
__IO uint32_t rxbuf : 1; /* [21] */
__IO uint32_t ioif : 1; /* [22] */
__IO uint32_t reserved1 : 9; /* [31:23] */
} sts_bit;
};
/**
* @brief sdio intclr register, offset:0x38
*/
union
{
__IO uint32_t intclr;
struct
{
__IO uint32_t cmdfail : 1; /* [0] */
__IO uint32_t dtfail : 1; /* [1] */
__IO uint32_t cmdtimeout : 1; /* [2] */
__IO uint32_t dttimeout : 1; /* [3] */
__IO uint32_t txerru : 1; /* [4] */
__IO uint32_t rxerro : 1; /* [5] */
__IO uint32_t cmdrspcmpl : 1; /* [6] */
__IO uint32_t cmdcmpl : 1; /* [7] */
__IO uint32_t dtcmpl : 1; /* [8] */
__IO uint32_t sbiterr : 1; /* [9] */
__IO uint32_t dtblkcmpl : 1; /* [10] */
__IO uint32_t reserved1 : 11;/* [21:11] */
__IO uint32_t ioif : 1; /* [22] */
__IO uint32_t reserved2 : 9; /* [31:23] */
} intclr_bit;
};
/**
* @brief sdio inten register, offset:0x3C
*/
union
{
__IO uint32_t inten;
struct
{
__IO uint32_t cmdfailien : 1; /* [0] */
__IO uint32_t dtfailien : 1; /* [1] */
__IO uint32_t cmdtimeoutien : 1; /* [2] */
__IO uint32_t dttimeoutien : 1; /* [3] */
__IO uint32_t txerruien : 1; /* [4] */
__IO uint32_t rxerroien : 1; /* [5] */
__IO uint32_t cmdrspcmplien : 1; /* [6] */
__IO uint32_t cmdcmplien : 1; /* [7] */
__IO uint32_t dtcmplien : 1; /* [8] */
__IO uint32_t sbiterrien : 1; /* [9] */
__IO uint32_t dtblkcmplien : 1; /* [10] */
__IO uint32_t docmdien : 1; /* [11] */
__IO uint32_t dotxien : 1; /* [12] */
__IO uint32_t dorxien : 1; /* [13] */
__IO uint32_t txbufhien : 1; /* [14] */
__IO uint32_t rxbufhien : 1; /* [15] */
__IO uint32_t txbuffien : 1; /* [16] */
__IO uint32_t rxbuffien : 1; /* [17] */
__IO uint32_t txbufeien : 1; /* [18] */
__IO uint32_t rxbufeien : 1; /* [19] */
__IO uint32_t txbufien : 1; /* [20] */
__IO uint32_t rxbufien : 1; /* [21] */
__IO uint32_t ioifien : 1; /* [22] */
__IO uint32_t reserved1 : 9; /* [31:23] */
} inten_bit;
};
/**
* @brief sdio reserved1 register, offset:0x40~0x44
*/
__IO uint32_t reserved1[2];
/**
* @brief sdio bufcnt register, offset:0x48
*/
union
{
__IO uint32_t bufcnt;
struct
{
__IO uint32_t cnt : 24;/* [23:0] */
__IO uint32_t reserved1 : 8; /* [31:24] */
} bufcnt_bit;
};
/**
* @brief sdio reserved2 register, offset:0x4C~0x7C
*/
__IO uint32_t reserved2[13];
/**
* @brief sdio buf register, offset:0x80
*/
union
{
__IO uint32_t buf;
struct
{
__IO uint32_t dt : 32;/* [31:0] */
} buf_bit;
};
} sdio_type;
/**
* @}
*/
#define SDIO1 ((sdio_type *) SDIO1_BASE)
/** @defgroup SDIO_exported_functions
* @{
*/
void sdio_reset(sdio_type *sdio_x);
void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x);
void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state);
flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag);
void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
uint8_t sdio_command_response_get(sdio_type *sdio_x);
uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index);
void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct);
void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
uint32_t sdio_data_counter_get(sdio_type *sdio_x);
uint32_t sdio_data_read(sdio_type *sdio_x);
uint32_t sdio_buffer_counter_get(sdio_type *sdio_x);
void sdio_data_write(sdio_type *sdio_x, uint32_t data);
void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode);
void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state);
void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state);
void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

494
libraries/drivers/inc/at32f415_spi.h Normal file
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@@ -0,0 +1,494 @@
/**
**************************************************************************
* @file at32f415_spi.h
* @brief at32f415 spi header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_SPI_H
#define __AT32F415_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/**
* @defgroup SPI_I2S_flags_definition
* @brief spi i2s flag
* @{
*/
#define SPI_I2S_RDBF_FLAG 0x0001 /*!< spi or i2s receive data buffer full flag */
#define SPI_I2S_TDBE_FLAG 0x0002 /*!< spi or i2s transmit data buffer empty flag */
#define I2S_ACS_FLAG 0x0004 /*!< i2s audio channel state flag */
#define I2S_TUERR_FLAG 0x0008 /*!< i2s transmitter underload error flag */
#define SPI_CCERR_FLAG 0x0010 /*!< spi crc calculation error flag */
#define SPI_MMERR_FLAG 0x0020 /*!< spi master mode error flag */
#define SPI_I2S_ROERR_FLAG 0x0040 /*!< spi or i2s receiver overflow error flag */
#define SPI_I2S_BF_FLAG 0x0080 /*!< spi or i2s busy flag */
/**
* @}
*/
/**
* @defgroup SPI_I2S_interrupts_definition
* @brief spi i2s interrupt
* @{
*/
#define SPI_I2S_ERROR_INT 0x0020 /*!< error interrupt */
#define SPI_I2S_RDBF_INT 0x0040 /*!< receive data buffer full interrupt */
#define SPI_I2S_TDBE_INT 0x0080 /*!< transmit data buffer empty interrupt */
/**
* @}
*/
/** @defgroup SPI_exported_types
* @{
*/
/**
* @brief spi frame bit num type
*/
typedef enum
{
SPI_FRAME_8BIT = 0x00, /*!< 8-bit data frame format */
SPI_FRAME_16BIT = 0x01 /*!< 16-bit data frame format */
} spi_frame_bit_num_type;
/**
* @brief spi master/slave mode type
*/
typedef enum
{
SPI_MODE_SLAVE = 0x00, /*!< select as slave mode */
SPI_MODE_MASTER = 0x01 /*!< select as master mode */
} spi_master_slave_mode_type;
/**
* @brief spi clock polarity (clkpol) type
*/
typedef enum
{
SPI_CLOCK_POLARITY_LOW = 0x00, /*!< sck keeps low at idle state */
SPI_CLOCK_POLARITY_HIGH = 0x01 /*!< sck keeps high at idle state */
} spi_clock_polarity_type;
/**
* @brief spi clock phase (clkpha) type
*/
typedef enum
{
SPI_CLOCK_PHASE_1EDGE = 0x00, /*!< data capture start from the first clock edge */
SPI_CLOCK_PHASE_2EDGE = 0x01 /*!< data capture start from the second clock edge */
} spi_clock_phase_type;
/**
* @brief spi cs mode type
*/
typedef enum
{
SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is hardware mode */
SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is software mode */
} spi_cs_mode_type;
/**
* @brief spi master clock frequency division type
*/
typedef enum
{
SPI_MCLK_DIV_2 = 0x00, /*!< master clock frequency division 2 */
SPI_MCLK_DIV_4 = 0x01, /*!< master clock frequency division 4 */
SPI_MCLK_DIV_8 = 0x02, /*!< master clock frequency division 8 */
SPI_MCLK_DIV_16 = 0x03, /*!< master clock frequency division 16 */
SPI_MCLK_DIV_32 = 0x04, /*!< master clock frequency division 32 */
SPI_MCLK_DIV_64 = 0x05, /*!< master clock frequency division 64 */
SPI_MCLK_DIV_128 = 0x06, /*!< master clock frequency division 128 */
SPI_MCLK_DIV_256 = 0x07, /*!< master clock frequency division 256 */
SPI_MCLK_DIV_512 = 0x08, /*!< master clock frequency division 512 */
SPI_MCLK_DIV_1024 = 0x09 /*!< master clock frequency division 1024 */
} spi_mclk_freq_div_type;
/**
* @brief spi transmit first bit (lsb/msb) type
*/
typedef enum
{
SPI_FIRST_BIT_MSB = 0x00, /*!< the frame format is msb first */
SPI_FIRST_BIT_LSB = 0x01 /*!< the frame format is lsb first */
} spi_first_bit_type;
/**
* @brief spi transmission mode type
*/
typedef enum
{
SPI_TRANSMIT_FULL_DUPLEX = 0x00, /*!< dual line unidirectional full-duplex mode(slben = 0 and ora = 0) */
SPI_TRANSMIT_SIMPLEX_RX = 0x01, /*!< dual line unidirectional simplex receive-only mode(slben = 0 and ora = 1) */
SPI_TRANSMIT_HALF_DUPLEX_RX = 0x02, /*!< single line bidirectional half duplex mode-receiving(slben = 1 and slbtd = 0) */
SPI_TRANSMIT_HALF_DUPLEX_TX = 0x03 /*!< single line bidirectional half duplex mode-transmitting(slben = 1 and slbtd = 1) */
} spi_transmission_mode_type;
/**
* @brief spi crc direction type
*/
typedef enum
{
SPI_CRC_RX = 0x0014, /*!< crc direction is rx */
SPI_CRC_TX = 0x0018 /*!< crc direction is tx */
} spi_crc_direction_type;
/**
* @brief spi single line bidirectional direction type
*/
typedef enum
{
SPI_HALF_DUPLEX_DIRECTION_RX = 0x00, /*!< single line bidirectional half duplex mode direction: receive(slbtd = 0) */
SPI_HALF_DUPLEX_DIRECTION_TX = 0x01 /*!< single line bidirectional half duplex mode direction: transmit(slbtd = 1) */
} spi_half_duplex_direction_type;
/**
* @brief spi software cs internal level type
*/
typedef enum
{
SPI_SWCS_INTERNAL_LEVEL_LOW = 0x00, /*!< internal level low */
SPI_SWCS_INTERNAL_LEVEL_HIGHT = 0x01 /*!< internal level high */
} spi_software_cs_level_type;
/**
* @brief i2s audio protocol type
*/
typedef enum
{
I2S_AUDIO_PROTOCOL_PHILLIPS = 0x00, /*!< i2s philip standard */
I2S_AUDIO_PROTOCOL_MSB = 0x01, /*!< msb-justified standard */
I2S_AUDIO_PROTOCOL_LSB = 0x02, /*!< lsb-justified standard */
I2S_AUDIO_PROTOCOL_PCM_SHORT = 0x03, /*!< pcm standard-short frame */
I2S_AUDIO_PROTOCOL_PCM_LONG = 0x04 /*!< pcm standard-long frame */
} i2s_audio_protocol_type;
/**
* @brief i2s audio frequency type
*/
typedef enum
{
I2S_AUDIO_FREQUENCY_DEFAULT = 2, /*!< i2s audio sampling frequency default */
I2S_AUDIO_FREQUENCY_8K = 8000, /*!< i2s audio sampling frequency 8k */
I2S_AUDIO_FREQUENCY_11_025K = 11025, /*!< i2s audio sampling frequency 11.025k */
I2S_AUDIO_FREQUENCY_16K = 16000, /*!< i2s audio sampling frequency 16k */
I2S_AUDIO_FREQUENCY_22_05K = 22050, /*!< i2s audio sampling frequency 22.05k */
I2S_AUDIO_FREQUENCY_32K = 32000, /*!< i2s audio sampling frequency 32k */
I2S_AUDIO_FREQUENCY_44_1K = 44100, /*!< i2s audio sampling frequency 44.1k */
I2S_AUDIO_FREQUENCY_48K = 48000, /*!< i2s audio sampling frequency 48k */
I2S_AUDIO_FREQUENCY_96K = 96000, /*!< i2s audio sampling frequency 96k */
I2S_AUDIO_FREQUENCY_192K = 192000 /*!< i2s audio sampling frequency 192k */
} i2s_audio_sampling_freq_type;
/**
* @brief i2s data bit num and channel bit num type
*/
typedef enum
{
I2S_DATA_16BIT_CHANNEL_16BIT = 0x01, /*!< 16-bit data packed in 16-bit channel frame */
I2S_DATA_16BIT_CHANNEL_32BIT = 0x02, /*!< 16-bit data packed in 32-bit channel frame */
I2S_DATA_24BIT_CHANNEL_32BIT = 0x03, /*!< 24-bit data packed in 32-bit channel frame */
I2S_DATA_32BIT_CHANNEL_32BIT = 0x04 /*!< 32-bit data packed in 32-bit channel frame */
} i2s_data_channel_format_type;
/**
* @brief i2s operation mode type
*/
typedef enum
{
I2S_MODE_SLAVE_TX = 0x00, /*!< slave transmission mode */
I2S_MODE_SLAVE_RX = 0x01, /*!< slave reception mode */
I2S_MODE_MASTER_TX = 0x02, /*!< master transmission mode */
I2S_MODE_MASTER_RX = 0x03 /*!< master reception mode */
} i2s_operation_mode_type;
/**
* @brief i2s clock polarity type
*/
typedef enum
{
I2S_CLOCK_POLARITY_LOW = 0x00, /*!< i2s clock steady state is low level */
I2S_CLOCK_POLARITY_HIGH = 0x01 /*!< i2s clock steady state is high level */
} i2s_clock_polarity_type;
/**
* @brief spi init type
*/
typedef struct
{
spi_transmission_mode_type transmission_mode; /*!< transmission mode selection */
spi_master_slave_mode_type master_slave_mode; /*!< master or slave mode selection */
spi_mclk_freq_div_type mclk_freq_division; /*!< master clock frequency division selection */
spi_first_bit_type first_bit_transmission;/*!< transmit lsb or msb selection */
spi_frame_bit_num_type frame_bit_num; /*!< frame bit num 8 or 16 bit selection */
spi_clock_polarity_type clock_polarity; /*!< clock polarity selection */
spi_clock_phase_type clock_phase; /*!< clock phase selection */
spi_cs_mode_type cs_mode_selection; /*!< hardware or software cs mode selection */
} spi_init_type;
/**
* @brief i2s init type
*/
typedef struct
{
i2s_operation_mode_type operation_mode; /*!< operation mode selection */
i2s_audio_protocol_type audio_protocol; /*!< audio protocol selection */
i2s_audio_sampling_freq_type audio_sampling_freq; /*!< audio frequency selection */
i2s_data_channel_format_type data_channel_format; /*!< data bit num and channel bit num selection */
i2s_clock_polarity_type clock_polarity; /*!< clock polarity selection */
confirm_state mclk_output_enable; /*!< mclk_output selection */
} i2s_init_type;
/**
* @brief type define spi register all
*/
typedef struct
{
/**
* @brief spi ctrl1 register, offset:0x00
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t clkpha : 1; /* [0] */
__IO uint32_t clkpol : 1; /* [1] */
__IO uint32_t msten : 1; /* [2] */
__IO uint32_t mdiv_l : 3; /* [5:3] */
__IO uint32_t spien : 1; /* [6] */
__IO uint32_t ltf : 1; /* [7] */
__IO uint32_t swcsil : 1; /* [8] */
__IO uint32_t swcsen : 1; /* [9] */
__IO uint32_t ora : 1; /* [10] */
__IO uint32_t fbn : 1; /* [11] */
__IO uint32_t ntc : 1; /* [12] */
__IO uint32_t ccen : 1; /* [13] */
__IO uint32_t slbtd : 1; /* [14] */
__IO uint32_t slben : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} ctrl1_bit;
};
/**
* @brief spi ctrl2 register, offset:0x04
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t dmaren : 1; /* [0] */
__IO uint32_t dmaten : 1; /* [1] */
__IO uint32_t hwcsoe : 1; /* [2] */
__IO uint32_t reserved1 : 2; /* [4:3] */
__IO uint32_t errie : 1; /* [5] */
__IO uint32_t rdbfie : 1; /* [6] */
__IO uint32_t tdbeie : 1; /* [7] */
__IO uint32_t mdiv_h : 1; /* [8] */
__IO uint32_t reserved2 : 23;/* [31:9] */
} ctrl2_bit;
};
/**
* @brief spi sts register, offset:0x08
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t rdbf : 1; /* [0] */
__IO uint32_t tdbe : 1; /* [1] */
__IO uint32_t acs : 1; /* [2] */
__IO uint32_t tuerr : 1; /* [3] */
__IO uint32_t ccerr : 1; /* [4] */
__IO uint32_t mmerr : 1; /* [5] */
__IO uint32_t roerr : 1; /* [6] */
__IO uint32_t bf : 1; /* [7] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} sts_bit;
};
/**
* @brief spi dt register, offset:0x0C
*/
union
{
__IO uint32_t dt;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} dt_bit;
};
/**
* @brief spi cpoly register, offset:0x10
*/
union
{
__IO uint32_t cpoly;
struct
{
__IO uint32_t cpoly : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cpoly_bit;
};
/**
* @brief spi rcrc register, offset:0x14
*/
union
{
__IO uint32_t rcrc;
struct
{
__IO uint32_t rcrc : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} rcrc_bit;
};
/**
* @brief spi tcrc register, offset:0x18
*/
union
{
__IO uint32_t tcrc;
struct
{
__IO uint32_t tcrc : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} tcrc_bit;
};
/**
* @brief spi i2sctrl register, offset:0x1C
*/
union
{
__IO uint32_t i2sctrl;
struct
{
__IO uint32_t i2scbn : 1; /* [0] */
__IO uint32_t i2sdbn : 2; /* [2:1] */
__IO uint32_t i2sclkpol : 1; /* [3] */
__IO uint32_t stdsel : 2; /* [5:4] */
__IO uint32_t reserved1 : 1; /* [6] */
__IO uint32_t pcmfssel : 1; /* [7] */
__IO uint32_t opersel : 2; /* [9:8] */
__IO uint32_t i2sen : 1; /* [10] */
__IO uint32_t i2smsel : 1; /* [11] */
__IO uint32_t reserved2 : 20;/* [31:12] */
} i2sctrl_bit;
};
/**
* @brief spi i2sclk register, offset:0x20
*/
union
{
__IO uint32_t i2sclk;
struct
{
__IO uint32_t i2sdiv_l : 8; /* [7:0] */
__IO uint32_t i2sodd : 1; /* [8] */
__IO uint32_t i2smclkoe : 1; /* [9] */
__IO uint32_t i2sdiv_h : 2; /* [11:10] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} i2sclk_bit;
};
} spi_type;
/**
* @}
*/
#define SPI1 ((spi_type *) SPI1_BASE)
#define SPI2 ((spi_type *) SPI2_BASE)
/** @defgroup SPI_exported_functions
* @{
*/
void spi_i2s_reset(spi_type *spi_x);
void spi_default_para_init(spi_init_type* spi_init_struct);
void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct);
void spi_crc_next_transmit(spi_type* spi_x);
void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly);
uint16_t spi_crc_polynomial_get(spi_type* spi_x);
void spi_crc_enable(spi_type* spi_x, confirm_state new_state);
uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction);
void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state);
void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level);
void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num);
void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction);
void spi_enable(spi_type* spi_x, confirm_state new_state);
void i2s_default_para_init(i2s_init_type* i2s_init_struct);
void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct);
void i2s_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state);
void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
uint16_t spi_i2s_data_receive(spi_type* spi_x);
flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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libraries/drivers/inc/at32f415_tmr.h Normal file
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@@ -0,0 +1,944 @@
/**
**************************************************************************
* @file at32f415_tmr.h
* @brief at32f415 tmr header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_TMR_H
#define __AT32F415_TMR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup TMR
* @{
*/
/** @defgroup TMR_flags_definition
* @brief tmr flag
* @{
*/
#define TMR_OVF_FLAG ((uint32_t)0x000001) /*!< tmr flag overflow */
#define TMR_C1_FLAG ((uint32_t)0x000002) /*!< tmr flag channel 1 */
#define TMR_C2_FLAG ((uint32_t)0x000004) /*!< tmr flag channel 2 */
#define TMR_C3_FLAG ((uint32_t)0x000008) /*!< tmr flag channel 3 */
#define TMR_C4_FLAG ((uint32_t)0x000010) /*!< tmr flag channel 4 */
#define TMR_HALL_FLAG ((uint32_t)0x000020) /*!< tmr flag hall */
#define TMR_TRIGGER_FLAG ((uint32_t)0x000040) /*!< tmr flag trigger */
#define TMR_BRK_FLAG ((uint32_t)0x000080) /*!< tmr flag brake */
#define TMR_C1_RECAPTURE_FLAG ((uint32_t)0x000200) /*!< tmr flag channel 1 recapture */
#define TMR_C2_RECAPTURE_FLAG ((uint32_t)0x000400) /*!< tmr flag channel 2 recapture */
#define TMR_C3_RECAPTURE_FLAG ((uint32_t)0x000800) /*!< tmr flag channel 3 recapture */
#define TMR_C4_RECAPTURE_FLAG ((uint32_t)0x001000) /*!< tmr flag channel 4 recapture */
/**
* @}
*/
/** @defgroup TMR_interrupt_select_type_definition
* @brief tmr interrupt select type
* @{
*/
#define TMR_OVF_INT ((uint32_t)0x000001) /*!< tmr interrupt overflow */
#define TMR_C1_INT ((uint32_t)0x000002) /*!< tmr interrupt channel 1 */
#define TMR_C2_INT ((uint32_t)0x000004) /*!< tmr interrupt channel 2 */
#define TMR_C3_INT ((uint32_t)0x000008) /*!< tmr interrupt channel 3 */
#define TMR_C4_INT ((uint32_t)0x000010) /*!< tmr interrupt channel 4 */
#define TMR_HALL_INT ((uint32_t)0x000020) /*!< tmr interrupt hall */
#define TMR_TRIGGER_INT ((uint32_t)0x000040) /*!< tmr interrupt trigger */
#define TMR_BRK_INT ((uint32_t)0x000080) /*!< tmr interrupt brake */
/**
* @}
*/
/** @defgroup TMR_exported_types
* @{
*/
/**
* @brief tmr clock division type
*/
typedef enum
{
TMR_CLOCK_DIV1 = 0x00, /*!< tmr clock division 1 */
TMR_CLOCK_DIV2 = 0x01, /*!< tmr clock division 2 */
TMR_CLOCK_DIV4 = 0x02 /*!< tmr clock division 4 */
} tmr_clock_division_type;
/**
* @brief tmr counter mode type
*/
typedef enum
{
TMR_COUNT_UP = 0x00, /*!< tmr counter mode up */
TMR_COUNT_DOWN = 0x01, /*!< tmr counter mode down */
TMR_COUNT_TWO_WAY_1 = 0x02, /*!< tmr counter mode two way 1 */
TMR_COUNT_TWO_WAY_2 = 0x04, /*!< tmr counter mode two way 2 */
TMR_COUNT_TWO_WAY_3 = 0x06 /*!< tmr counter mode two way 3 */
} tmr_count_mode_type;
/**
* @brief tmr primary mode select type
*/
typedef enum
{
TMR_PRIMARY_SEL_RESET = 0x00, /*!< tmr primary mode select reset */
TMR_PRIMARY_SEL_ENABLE = 0x01, /*!< tmr primary mode select enable */
TMR_PRIMARY_SEL_OVERFLOW = 0x02, /*!< tmr primary mode select overflow */
TMR_PRIMARY_SEL_COMPARE = 0x03, /*!< tmr primary mode select compare */
TMR_PRIMARY_SEL_C1ORAW = 0x04, /*!< tmr primary mode select c1oraw */
TMR_PRIMARY_SEL_C2ORAW = 0x05, /*!< tmr primary mode select c2oraw */
TMR_PRIMARY_SEL_C3ORAW = 0x06, /*!< tmr primary mode select c3oraw */
TMR_PRIMARY_SEL_C4ORAW = 0x07 /*!< tmr primary mode select c4oraw */
} tmr_primary_select_type;
/**
* @brief tmr subordinate mode input select type
*/
typedef enum
{
TMR_SUB_INPUT_SEL_IS0 = 0x00, /*!< subordinate mode input select is0 */
TMR_SUB_INPUT_SEL_IS1 = 0x01, /*!< subordinate mode input select is1 */
TMR_SUB_INPUT_SEL_IS2 = 0x02, /*!< subordinate mode input select is2 */
TMR_SUB_INPUT_SEL_IS3 = 0x03, /*!< subordinate mode input select is3 */
TMR_SUB_INPUT_SEL_C1INC = 0x04, /*!< subordinate mode input select c1inc */
TMR_SUB_INPUT_SEL_C1DF1 = 0x05, /*!< subordinate mode input select c1df1 */
TMR_SUB_INPUT_SEL_C2DF2 = 0x06, /*!< subordinate mode input select c2df2 */
TMR_SUB_INPUT_SEL_EXTIN = 0x07 /*!< subordinate mode input select extin */
} sub_tmr_input_sel_type;
/**
* @brief tmr subordinate mode select type
*/
typedef enum
{
TMR_SUB_MODE_DIABLE = 0x00, /*!< subordinate mode disable */
TMR_SUB_ENCODER_MODE_A = 0x01, /*!< subordinate mode select encoder mode a */
TMR_SUB_ENCODER_MODE_B = 0x02, /*!< subordinate mode select encoder mode b */
TMR_SUB_ENCODER_MODE_C = 0x03, /*!< subordinate mode select encoder mode c */
TMR_SUB_RESET_MODE = 0x04, /*!< subordinate mode select reset */
TMR_SUB_HANG_MODE = 0x05, /*!< subordinate mode select hang */
TMR_SUB_TRIGGER_MODE = 0x06, /*!< subordinate mode select trigger */
TMR_SUB_EXTERNAL_CLOCK_MODE_A = 0x07 /*!< subordinate mode external clock mode a */
} tmr_sub_mode_select_type;
/**
* @brief tmr encoder mode type
*/
typedef enum
{
TMR_ENCODER_MODE_A = TMR_SUB_ENCODER_MODE_A, /*!< tmr encoder mode a */
TMR_ENCODER_MODE_B = TMR_SUB_ENCODER_MODE_B, /*!< tmr encoder mode b */
TMR_ENCODER_MODE_C = TMR_SUB_ENCODER_MODE_C /*!< tmr encoder mode c */
} tmr_encoder_mode_type;
/**
* @brief tmr output control mode type
*/
typedef enum
{
TMR_OUTPUT_CONTROL_OFF = 0x00, /*!< tmr output control mode off */
TMR_OUTPUT_CONTROL_HIGH = 0x01, /*!< tmr output control mode high */
TMR_OUTPUT_CONTROL_LOW = 0x02, /*!< tmr output control mode low */
TMR_OUTPUT_CONTROL_SWITCH = 0x03, /*!< tmr output control mode switch */
TMR_OUTPUT_CONTROL_FORCE_LOW = 0x04, /*!< tmr output control mode force low */
TMR_OUTPUT_CONTROL_FORCE_HIGH = 0x05, /*!< tmr output control mode force high */
TMR_OUTPUT_CONTROL_PWM_MODE_A = 0x06, /*!< tmr output control mode pwm a */
TMR_OUTPUT_CONTROL_PWM_MODE_B = 0x07 /*!< tmr output control mode pwm b */
} tmr_output_control_mode_type;
/**
* @brief tmr force output type
*/
typedef enum
{
TMR_FORCE_OUTPUT_HIGH = TMR_OUTPUT_CONTROL_FORCE_HIGH, /*!< tmr force output high */
TMR_FORCE_OUTPUT_LOW = TMR_OUTPUT_CONTROL_FORCE_LOW /*!< tmr force output low */
} tmr_force_output_type;
/**
* @brief tmr output channel polarity type
*/
typedef enum
{
TMR_OUTPUT_ACTIVE_HIGH = 0x00, /*!< tmr output channel polarity high */
TMR_OUTPUT_ACTIVE_LOW = 0x01 /*!< tmr output channel polarity low */
} tmr_output_polarity_type;
/**
* @brief tmr input channel polarity type
*/
typedef enum
{
TMR_INPUT_RISING_EDGE = 0x00, /*!< tmr input channel polarity rising */
TMR_INPUT_FALLING_EDGE = 0x01, /*!< tmr input channel polarity falling */
TMR_INPUT_BOTH_EDGE = 0x03 /*!< tmr input channel polarity both edge */
} tmr_input_polarity_type;
/**
* @brief tmr channel select type
*/
typedef enum
{
TMR_SELECT_CHANNEL_1 = 0x00, /*!< tmr channel select channel 1 */
TMR_SELECT_CHANNEL_1C = 0x01, /*!< tmr channel select channel 1 complementary */
TMR_SELECT_CHANNEL_2 = 0x02, /*!< tmr channel select channel 2 */
TMR_SELECT_CHANNEL_2C = 0x03, /*!< tmr channel select channel 2 complementary */
TMR_SELECT_CHANNEL_3 = 0x04, /*!< tmr channel select channel 3 */
TMR_SELECT_CHANNEL_3C = 0x05, /*!< tmr channel select channel 3 complementary */
TMR_SELECT_CHANNEL_4 = 0x06 /*!< tmr channel select channel 4 */
} tmr_channel_select_type;
/**
* @brief tmr channel1 input connected type
*/
typedef enum
{
TMR_CHANEL1_CONNECTED_C1IRAW = 0x00, /*!< channel1 pins is only connected to C1IRAW input */
TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR = 0x01 /*!< channel1/2/3 pins are connected to C1IRAW input after xored */
} tmr_channel1_input_connected_type;
/**
* @brief tmr input channel mapped type channel direction
*/
typedef enum
{
TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */
TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */
TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */
} tmr_input_direction_mapped_type;
/**
* @brief tmr input divider type
*/
typedef enum
{
TMR_CHANNEL_INPUT_DIV_1 = 0x00, /*!< tmr channel input divider 1 */
TMR_CHANNEL_INPUT_DIV_2 = 0x01, /*!< tmr channel input divider 2 */
TMR_CHANNEL_INPUT_DIV_4 = 0x02, /*!< tmr channel input divider 4 */
TMR_CHANNEL_INPUT_DIV_8 = 0x03 /*!< tmr channel input divider 8 */
} tmr_channel_input_divider_type;
/**
* @brief tmr dma request source select type
*/
typedef enum
{
TMR_DMA_REQUEST_BY_CHANNEL = 0x00, /*!< tmr dma request source select channel */
TMR_DMA_REQUEST_BY_OVERFLOW = 0x01 /*!< tmr dma request source select overflow */
} tmr_dma_request_source_type;
/**
* @brief tmr dma request type
*/
typedef enum
{
TMR_OVERFLOW_DMA_REQUEST = 0x00000100, /*!< tmr dma request select overflow */
TMR_C1_DMA_REQUEST = 0x00000200, /*!< tmr dma request select channel 1 */
TMR_C2_DMA_REQUEST = 0x00000400, /*!< tmr dma request select channel 2 */
TMR_C3_DMA_REQUEST = 0x00000800, /*!< tmr dma request select channel 3 */
TMR_C4_DMA_REQUEST = 0x00001000, /*!< tmr dma request select channel 4 */
TMR_HALL_DMA_REQUEST = 0x00002000, /*!< tmr dma request select hall */
TMR_TRIGGER_DMA_REQUEST = 0x00004000 /*!< tmr dma request select trigger */
} tmr_dma_request_type;
/**
* @brief tmr event triggered by software type
*/
typedef enum
{
TMR_OVERFLOW_SWTRIG = 0x00000001, /*!< tmr event triggered by software of overflow */
TMR_C1_SWTRIG = 0x00000002, /*!< tmr event triggered by software of channel 1 */
TMR_C2_SWTRIG = 0x00000004, /*!< tmr event triggered by software of channel 2 */
TMR_C3_SWTRIG = 0x00000008, /*!< tmr event triggered by software of channel 3 */
TMR_C4_SWTRIG = 0x00000010, /*!< tmr event triggered by software of channel 4 */
TMR_HALL_SWTRIG = 0x00000020, /*!< tmr event triggered by software of hall */
TMR_TRIGGER_SWTRIG = 0x00000040, /*!< tmr event triggered by software of trigger */
TMR_BRK_SWTRIG = 0x00000080 /*!< tmr event triggered by software of brake */
}tmr_event_trigger_type;
/**
* @brief tmr polarity active type
*/
typedef enum
{
TMR_POLARITY_ACTIVE_HIGH = 0x00, /*!< tmr polarity active high */
TMR_POLARITY_ACTIVE_LOW = 0x01, /*!< tmr polarity active low */
TMR_POLARITY_ACTIVE_BOTH = 0x02 /*!< tmr polarity active both high ande low */
}tmr_polarity_active_type;
/**
* @brief tmr external signal divider type
*/
typedef enum
{
TMR_ES_FREQUENCY_DIV_1 = 0x00, /*!< tmr external signal frequency divider 1 */
TMR_ES_FREQUENCY_DIV_2 = 0x01, /*!< tmr external signal frequency divider 2 */
TMR_ES_FREQUENCY_DIV_4 = 0x02, /*!< tmr external signal frequency divider 4 */
TMR_ES_FREQUENCY_DIV_8 = 0x03 /*!< tmr external signal frequency divider 8 */
}tmr_external_signal_divider_type;
/**
* @brief tmr external signal polarity type
*/
typedef enum
{
TMR_ES_POLARITY_NON_INVERTED = 0x00, /*!< tmr external signal polarity non-inerted */
TMR_ES_POLARITY_INVERTED = 0x01 /*!< tmr external signal polarity inerted */
}tmr_external_signal_polarity_type;
/**
* @brief tmr dma transfer length type
*/
typedef enum
{
TMR_DMA_TRANSFER_1BYTE = 0x00, /*!< tmr dma transfer length 1 byte */
TMR_DMA_TRANSFER_2BYTES = 0x01, /*!< tmr dma transfer length 2 bytes */
TMR_DMA_TRANSFER_3BYTES = 0x02, /*!< tmr dma transfer length 3 bytes */
TMR_DMA_TRANSFER_4BYTES = 0x03, /*!< tmr dma transfer length 4 bytes */
TMR_DMA_TRANSFER_5BYTES = 0x04, /*!< tmr dma transfer length 5 bytes */
TMR_DMA_TRANSFER_6BYTES = 0x05, /*!< tmr dma transfer length 6 bytes */
TMR_DMA_TRANSFER_7BYTES = 0x06, /*!< tmr dma transfer length 7 bytes */
TMR_DMA_TRANSFER_8BYTES = 0x07, /*!< tmr dma transfer length 8 bytes */
TMR_DMA_TRANSFER_9BYTES = 0x08, /*!< tmr dma transfer length 9 bytes */
TMR_DMA_TRANSFER_10BYTES = 0x09, /*!< tmr dma transfer length 10 bytes */
TMR_DMA_TRANSFER_11BYTES = 0x0A, /*!< tmr dma transfer length 11 bytes */
TMR_DMA_TRANSFER_12BYTES = 0x0B, /*!< tmr dma transfer length 12 bytes */
TMR_DMA_TRANSFER_13BYTES = 0x0C, /*!< tmr dma transfer length 13 bytes */
TMR_DMA_TRANSFER_14BYTES = 0x0D, /*!< tmr dma transfer length 14 bytes */
TMR_DMA_TRANSFER_15BYTES = 0x0E, /*!< tmr dma transfer length 15 bytes */
TMR_DMA_TRANSFER_16BYTES = 0x0F, /*!< tmr dma transfer length 16 bytes */
TMR_DMA_TRANSFER_17BYTES = 0x10, /*!< tmr dma transfer length 17 bytes */
TMR_DMA_TRANSFER_18BYTES = 0x11 /*!< tmr dma transfer length 18 bytes */
}tmr_dma_transfer_length_type;
/**
* @brief tmr dma base address type
*/
typedef enum
{
TMR_CTRL1_ADDRESS = 0x0000, /*!< tmr dma base address ctrl1 */
TMR_CTRL2_ADDRESS = 0x0001, /*!< tmr dma base address ctrl2 */
TMR_STCTRL_ADDRESS = 0x0002, /*!< tmr dma base address stctrl */
TMR_IDEN_ADDRESS = 0x0003, /*!< tmr dma base address iden */
TMR_ISTS_ADDRESS = 0x0004, /*!< tmr dma base address ists */
TMR_SWEVT_ADDRESS = 0x0005, /*!< tmr dma base address swevt */
TMR_CM1_ADDRESS = 0x0006, /*!< tmr dma base address cm1 */
TMR_CM2_ADDRESS = 0x0007, /*!< tmr dma base address cm2 */
TMR_CCTRL_ADDRESS = 0x0008, /*!< tmr dma base address cctrl */
TMR_CVAL_ADDRESS = 0x0009, /*!< tmr dma base address cval */
TMR_DIV_ADDRESS = 0x000A, /*!< tmr dma base address div */
TMR_PR_ADDRESS = 0x000B, /*!< tmr dma base address pr */
TMR_RPR_ADDRESS = 0x000C, /*!< tmr dma base address rpr */
TMR_C1DT_ADDRESS = 0x000D, /*!< tmr dma base address c1dt */
TMR_C2DT_ADDRESS = 0x000E, /*!< tmr dma base address c2dt */
TMR_C3DT_ADDRESS = 0x000F, /*!< tmr dma base address c3dt */
TMR_C4DT_ADDRESS = 0x0010, /*!< tmr dma base address c4dt */
TMR_BRK_ADDRESS = 0x0011, /*!< tmr dma base address brake */
TMR_DMACTRL_ADDRESS = 0x0012 /*!< tmr dma base address dmactrl */
}tmr_dma_address_type;
/**
* @brief tmr brk polarity type
*/
typedef enum
{
TMR_BRK_INPUT_ACTIVE_LOW = 0x00, /*!< tmr brk input channel active low */
TMR_BRK_INPUT_ACTIVE_HIGH = 0x01 /*!< tmr brk input channel active high */
}tmr_brk_polarity_type;
/**
* @brief tmr write protect level type
*/
typedef enum
{
TMR_WP_OFF = 0x00, /*!< tmr write protect off */
TMR_WP_LEVEL_3 = 0x01, /*!< tmr write protect level 3 */
TMR_WP_LEVEL_2 = 0x02, /*!< tmr write protect level 2 */
TMR_WP_LEVEL_1 = 0x03 /*!< tmr write protect level 1 */
}tmr_wp_level_type;
/**
* @brief tmr output channel switch selection type
*/
typedef enum
{
TMR_CH_SWITCH_SELECT_EXT = 0x00, /*!< tmr output channel switch select ext pin */
TMR_CH_SWITCH_SELECT_CXORAW_OFF = 0x01, /*!< tmr output channel switch select cxoraw off signal */
}tmr_ch_switch_select_type ;
/**
* @brief tmr output config type
*/
typedef struct
{
tmr_output_control_mode_type oc_mode; /*!< output channel mode */
confirm_state oc_idle_state; /*!< output channel idle state */
confirm_state occ_idle_state; /*!< output channel complementary idle state */
tmr_output_polarity_type oc_polarity; /*!< output channel polarity */
tmr_output_polarity_type occ_polarity; /*!< output channel complementary polarity */
confirm_state oc_output_state; /*!< output channel enable */
confirm_state occ_output_state; /*!< output channel complementary enable */
} tmr_output_config_type;
/**
* @brief tmr input capture config type
*/
typedef struct
{
tmr_channel_select_type input_channel_select; /*!< tmr input channel select */
tmr_input_polarity_type input_polarity_select; /*!< tmr input polarity select */
tmr_input_direction_mapped_type input_mapped_select; /*!< tmr channel mapped direct or indirect */
uint8_t input_filter_value; /*!< tmr channel filter value */
} tmr_input_config_type;
/**
* @brief tmr brkdt config type
*/
typedef struct
{
uint8_t deadtime; /*!< dead-time generator setup */
tmr_brk_polarity_type brk_polarity; /*!< tmr brake polarity */
tmr_wp_level_type wp_level; /*!< write protect configuration */
confirm_state auto_output_enable; /*!< automatic output enable */
confirm_state fcsoen_state; /*!< frozen channel status when output enable */
confirm_state fcsodis_state; /*!< frozen channel status when output disable */
confirm_state brk_enable; /*!< tmr brk enale */
} tmr_brkdt_config_type;
/**
* @brief type define tmr register all
*/
typedef struct
{
/**
* @brief tmr ctrl1 register, offset:0x00
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t tmren : 1; /* [0] */
__IO uint32_t ovfen : 1; /* [1] */
__IO uint32_t ovfs : 1; /* [2] */
__IO uint32_t ocmen : 1; /* [3] */
__IO uint32_t cnt_dir : 3; /* [6:4] */
__IO uint32_t prben : 1; /* [7] */
__IO uint32_t clkdiv : 2; /* [9:8] */
__IO uint32_t pmen : 1; /* [10] */
__IO uint32_t reserved1 : 21;/* [31:11] */
} ctrl1_bit;
};
/**
* @brief tmr ctrl2 register, offset:0x04
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t cbctrl : 1; /* [0] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t ccfs : 1; /* [2] */
__IO uint32_t drs : 1; /* [3] */
__IO uint32_t ptos : 3; /* [6:4] */
__IO uint32_t c1insel : 1; /* [7] */
__IO uint32_t c1ios : 1; /* [8] */
__IO uint32_t c1cios : 1; /* [9] */
__IO uint32_t c2ios : 1; /* [10] */
__IO uint32_t c2cios : 1; /* [11] */
__IO uint32_t c3ios : 1; /* [12] */
__IO uint32_t c3cios : 1; /* [13] */
__IO uint32_t c4ios : 1; /* [14] */
__IO uint32_t reserved2 : 17;/* [31:15] */
} ctrl2_bit;
};
/**
* @brief tmr smc register, offset:0x08
*/
union
{
__IO uint32_t stctrl;
struct
{
__IO uint32_t smsel : 3; /* [2:0] */
__IO uint32_t cossel : 1; /* [3] */
__IO uint32_t stis : 3; /* [6:4] */
__IO uint32_t sts : 1; /* [7] */
__IO uint32_t esf : 4; /* [11:8] */
__IO uint32_t esdiv : 2; /* [13:12] */
__IO uint32_t ecmben : 1; /* [14] */
__IO uint32_t esp : 1; /* [15] */
__IO uint32_t reserved2 : 16;/* [31:16] */
} stctrl_bit;
};
/**
* @brief tmr die register, offset:0x0C
*/
union
{
__IO uint32_t iden;
struct
{
__IO uint32_t ovfien : 1; /* [0] */
__IO uint32_t c1ien : 1; /* [1] */
__IO uint32_t c2ien : 1; /* [2] */
__IO uint32_t c3ien : 1; /* [3] */
__IO uint32_t c4ien : 1; /* [4] */
__IO uint32_t hallien : 1; /* [5] */
__IO uint32_t tien : 1; /* [6] */
__IO uint32_t brkie : 1; /* [7] */
__IO uint32_t ovfden : 1; /* [8] */
__IO uint32_t c1den : 1; /* [9] */
__IO uint32_t c2den : 1; /* [10] */
__IO uint32_t c3den : 1; /* [11] */
__IO uint32_t c4den : 1; /* [12] */
__IO uint32_t hallde : 1; /* [13] */
__IO uint32_t tden : 1; /* [14] */
__IO uint32_t reserved1 : 17;/* [31:15] */
} iden_bit;
};
/**
* @brief tmr ists register, offset:0x10
*/
union
{
__IO uint32_t ists;
struct
{
__IO uint32_t ovfif : 1; /* [0] */
__IO uint32_t c1if : 1; /* [1] */
__IO uint32_t c2if : 1; /* [2] */
__IO uint32_t c3if : 1; /* [3] */
__IO uint32_t c4if : 1; /* [4] */
__IO uint32_t hallif : 1; /* [5] */
__IO uint32_t trgif : 1; /* [6] */
__IO uint32_t brkif : 1; /* [7] */
__IO uint32_t reserved1 : 1; /* [8] */
__IO uint32_t c1rf : 1; /* [9] */
__IO uint32_t c2rf : 1; /* [10] */
__IO uint32_t c3rf : 1; /* [11] */
__IO uint32_t c4rf : 1; /* [12] */
__IO uint32_t reserved2 : 19;/* [31:13] */
} ists_bit;
};
/**
* @brief tmr eveg register, offset:0x14
*/
union
{
__IO uint32_t swevt;
struct
{
__IO uint32_t ovfswtr : 1; /* [0] */
__IO uint32_t c1swtr : 1; /* [1] */
__IO uint32_t c2swtr : 1; /* [2] */
__IO uint32_t c3swtr : 1; /* [3] */
__IO uint32_t c4swtr : 1; /* [4] */
__IO uint32_t hallswtr : 1; /* [5] */
__IO uint32_t trgswtr : 1; /* [6] */
__IO uint32_t brkswtr : 1; /* [7] */
__IO uint32_t reserved : 24;/* [31:8] */
} swevt_bit;
};
/**
* @brief tmr ccm1 register, offset:0x18
*/
union
{
__IO uint32_t cm1;
/**
* @brief channel mode
*/
struct
{
__IO uint32_t c1c : 2; /* [1:0] */
__IO uint32_t c1oien : 1; /* [2] */
__IO uint32_t c1oben : 1; /* [3] */
__IO uint32_t c1octrl : 3; /* [6:4] */
__IO uint32_t c1osen : 1; /* [7] */
__IO uint32_t c2c : 2; /* [9:8] */
__IO uint32_t c2oien : 1; /* [10] */
__IO uint32_t c2oben : 1; /* [11] */
__IO uint32_t c2octrl : 3; /* [14:12] */
__IO uint32_t c2osen : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cm1_output_bit;
/**
* @brief input capture mode
*/
struct
{
__IO uint32_t c1c : 2; /* [1:0] */
__IO uint32_t c1idiv : 2; /* [3:2] */
__IO uint32_t c1df : 4; /* [7:4] */
__IO uint32_t c2c : 2; /* [9:8] */
__IO uint32_t c2idiv : 2; /* [11:10] */
__IO uint32_t c2df : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cm1_input_bit;
};
/**
* @brief tmr ccm2 register, offset:0x1C
*/
union
{
__IO uint32_t cm2;
/**
* @brief channel mode
*/
struct
{
__IO uint32_t c3c : 2; /* [1:0] */
__IO uint32_t c3oien : 1; /* [2] */
__IO uint32_t c3oben : 1; /* [3] */
__IO uint32_t c3octrl : 3; /* [6:4] */
__IO uint32_t c3osen : 1; /* [7] */
__IO uint32_t c4c : 2; /* [9:8] */
__IO uint32_t c4oien : 1; /* [10] */
__IO uint32_t c4oben : 1; /* [11] */
__IO uint32_t c4octrl : 3; /* [14:12] */
__IO uint32_t c4osen : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cm2_output_bit;
/**
* @brief input capture mode
*/
struct
{
__IO uint32_t c3c : 2; /* [1:0] */
__IO uint32_t c3idiv : 2; /* [3:2] */
__IO uint32_t c3df : 4; /* [7:4] */
__IO uint32_t c4c : 2; /* [9:8] */
__IO uint32_t c4idiv : 2; /* [11:10] */
__IO uint32_t c4df : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cm2_input_bit;
};
/**
* @brief tmr cce register, offset:0x20
*/
union
{
uint32_t cctrl;
struct
{
__IO uint32_t c1en : 1; /* [0] */
__IO uint32_t c1p : 1; /* [1] */
__IO uint32_t c1cen : 1; /* [2] */
__IO uint32_t c1cp : 1; /* [3] */
__IO uint32_t c2en : 1; /* [4] */
__IO uint32_t c2p : 1; /* [5] */
__IO uint32_t c2cen : 1; /* [6] */
__IO uint32_t c2cp : 1; /* [7] */
__IO uint32_t c3en : 1; /* [8] */
__IO uint32_t c3p : 1; /* [9] */
__IO uint32_t c3cen : 1; /* [10] */
__IO uint32_t c3cp : 1; /* [11] */
__IO uint32_t c4en : 1; /* [12] */
__IO uint32_t c4p : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} cctrl_bit;
};
/**
* @brief tmr cnt register, offset:0x24
*/
union
{
__IO uint32_t cval;
struct
{
__IO uint32_t cval : 32;/* [31:0] */
} cval_bit;
};
/**
* @brief tmr div, offset:0x28
*/
union
{
__IO uint32_t div;
struct
{
__IO uint32_t div : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} div_bit;
};
/**
* @brief tmr pr register, offset:0x2C
*/
union
{
__IO uint32_t pr;
struct
{
__IO uint32_t pr : 32;/* [31:0] */
} pr_bit;
};
/**
* @brief tmr rpr register, offset:0x30
*/
union
{
__IO uint32_t rpr;
struct
{
__IO uint32_t rpr : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} rpr_bit;
};
/**
* @brief tmr c1dt register, offset:0x34
*/
union
{
uint32_t c1dt;
struct
{
__IO uint32_t c1dt : 32;/* [31:0] */
} c1dt_bit;
};
/**
* @brief tmr c2dt register, offset:0x38
*/
union
{
uint32_t c2dt;
struct
{
__IO uint32_t c2dt : 32;/* [31:0] */
} c2dt_bit;
};
/**
* @brief tmr c3dt register, offset:0x3C
*/
union
{
__IO uint32_t c3dt;
struct
{
__IO uint32_t c3dt : 32;/* [31:0] */
} c3dt_bit;
};
/**
* @brief tmr c4dt register, offset:0x40
*/
union
{
__IO uint32_t c4dt;
struct
{
__IO uint32_t c4dt : 32;/* [31:0] */
} c4dt_bit;
};
/**
* @brief tmr brk register, offset:0x44
*/
union
{
__IO uint32_t brk;
struct
{
__IO uint32_t dtc : 8; /* [7:0] */
__IO uint32_t wpc : 2; /* [9:8] */
__IO uint32_t fcsodis : 1; /* [10] */
__IO uint32_t fcsoen : 1; /* [11] */
__IO uint32_t brken : 1; /* [12] */
__IO uint32_t brkv : 1; /* [13] */
__IO uint32_t aoen : 1; /* [14] */
__IO uint32_t oen : 1; /* [15] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} brk_bit;
};
/**
* @brief tmr dmactrl register, offset:0x48
*/
union
{
__IO uint32_t dmactrl;
struct
{
__IO uint32_t addr : 5; /* [4:0] */
__IO uint32_t reserved1 : 3; /* [7:5] */
__IO uint32_t dtb : 5; /* [12:8] */
__IO uint32_t reserved2 : 19;/* [31:13] */
} dmactrl_bit;
};
/**
* @brief tmr dmadt register, offset:0x4C
*/
union
{
__IO uint32_t dmadt;
struct
{
__IO uint32_t dmadt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} dmadt_bit;
};
} tmr_type;
/**
* @}
*/
#define TMR1 ((tmr_type *) TMR1_BASE)
#define TMR2 ((tmr_type *) TMR2_BASE)
#define TMR3 ((tmr_type *) TMR3_BASE)
#define TMR4 ((tmr_type *) TMR4_BASE)
#define TMR5 ((tmr_type *) TMR5_BASE)
#define TMR9 ((tmr_type *) TMR9_BASE)
#define TMR10 ((tmr_type *) TMR10_BASE)
#define TMR11 ((tmr_type *) TMR11_BASE)
/** @defgroup TMR_exported_functions
* @{
*/
void tmr_reset(tmr_type *tmr_x);
void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct);
void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct);
void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct);
void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div);
void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div);
void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir);
void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value);
void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value);
uint32_t tmr_counter_value_get(tmr_type *tmr_x);
void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value);
uint32_t tmr_div_value_get(tmr_type *tmr_x);
void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
tmr_output_config_type *tmr_output_struct);
void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
tmr_output_control_mode_type oc_mode);
void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value);
uint32_t tmr_period_value_get(tmr_type *tmr_x);
void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
uint32_t tmr_channel_value);
uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel);
void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
confirm_state new_state);
void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
confirm_state new_state);
void tmr_output_channel_switch_select(tmr_type *tmr_x, tmr_ch_switch_select_type switch_sel);
void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
confirm_state new_state);
void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state);
void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state);
void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state);
void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
tmr_channel_input_divider_type divider_factor);
void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state);
void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
uint16_t filter_value);
void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
tmr_channel_input_divider_type divider_factor);
void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect);
void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
tmr_channel_input_divider_type divider_factor);
void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode);
void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode);
void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select);
void tmr_hall_select(tmr_type *tmr_x, confirm_state new_state);
void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select);
void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state);
void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state);
void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state);
flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag);
void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event);
void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_internal_clock_set(tmr_type *tmr_x);
void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
tmr_polarity_active_type oc_polarity);
void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type \
ic1_polarity, tmr_input_polarity_type ic2_polarity);
void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
tmr_force_output_type force_output);
void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
tmr_dma_address_type dma_base_address);
void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

378
libraries/drivers/inc/at32f415_usart.h Normal file
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@@ -0,0 +1,378 @@
/**
**************************************************************************
* @file at32f415_usart.h
* @brief at32f415 usart header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_USART_H
#define __AT32F415_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup USART
* @{
*/
/** @defgroup USART_flags_definition
* @brief usart flag
* @{
*/
#define USART_PERR_FLAG ((uint32_t)0x00000001) /*!< usart parity error flag */
#define USART_FERR_FLAG ((uint32_t)0x00000002) /*!< usart framing error flag */
#define USART_NERR_FLAG ((uint32_t)0x00000004) /*!< usart noise error flag */
#define USART_ROERR_FLAG ((uint32_t)0x00000008) /*!< usart receiver overflow error flag */
#define USART_IDLEF_FLAG ((uint32_t)0x00000010) /*!< usart idle flag */
#define USART_RDBF_FLAG ((uint32_t)0x00000020) /*!< usart receive data buffer full flag */
#define USART_TDC_FLAG ((uint32_t)0x00000040) /*!< usart transmit data complete flag */
#define USART_TDBE_FLAG ((uint32_t)0x00000080) /*!< usart transmit data buffer empty flag */
#define USART_BFF_FLAG ((uint32_t)0x00000100) /*!< usart break frame flag */
#define USART_CTSCF_FLAG ((uint32_t)0x00000200) /*!< usart cts change flag */
/**
* @}
*/
/** @defgroup USART_interrupts_definition
* @brief usart interrupt
* @{
*/
#define USART_IDLE_INT MAKE_VALUE(0x0C,0x04) /*!< usart idle interrupt */
#define USART_RDBF_INT MAKE_VALUE(0x0C,0x05) /*!< usart receive data buffer full interrupt */
#define USART_TDC_INT MAKE_VALUE(0x0C,0x06) /*!< usart transmit data complete interrupt */
#define USART_TDBE_INT MAKE_VALUE(0x0C,0x07) /*!< usart transmit data buffer empty interrupt */
#define USART_PERR_INT MAKE_VALUE(0x0C,0x08) /*!< usart parity error interrupt */
#define USART_BF_INT MAKE_VALUE(0x10,0x06) /*!< usart break frame interrupt */
#define USART_ERR_INT MAKE_VALUE(0x14,0x00) /*!< usart error interrupt */
#define USART_CTSCF_INT MAKE_VALUE(0x14,0x0A) /*!< usart cts change interrupt */
/**
* @}
*/
/** @defgroup USART_exported_types
* @{
*/
/**
* @brief usart parity selection type
*/
typedef enum
{
USART_PARITY_NONE = 0x00, /*!< usart no parity */
USART_PARITY_EVEN = 0x01, /*!< usart even parity */
USART_PARITY_ODD = 0x02 /*!< usart odd parity */
} usart_parity_selection_type;
/**
* @brief usart wakeup mode type
*/
typedef enum
{
USART_WAKEUP_BY_IDLE_FRAME = 0x00, /*!< usart wakeup by idle frame */
USART_WAKEUP_BY_MATCHING_ID = 0x01 /*!< usart wakeup by matching id */
} usart_wakeup_mode_type;
/**
* @brief usart data bit num type
*/
typedef enum
{
USART_DATA_8BITS = 0x00, /*!< usart data size is 8 bits */
USART_DATA_9BITS = 0x01 /*!< usart data size is 9 bits */
} usart_data_bit_num_type;
/**
* @brief usart break frame bit num type
*/
typedef enum
{
USART_BREAK_10BITS = 0x00, /*!< usart lin mode berak frame detection 10 bits */
USART_BREAK_11BITS = 0x01 /*!< usart lin mode berak frame detection 11 bits */
} usart_break_bit_num_type;
/**
* @brief usart phase of the clock type
*/
typedef enum
{
USART_CLOCK_PHASE_1EDGE = 0x00, /*!< usart data capture is done on the clock leading edge */
USART_CLOCK_PHASE_2EDGE = 0x01 /*!< usart data capture is done on the clock trailing edge */
} usart_clock_phase_type;
/**
* @brief usart polarity of the clock type
*/
typedef enum
{
USART_CLOCK_POLARITY_LOW = 0x00, /*!< usart clock stay low level outside transmission window */
USART_CLOCK_POLARITY_HIGH = 0x01 /*!< usart clock stay high level outside transmission window */
} usart_clock_polarity_type;
/**
* @brief usart last bit clock pulse type
*/
typedef enum
{
USART_CLOCK_LAST_BIT_NONE = 0x00, /*!< usart clock pulse of the last data bit is not outputted */
USART_CLOCK_LAST_BIT_OUTPUT = 0x01 /*!< usart clock pulse of the last data bit is outputted */
} usart_lbcp_type;
/**
* @brief usart stop bit num type
*/
typedef enum
{
USART_STOP_1_BIT = 0x00, /*!< usart stop bits num is 1 */
USART_STOP_0_5_BIT = 0x01, /*!< usart stop bits num is 0.5 */
USART_STOP_2_BIT = 0x02, /*!< usart stop bits num is 2 */
USART_STOP_1_5_BIT = 0x03 /*!< usart stop bits num is 1.5 */
} usart_stop_bit_num_type;
/**
* @brief usart hardware flow control type
*/
typedef enum
{
USART_HARDWARE_FLOW_NONE = 0x00, /*!< usart without hardware flow */
USART_HARDWARE_FLOW_RTS = 0x01, /*!< usart hardware flow only rts */
USART_HARDWARE_FLOW_CTS = 0x02, /*!< usart hardware flow only cts */
USART_HARDWARE_FLOW_RTS_CTS = 0x03 /*!< usart hardware flow both rts and cts */
} usart_hardware_flow_control_type;
/**
* @brief type define usart register all
*/
typedef struct
{
/**
* @brief usart sts register, offset:0x00
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t perr : 1; /* [0] */
__IO uint32_t ferr : 1; /* [1] */
__IO uint32_t nerr : 1; /* [2] */
__IO uint32_t roerr : 1; /* [3] */
__IO uint32_t idlef : 1; /* [4] */
__IO uint32_t rdbf : 1; /* [5] */
__IO uint32_t tdc : 1; /* [6] */
__IO uint32_t tdbe : 1; /* [7] */
__IO uint32_t bff : 1; /* [8] */
__IO uint32_t ctscf : 1; /* [9] */
__IO uint32_t reserved1 : 22;/* [31:10] */
} sts_bit;
};
/**
* @brief usart dt register, offset:0x04
*/
union
{
__IO uint32_t dt;
struct
{
__IO uint32_t dt : 9; /* [8:0] */
__IO uint32_t reserved1 : 23;/* [31:9] */
} dt_bit;
};
/**
* @brief usart baudr register, offset:0x08
*/
union
{
__IO uint32_t baudr;
struct
{
__IO uint32_t div : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} baudr_bit;
};
/**
* @brief usart ctrl1 register, offset:0x0C
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t sbf : 1; /* [0] */
__IO uint32_t rm : 1; /* [1] */
__IO uint32_t ren : 1; /* [2] */
__IO uint32_t ten : 1; /* [3] */
__IO uint32_t idleien : 1; /* [4] */
__IO uint32_t rdbfien : 1; /* [5] */
__IO uint32_t tdcien : 1; /* [6] */
__IO uint32_t tdbeien : 1; /* [7] */
__IO uint32_t perrien : 1; /* [8] */
__IO uint32_t psel : 1; /* [9] */
__IO uint32_t pen : 1; /* [10] */
__IO uint32_t wum : 1; /* [11] */
__IO uint32_t dbn : 1; /* [12] */
__IO uint32_t uen : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} ctrl1_bit;
};
/**
* @brief usart ctrl2 register, offset:0x10
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t id : 4; /* [3:0] */
__IO uint32_t reserved1 : 1; /* [4] */
__IO uint32_t bfbn : 1; /* [5] */
__IO uint32_t bfien : 1; /* [6] */
__IO uint32_t reserved2 : 1; /* [7] */
__IO uint32_t lbcp : 1; /* [8] */
__IO uint32_t clkpha : 1; /* [9] */
__IO uint32_t clkpol : 1; /* [10] */
__IO uint32_t clken : 1; /* [11] */
__IO uint32_t stopbn : 2; /* [13:12] */
__IO uint32_t linen : 1; /* [14] */
__IO uint32_t reserved3 : 17;/* [31:15] */
} ctrl2_bit;
};
/**
* @brief usart ctrl3 register, offset:0x14
*/
union
{
__IO uint32_t ctrl3;
struct
{
__IO uint32_t errien : 1; /* [0] */
__IO uint32_t irdaen : 1; /* [1] */
__IO uint32_t irdalp : 1; /* [2] */
__IO uint32_t slben : 1; /* [3] */
__IO uint32_t scnacken : 1; /* [4] */
__IO uint32_t scmen : 1; /* [5] */
__IO uint32_t dmaren : 1; /* [6] */
__IO uint32_t dmaten : 1; /* [7] */
__IO uint32_t rtsen : 1; /* [8] */
__IO uint32_t ctsen : 1; /* [9] */
__IO uint32_t ctscfien : 1; /* [10] */
__IO uint32_t reserved1 : 21;/* [31:11] */
} ctrl3_bit;
};
/**
* @brief usart gdiv register, offset:0x18
*/
union
{
__IO uint32_t gdiv;
struct
{
__IO uint32_t isdiv : 8; /* [7:0] */
__IO uint32_t scgt : 8; /* [15:8] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} gdiv_bit;
};
} usart_type;
/**
* @}
*/
#define USART1 ((usart_type *) USART1_BASE)
#define USART2 ((usart_type *) USART2_BASE)
#if defined (AT32F415Cx) || defined (AT32F415Rx)
#define USART3 ((usart_type *) USART3_BASE)
#endif
#if defined (AT32F415Rx)
#define UART4 ((usart_type *) UART4_BASE)
#define UART5 ((usart_type *) UART5_BASE)
#endif
/** @defgroup USART_exported_functions
* @{
*/
void usart_reset(usart_type* usart_x);
void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit);
void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity);
void usart_enable(usart_type* usart_x, confirm_state new_state);
void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state);
void usart_receiver_enable(usart_type* usart_x, confirm_state new_state);
void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb);
void usart_clock_enable(usart_type* usart_x, confirm_state new_state);
void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state);
void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state);
void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state);
void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id);
void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode);
void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state);
void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit);
void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state);
void usart_data_transmit(usart_type* usart_x, uint16_t data);
uint16_t usart_data_receive(usart_type* usart_x);
void usart_break_send(usart_type* usart_x);
void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val);
void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val);
void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state);
void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state);
void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state);
void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag);
void usart_flag_clear(usart_type* usart_x, uint32_t flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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libraries/drivers/inc/at32f415_wdt.h Normal file
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/**
**************************************************************************
* @file at32f415_wdt.h
* @brief at32f415 wdt header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_WDT_H
#define __AT32F415_WDT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup WDT
* @{
*/
/** @defgroup WDT_flags_definition
* @brief wdt flag
* @{
*/
#define WDT_DIVF_UPDATE_FLAG ((uint16_t)0x0001) /*!< wdt division value update complete flag */
#define WDT_RLDF_UPDATE_FLAG ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
/**
* @}
*/
/** @defgroup WDT_exported_types
* @{
*/
/**
* @brief wdt division value type
*/
typedef enum
{
WDT_CLK_DIV_4 = 0x00, /*!< wdt clock divider value is 4 */
WDT_CLK_DIV_8 = 0x01, /*!< wdt clock divider value is 8 */
WDT_CLK_DIV_16 = 0x02, /*!< wdt clock divider value is 16 */
WDT_CLK_DIV_32 = 0x03, /*!< wdt clock divider value is 32 */
WDT_CLK_DIV_64 = 0x04, /*!< wdt clock divider value is 64 */
WDT_CLK_DIV_128 = 0x05, /*!< wdt clock divider value is 128 */
WDT_CLK_DIV_256 = 0x06 /*!< wdt clock divider value is 256 */
} wdt_division_type;
/**
* @brief wdt cmd value type
*/
typedef enum
{
WDT_CMD_LOCK = 0x0000, /*!< disable write protection command */
WDT_CMD_UNLOCK = 0x5555, /*!< enable write protection command */
WDT_CMD_ENABLE = 0xCCCC, /*!< enable wdt command */
WDT_CMD_RELOAD = 0xAAAA /*!< reload command */
} wdt_cmd_value_type;
/**
* @brief type define wdt register all
*/
typedef struct
{
/**
* @brief wdt cmd register, offset:0x00
*/
union
{
__IO uint32_t cmd;
struct
{
__IO uint32_t cmd : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cmd_bit;
};
/**
* @brief wdt div register, offset:0x04
*/
union
{
__IO uint32_t div;
struct
{
__IO uint32_t div : 3; /* [2:0] */
__IO uint32_t reserved1 : 29;/* [31:3] */
} div_bit;
};
/**
* @brief wdt rld register, offset:0x08
*/
union
{
__IO uint32_t rld;
struct
{
__IO uint32_t rld : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} rld_bit;
};
/**
* @brief wdt sts register, offset:0x0C
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t divf : 1; /* [0] */
__IO uint32_t rldf : 1; /* [1] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} sts_bit;
};
} wdt_type;
/**
* @}
*/
#define WDT ((wdt_type *) WDT_BASE)
/** @defgroup WDT_exported_functions
* @{
*/
void wdt_enable(void);
void wdt_counter_reload(void);
void wdt_reload_value_set(uint16_t reload_value);
void wdt_divider_set(wdt_division_type division);
void wdt_register_write_enable( confirm_state new_state);
flag_status wdt_flag_get(uint16_t wdt_flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f415_wwdt.h
* @brief at32f415 wwdt header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F415_WWDT_H
#define __AT32F415_WWDT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f415.h"
/** @addtogroup AT32F415_periph_driver
* @{
*/
/** @addtogroup WWDT
* @{
*/
/** @defgroup WWDT_enable_bit_definition
* @brief wwdt enable bit
* @{
*/
#define WWDT_EN_BIT ((uint32_t)0x00000080) /*!< wwdt enable bit */
/**
* @}
*/
/** @defgroup WWDT_exported_types
* @{
*/
/**
* @brief wwdt division type
*/
typedef enum
{
WWDT_PCLK1_DIV_4096 = 0x00, /*!< wwdt counter clock = (pclk1/4096)/1) */
WWDT_PCLK1_DIV_8192 = 0x01, /*!< wwdt counter clock = (pclk1/4096)/2) */
WWDT_PCLK1_DIV_16384 = 0x02, /*!< wwdt counter clock = (pclk1/4096)/4) */
WWDT_PCLK1_DIV_32768 = 0x03 /*!< wwdt counter clock = (pclk1/4096)/8) */
} wwdt_division_type;
/**
* @brief type define wwdt register all
*/
typedef struct
{
/**
* @brief wwdt ctrl register, offset:0x00
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t cnt : 7; /* [6:0] */
__IO uint32_t wwdten : 1; /* [7] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} ctrl_bit;
};
/**
* @brief wwdt cfg register, offset:0x04
*/
union
{
__IO uint32_t cfg;
struct
{
__IO uint32_t win : 7; /* [6:0] */
__IO uint32_t div : 2; /* [8:7] */
__IO uint32_t rldien : 1; /* [9] */
__IO uint32_t reserved1 : 22;/* [31:10] */
} cfg_bit;
};
/**
* @brief wwdt cfg register, offset:0x08
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t rldf : 1; /* [0] */
__IO uint32_t reserved1 : 31;/* [31:1] */
} sts_bit;
};
} wwdt_type;
/**
* @}
*/
#define WWDT ((wwdt_type *) WWDT_BASE)
/** @defgroup WWDT_exported_functions
* @{
*/
void wwdt_reset(void);
void wwdt_divider_set(wwdt_division_type division);
void wwdt_flag_clear(void);
void wwdt_enable(uint8_t wwdt_cnt);
void wwdt_interrupt_enable(void);
flag_status wwdt_flag_get(void);
flag_status wwdt_interrupt_flag_get(void);
void wwdt_counter_set(uint8_t wwdt_cnt);
void wwdt_window_counter_set(uint8_t window_cnt);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif