initial commit
This commit is contained in:
38
.clang-format
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38
.clang-format
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||||
---
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||||
BasedOnStyle: Microsoft
|
||||
Language: Cpp
|
||||
|
||||
###################################
|
||||
# indent conf
|
||||
###################################
|
||||
|
||||
UseTab: Never
|
||||
IndentWidth: 4
|
||||
TabWidth: 4
|
||||
ColumnLimit: 0
|
||||
AccessModifierOffset: -4
|
||||
NamespaceIndentation: All
|
||||
FixNamespaceComments: false
|
||||
BreakBeforeBraces: Linux
|
||||
|
||||
###################################
|
||||
# other styles
|
||||
###################################
|
||||
|
||||
#
|
||||
# for more conf, you can ref: https://clang.llvm.org/docs/ClangFormatStyleOptions.html
|
||||
#
|
||||
|
||||
AllowShortIfStatementsOnASingleLine: true
|
||||
|
||||
AllowShortLoopsOnASingleLine: true
|
||||
|
||||
AllowShortBlocksOnASingleLine: true
|
||||
|
||||
IndentCaseLabels: true
|
||||
|
||||
SortIncludes: false
|
||||
|
||||
AlignConsecutiveMacros: AcrossEmptyLines
|
||||
|
||||
AlignConsecutiveAssignments: Consecutive
|
||||
29
.eide/bc2d.arm.options.gcc.json
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29
.eide/bc2d.arm.options.gcc.json
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@@ -0,0 +1,29 @@
|
||||
{
|
||||
"version": 5,
|
||||
"beforeBuildTasks": [],
|
||||
"afterBuildTasks": [],
|
||||
"global": {
|
||||
"$float-abi-type": "softfp",
|
||||
"output-debug-info": "enable",
|
||||
"misc-control": "--specs=nosys.specs --specs=nano.specs"
|
||||
},
|
||||
"c/cpp-compiler": {
|
||||
"language-c": "c11",
|
||||
"language-cpp": "c++11",
|
||||
"optimization": "level-debug",
|
||||
"warnings": "all-warnings",
|
||||
"one-elf-section-per-function": true,
|
||||
"one-elf-section-per-data": true,
|
||||
"C_FLAGS": "",
|
||||
"CXX_FLAGS": ""
|
||||
},
|
||||
"asm-compiler": {
|
||||
"ASM_FLAGS": ""
|
||||
},
|
||||
"linker": {
|
||||
"output-format": "elf",
|
||||
"remove-unused-input-sections": true,
|
||||
"LD_FLAGS": "",
|
||||
"LIB_FLAGS": "-lm"
|
||||
}
|
||||
}
|
||||
24
.eide/bc2d.arm.options.v5.json
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24
.eide/bc2d.arm.options.v5.json
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@@ -0,0 +1,24 @@
|
||||
{
|
||||
"version": 4,
|
||||
"beforeBuildTasks": [],
|
||||
"afterBuildTasks": [],
|
||||
"global": {
|
||||
"use-microLIB": true,
|
||||
"output-debug-info": "enable"
|
||||
},
|
||||
"c/cpp-compiler": {
|
||||
"optimization": "level-0",
|
||||
"one-elf-section-per-function": true,
|
||||
"c99-mode": true,
|
||||
"C_FLAGS": "--diag_suppress=1 --diag_suppress=1295",
|
||||
"CXX_FLAGS": "--diag_suppress=1 --diag_suppress=1295",
|
||||
"warnings": "all-warnings"
|
||||
},
|
||||
"asm-compiler": {},
|
||||
"linker": {
|
||||
"output-format": "elf",
|
||||
"xo-base": "",
|
||||
"ro-base": "0x08000000",
|
||||
"rw-base": "0x20000000"
|
||||
}
|
||||
}
|
||||
31
.eide/bc2d.files.options.yml
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31
.eide/bc2d.files.options.yml
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|
||||
##########################################################################################
|
||||
# Append Compiler Options For Source Files
|
||||
#
|
||||
# syntax:
|
||||
# <your matcher expr>: <your compiler command>
|
||||
#
|
||||
# examples:
|
||||
# 'main.cpp': --cpp11 -Og ...
|
||||
# 'src/*.c': -gnu -O2 ...
|
||||
# 'src/lib/**/*.cpp': --cpp11 -Os ...
|
||||
# '!Application/*.c': -O0
|
||||
# '**/*.c': -O2 -gnu ...
|
||||
#
|
||||
# For more syntax, please refer to: https://www.npmjs.com/package/micromatch
|
||||
#
|
||||
##########################################################################################
|
||||
|
||||
version: '1.0'
|
||||
|
||||
#
|
||||
# for source files with filesystem paths
|
||||
#
|
||||
files:
|
||||
# './test/**/*.c': --c99
|
||||
|
||||
#
|
||||
# for source files with virtual paths
|
||||
#
|
||||
virtualPathFiles:
|
||||
# 'virtual_folder/**/*.c': --c99
|
||||
|
||||
141
.eide/eide.json
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141
.eide/eide.json
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@@ -0,0 +1,141 @@
|
||||
{
|
||||
"name": "BC2D",
|
||||
"type": "ARM",
|
||||
"dependenceList": [],
|
||||
"srcDirs": [
|
||||
".eide/deps",
|
||||
"3rd-part"
|
||||
],
|
||||
"virtualFolder": {
|
||||
"name": "<virtual_root>",
|
||||
"files": [],
|
||||
"folders": [
|
||||
{
|
||||
"name": "cmsis",
|
||||
"files": [
|
||||
{
|
||||
"path": "libraries/cmsis/cm4/device_support/startup/gcc/startup_at32f413.s"
|
||||
},
|
||||
{
|
||||
"path": "libraries/cmsis/cm4/device_support/system_at32f413.c"
|
||||
}
|
||||
],
|
||||
"folders": []
|
||||
},
|
||||
{
|
||||
"name": "firmware",
|
||||
"files": [
|
||||
{
|
||||
"path": "libraries/drivers/src/at32f413_can.c"
|
||||
},
|
||||
{
|
||||
"path": "libraries/drivers/src/at32f413_crm.c"
|
||||
},
|
||||
{
|
||||
"path": "libraries/drivers/src/at32f413_debug.c"
|
||||
},
|
||||
{
|
||||
"path": "libraries/drivers/src/at32f413_exint.c"
|
||||
},
|
||||
{
|
||||
"path": "libraries/drivers/src/at32f413_flash.c"
|
||||
},
|
||||
{
|
||||
"path": "libraries/drivers/src/at32f413_gpio.c"
|
||||
},
|
||||
{
|
||||
"path": "libraries/drivers/src/at32f413_misc.c"
|
||||
},
|
||||
{
|
||||
"path": "libraries/drivers/src/at32f413_pwc.c"
|
||||
},
|
||||
{
|
||||
"path": "libraries/drivers/src/at32f413_tmr.c"
|
||||
},
|
||||
{
|
||||
"path": "libraries/drivers/src/at32f413_usart.c"
|
||||
}
|
||||
],
|
||||
"folders": []
|
||||
},
|
||||
{
|
||||
"name": "user",
|
||||
"files": [
|
||||
{
|
||||
"path": "project/src/at32f413_int.c"
|
||||
},
|
||||
{
|
||||
"path": "project/src/at32f413_wk_config.c"
|
||||
},
|
||||
{
|
||||
"path": "project/src/main.c"
|
||||
}
|
||||
],
|
||||
"folders": []
|
||||
}
|
||||
]
|
||||
},
|
||||
"outDir": "build",
|
||||
"deviceName": null,
|
||||
"packDir": null,
|
||||
"miscInfo": {
|
||||
"uid": "9d909db3024271625a98879e53e2d396"
|
||||
},
|
||||
"targets": {
|
||||
"BC2D": {
|
||||
"excludeList": [],
|
||||
"toolchain": "GCC",
|
||||
"compileConfig": {
|
||||
"cpuType": "Cortex-M4",
|
||||
"floatingPointHardware": "single",
|
||||
"scatterFilePath": "${workspaceFolder}\\libraries\\cmsis\\cm4\\device_support\\startup\\gcc\\linker\\AT32F413xB_FLASH.ld",
|
||||
"useCustomScatterFile": true,
|
||||
"storageLayout": {
|
||||
"RAM": [],
|
||||
"ROM": []
|
||||
},
|
||||
"options": "null"
|
||||
},
|
||||
"uploader": "OpenOCD",
|
||||
"uploadConfig": {
|
||||
"bin": "",
|
||||
"target": "at32f413xx",
|
||||
"interface": "cmsis-dap",
|
||||
"baseAddr": "0x08000000"
|
||||
},
|
||||
"uploadConfigMap": {
|
||||
"JLink": {
|
||||
"bin": "",
|
||||
"baseAddr": "",
|
||||
"cpuInfo": {
|
||||
"vendor": "null",
|
||||
"cpuName": "null"
|
||||
},
|
||||
"proType": 1,
|
||||
"speed": 8000,
|
||||
"otherCmds": ""
|
||||
}
|
||||
},
|
||||
"custom_dep": {
|
||||
"name": "default",
|
||||
"incList": [
|
||||
"libraries/drivers/inc",
|
||||
"libraries/cmsis/cm4/core_support",
|
||||
"libraries/cmsis/cm4/device_support",
|
||||
"project/inc",
|
||||
".cmsis/include",
|
||||
"project/MDK_V5/RTE/_BC2D",
|
||||
".eide/deps",
|
||||
"3rd-part/dwt_delay"
|
||||
],
|
||||
"libList": [],
|
||||
"sourceDirList": [],
|
||||
"defineList": [
|
||||
"AT32F413CBT7",
|
||||
"USE_STDPERIPH_DRIVER"
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
"version": "3.3"
|
||||
}
|
||||
15
.gitignore
vendored
Normal file
15
.gitignore
vendored
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@@ -0,0 +1,15 @@
|
||||
# dot files
|
||||
/.vscode/launch.json
|
||||
/.settings
|
||||
/.eide/log
|
||||
/.eide.usr.ctx.json
|
||||
|
||||
# project out
|
||||
/build
|
||||
/bin
|
||||
/obj
|
||||
/out
|
||||
|
||||
# eide template
|
||||
*.ept
|
||||
*.eide-template
|
||||
3
.vscode/settings.json
vendored
Normal file
3
.vscode/settings.json
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
{
|
||||
"sonarlint.pathToCompileCommands": "${workspaceFolder}\\build\\BC2D\\compile_commands.json"
|
||||
}
|
||||
40
.vscode/tasks.json
vendored
Normal file
40
.vscode/tasks.json
vendored
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@@ -0,0 +1,40 @@
|
||||
{
|
||||
"version": "2.0.0",
|
||||
"tasks": [
|
||||
{
|
||||
"label": "build",
|
||||
"type": "shell",
|
||||
"command": "${command:eide.project.build}",
|
||||
"group": "build",
|
||||
"problemMatcher": []
|
||||
},
|
||||
{
|
||||
"label": "flash",
|
||||
"type": "shell",
|
||||
"command": "${command:eide.project.uploadToDevice}",
|
||||
"group": "build",
|
||||
"problemMatcher": []
|
||||
},
|
||||
{
|
||||
"label": "build and flash",
|
||||
"type": "shell",
|
||||
"command": "${command:eide.project.buildAndFlash}",
|
||||
"group": "build",
|
||||
"problemMatcher": []
|
||||
},
|
||||
{
|
||||
"label": "rebuild",
|
||||
"type": "shell",
|
||||
"command": "${command:eide.project.rebuild}",
|
||||
"group": "build",
|
||||
"problemMatcher": []
|
||||
},
|
||||
{
|
||||
"label": "clean",
|
||||
"type": "shell",
|
||||
"command": "${command:eide.project.clean}",
|
||||
"group": "build",
|
||||
"problemMatcher": []
|
||||
}
|
||||
]
|
||||
}
|
||||
21
3rd-part/dwt_delay/LICENSE
Normal file
21
3rd-part/dwt_delay/LICENSE
Normal file
@@ -0,0 +1,21 @@
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2017 and so on
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
84
3rd-part/dwt_delay/README.md
Normal file
84
3rd-part/dwt_delay/README.md
Normal file
@@ -0,0 +1,84 @@
|
||||
# dwt_delay
|
||||
Microseconds delay lib based on DWT for STM32 or whatever ARM supporting it.
|
||||
Just include `dwt_delay.h` in your project, call `DWT_Init()` and then use delays as needed.
|
||||
|
||||
Depending on MCU used, you may need to include another header file (with MCU peripherals defines) in `dwt_delay.h`.
|
||||
The `stm32f1xx.h` is included by default, allowing STM32F1xx to start out of the box.
|
||||
If you don't use STM32 MCU or CubeMX, read a section at the end.
|
||||
|
||||
Functions are named as DWT_* to be HAL-alike. Feel free to do whatever you like with this lib,
|
||||
change names, indents, coding style, use it in LHC firmware.
|
||||
|
||||
|
||||
## Example
|
||||
|
||||
```c
|
||||
/* main.c */
|
||||
|
||||
#include "dwt_delay.h"
|
||||
|
||||
|
||||
void main (void)
|
||||
{
|
||||
// Init section of your code
|
||||
DWT_Init();
|
||||
|
||||
|
||||
while(1) {
|
||||
// Delay for 42us
|
||||
DWT_Delay(42);
|
||||
}
|
||||
|
||||
}
|
||||
```
|
||||
|
||||
## Notes on Cortex-M0/0+/1
|
||||
Unfortunately, these are not supported, since cores have no access to DWT. CMSIS library states:
|
||||
```
|
||||
Cortex-M0/0+/1 Core Debug Registers are only accessible over DAP and not via processor
|
||||
```
|
||||
You may want a delay function based on hardware timer instead.
|
||||
|
||||
|
||||
## What about Cortex-M35/55/85?
|
||||
I don't have any of these to check, but in theory they are supported.
|
||||
Anyway you have to change `CoreDebug` to `DCB`, because `CoreDebug` is deprecated in these cores.
|
||||
|
||||
Hence, init sequence should be something like:
|
||||
```c
|
||||
DCB->DEMCR |= DCB_DEMCR_TRCENA_Msk;
|
||||
```
|
||||
|
||||
|
||||
## I'm not with STM but need microsec delays
|
||||
There's an option to try! Also suits those, who use STM32, but dont use HAL/LL libs.
|
||||
|
||||
Include a CMSIS header file according to your core in `dwt_delay.c` and change `SystemCoreClock`
|
||||
variable to whatever you probably have in the project representing clock frequency (in Hz).
|
||||
|
||||
Something like this:
|
||||
```c
|
||||
// In dwt_delay.c
|
||||
|
||||
#include "dwt_delay.h"
|
||||
#include "core_cm4.h" // CMSIS header
|
||||
|
||||
#define SystemCoreClock NameOfTheGlobalVariableInYourProject_or_AnotherDefine
|
||||
// or at least
|
||||
#define SystemCoreClock 48000000UL // Clock is 48Mhz
|
||||
...
|
||||
```
|
||||
|
||||
|
||||
## Changelog
|
||||
- **2018-01-06**
|
||||
This lib emerged.
|
||||
|
||||
- **2019-02-19**
|
||||
Overflow check added.
|
||||
|
||||
- **2019-03-26**
|
||||
Typo in definition fixed. Got back to short and simpler function.
|
||||
|
||||
- **2023-11-21**
|
||||
Now it is MIT License. Added warning for Cortex-M0/0+/1 and notes regarding other Cortex-M cores.
|
||||
73
3rd-part/dwt_delay/dwt_delay.c
Normal file
73
3rd-part/dwt_delay/dwt_delay.c
Normal file
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Simple microseconds delay routine, utilizing ARM's DWT
|
||||
* (Data Watchpoint and Trace Unit) and HAL library.
|
||||
* Intended to use with gcc compiler, but I hope it can be used
|
||||
* with any other C compiler across the Universe (provided that
|
||||
* ARM and CMSIS already invented) :)
|
||||
* Max K
|
||||
*
|
||||
*
|
||||
* This file is part of DWT_Delay package.
|
||||
* DWT_Delay is free software: you can redistribute it and/or modify it
|
||||
* under the terms of the MIT License
|
||||
*/
|
||||
|
||||
// #include "stm32f1xx_hal.h" // change to whatever MCU or Cortex-M core you use
|
||||
#include "dwt_delay.h"
|
||||
#include "at32f413.h" // CMSIS header
|
||||
|
||||
/**
|
||||
* Initialization routine.
|
||||
* You might need to enable access to DWT registers on Cortex-M7
|
||||
* DWT->LAR = 0xC5ACCE55
|
||||
*/
|
||||
void DWT_Init(void)
|
||||
{
|
||||
if (!(CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)) {
|
||||
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
DWT->CYCCNT = 0;
|
||||
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
|
||||
}
|
||||
}
|
||||
|
||||
#if DWT_DELAY_NEWBIE
|
||||
/**
|
||||
* If you are a newbie and see magic in DWT_Delay, consider this more
|
||||
* illustrative function, where you explicitly determine a counter
|
||||
* value when delay should stop while keeping things in bounds of uint32.
|
||||
*
|
||||
* @param uint32_t us Number of microseconds to delay for
|
||||
*/
|
||||
void DWT_Delay(uint32_t us)
|
||||
{
|
||||
uint32_t startTick = DWT->CYCCNT,
|
||||
targetTick = DWT->CYCCNT + us * (SystemCoreClock/1000000);
|
||||
|
||||
// Must check if target tick is out of bounds and overflowed
|
||||
if (targetTick > startTick) {
|
||||
// Not overflowed
|
||||
while (DWT->CYCCNT < targetTick);
|
||||
} else {
|
||||
// Overflowed
|
||||
while (DWT->CYCCNT > startTick || DWT->CYCCNT < targetTick);
|
||||
}
|
||||
}
|
||||
#else
|
||||
/**
|
||||
* Delay routine itself.
|
||||
* Time is in microseconds (1/1000000th of a second), not to be
|
||||
* confused with millisecond (1/1000th).
|
||||
*
|
||||
* No need to check an overflow. Let it just tick :)
|
||||
*
|
||||
* @param uint32_t us Number of microseconds to delay for
|
||||
*/
|
||||
void DWT_Delay(uint32_t us)
|
||||
{
|
||||
uint32_t startTick = DWT->CYCCNT,
|
||||
delayTicks = us * (SystemCoreClock/1000000);
|
||||
|
||||
while (DWT->CYCCNT - startTick < delayTicks);
|
||||
}
|
||||
|
||||
#endif
|
||||
31
3rd-part/dwt_delay/dwt_delay.h
Normal file
31
3rd-part/dwt_delay/dwt_delay.h
Normal file
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Simple microseconds delay routine, utilizing ARM's DWT
|
||||
* (Data Watchpoint and Trace Unit) and HAL library.
|
||||
* Intended to use with gcc compiler, but I hope it can be used
|
||||
* with any other C compiler across the Universe (provided that
|
||||
* ARM and CMSIS already invented) :)
|
||||
* Max K
|
||||
*
|
||||
*
|
||||
* This file is part of DWT_Delay package.
|
||||
* DWT_Delay is free software: you can redistribute it and/or modify it
|
||||
* under the terms of the MIT License.
|
||||
*/
|
||||
|
||||
#if defined(__CORTEX_M) && __CORTEX_M < 3U
|
||||
#warning DWT_Delay in useless in this project since DWT unit is not accessible \
|
||||
by processor on Cortex-M0/0+/1 cores. You may want to implement microdelays \
|
||||
with hardware timer.
|
||||
#endif
|
||||
|
||||
#ifndef INC_DWT_DELAY_H_
|
||||
#define INC_DWT_DELAY_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define DWT_DELAY_NEWBIE 0
|
||||
|
||||
void DWT_Init(void);
|
||||
void DWT_Delay(uint32_t us);
|
||||
|
||||
#endif /* INC_DWT_DELAY_H_ */
|
||||
148
BC2D.ATWP
Normal file
148
BC2D.ATWP
Normal file
@@ -0,0 +1,148 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root>
|
||||
<MCUInfo>
|
||||
<MCUSerials>AT32F413</MCUSerials>
|
||||
<MCUName>AT32F413CBT7</MCUName>
|
||||
<MCUPackage>LQFP48</MCUPackage>
|
||||
</MCUInfo>
|
||||
<CAN1>
|
||||
<Mode>
|
||||
<ModeSub name="CAN_Activate" value="TRUE"/>
|
||||
</Mode>
|
||||
<Parameters>
|
||||
<ParametersSub name="BaudRate" value="500"/>
|
||||
<ParametersSub name="Sample_Point" value="87.5"/>
|
||||
<ParametersSub name="BaudRate_Division" value="25"/>
|
||||
<ParametersSub name="BTS1" value="CAN_BTS1_6TQ"/>
|
||||
<ParametersSub name="BTS2" value="CAN_BTS2_1TQ"/>
|
||||
<ParametersSub name="RSAW" value="CAN_RSAW_1TQ"/>
|
||||
</Parameters>
|
||||
</CAN1>
|
||||
<CRM>
|
||||
<Mode>
|
||||
<ModeSub name="HEXT" value="HEXT-External-Oscillator"/>
|
||||
</Mode>
|
||||
<Parameters>
|
||||
<ParametersSub name="HEXT" value="HEXT_CRYSTAL"/>
|
||||
</Parameters>
|
||||
</CRM>
|
||||
<DEBUG>
|
||||
<Mode>
|
||||
<ModeSub name="Debug interface" value="SWD"/>
|
||||
</Mode>
|
||||
</DEBUG>
|
||||
<PWC>
|
||||
<Mode>
|
||||
<ModeSub name="Voltage-Monitoring" value="TRUE"/>
|
||||
</Mode>
|
||||
<Parameters>
|
||||
<ParametersSub name="BoundarySelect" value="PWC_PVM_VOLTAGE_2V8"/>
|
||||
</Parameters>
|
||||
</PWC>
|
||||
<TMR1>
|
||||
<Mode>
|
||||
<ModeSub name="Channel1 mode" value="Output_CH1_CH1C"/>
|
||||
<ModeSub name="Channel2 mode" value="Output_CH2_CH2C"/>
|
||||
<ModeSub name="Activated" value="TRUE"/>
|
||||
</Mode>
|
||||
</TMR1>
|
||||
<TMR2>
|
||||
<Mode>
|
||||
<ModeSub name="Multi-Channels" value="Encoder_Mode"/>
|
||||
<ModeSub name="Activated" value="TRUE"/>
|
||||
</Mode>
|
||||
</TMR2>
|
||||
<TMR3>
|
||||
<Mode>
|
||||
<ModeSub name="Multi-Channels" value="Encoder_Mode"/>
|
||||
<ModeSub name="Activated" value="TRUE"/>
|
||||
</Mode>
|
||||
</TMR3>
|
||||
<TMR4>
|
||||
<Mode>
|
||||
<ModeSub name="Activated" value="TRUE"/>
|
||||
</Mode>
|
||||
<Parameters>
|
||||
<ParametersSub name="DividerValue" value="999"/>
|
||||
<ParametersSub name="Period" value="199"/>
|
||||
</Parameters>
|
||||
</TMR4>
|
||||
<USART2>
|
||||
<Mode>
|
||||
<ModeSub name="Mode" value="Asynchronous"/>
|
||||
</Mode>
|
||||
<Parameters>
|
||||
<ParametersSub name="Mode" value="MODE_RX"/>
|
||||
</Parameters>
|
||||
</USART2>
|
||||
<NVIC>
|
||||
<SysTick_Handler>0;0;0</SysTick_Handler>
|
||||
<PVM_IRQHandler>0;0;0</PVM_IRQHandler>
|
||||
<FLASH_IRQHandler>0;0;0</FLASH_IRQHandler>
|
||||
<CRM_IRQHandler>0;0;0</CRM_IRQHandler>
|
||||
<USBFS_H_CAN1_TX_IRQHandler>0;0;0</USBFS_H_CAN1_TX_IRQHandler>
|
||||
<USBFS_L_CAN1_RX0_IRQHandler>0;0;0</USBFS_L_CAN1_RX0_IRQHandler>
|
||||
<CAN1_RX1_IRQHandler>0;0;0</CAN1_RX1_IRQHandler>
|
||||
<CAN1_SE_IRQHandler>0;0;0</CAN1_SE_IRQHandler>
|
||||
<TMR1_BRK_TMR9_IRQHandler>0;0;0</TMR1_BRK_TMR9_IRQHandler>
|
||||
<TMR1_OVF_TMR10_IRQHandler>0;0;0</TMR1_OVF_TMR10_IRQHandler>
|
||||
<TMR1_TRG_HALL_TMR11_IRQHandler>0;0;0</TMR1_TRG_HALL_TMR11_IRQHandler>
|
||||
<TMR1_CH_IRQHandler>0;0;0</TMR1_CH_IRQHandler>
|
||||
<TMR2_GLOBAL_IRQHandler>0;0;0</TMR2_GLOBAL_IRQHandler>
|
||||
<TMR3_GLOBAL_IRQHandler>0;0;0</TMR3_GLOBAL_IRQHandler>
|
||||
<TMR4_GLOBAL_IRQHandler>1;0;0</TMR4_GLOBAL_IRQHandler>
|
||||
<USART2_IRQHandler>0;0;0</USART2_IRQHandler>
|
||||
</NVIC>
|
||||
<ClockConfiguration>
|
||||
<rtcsel>0</rtcsel>
|
||||
<hext>16.000000</hext>
|
||||
<pllhextdiv>1</pllhextdiv>
|
||||
<pllrcs>0</pllrcs>
|
||||
<pllmult>25</pllmult>
|
||||
<sclkselect>1</sclkselect>
|
||||
<ahbdiv>1</ahbdiv>
|
||||
<apb1div>2</apb1div>
|
||||
<apb2div>2</apb2div>
|
||||
<usbdiv>4.0</usbdiv>
|
||||
<hicktousb>1</hicktousb>
|
||||
<hicktosclk>0</hicktosclk>
|
||||
<clkout>0</clkout>
|
||||
<clkoutdiv>1</clkoutdiv>
|
||||
<adcdiv>4</adcdiv>
|
||||
</ClockConfiguration>
|
||||
<PINInfo>
|
||||
<PinSub pinname="PD0/HEXT_IN" signalname="CRM_HEXT_IN" signaltype="2"/>
|
||||
<PinSub pinname="PD1/HEXT_OUT" signalname="CRM_HEXT_OUT" signaltype="2"/>
|
||||
<PinSub pinname="PA0/WKUP" signalname="TMR2_CH1" signaltype="2"/>
|
||||
<PinSub pinname="PA1" signalname="TMR2_CH2" signaltype="2"/>
|
||||
<PinSub pinname="PA2" signalname="USART2_TX" signaltype="2"/>
|
||||
<PinSub pinname="PA3" signalname="USART2_RX" signaltype="2"/>
|
||||
<PinSub pinname="PA6" signalname="TMR3_CH1" signaltype="2"/>
|
||||
<PinSub pinname="PA7" signalname="TMR3_CH2" signaltype="2"/>
|
||||
<PinSub pinname="PB13" signalname="TMR1_CH1C" signaltype="2"/>
|
||||
<PinSub pinname="PB14" signalname="TMR1_CH2C" signaltype="2"/>
|
||||
<PinSub pinname="PB15" signalname="GPIO_Output" signaltype="3"/>
|
||||
<PinSub pinname="PA8" signalname="TMR1_CH1" signaltype="2"/>
|
||||
<PinSub pinname="PA9" signalname="TMR1_CH2" signaltype="2"/>
|
||||
<PinSub pinname="PA11" signalname="CAN1_RX" signaltype="2"/>
|
||||
<PinSub pinname="PA12" signalname="CAN1_TX" signaltype="2"/>
|
||||
<PinSub pinname="PA13" signalname="DEBUG_JTMS_SWDIO" signaltype="2"/>
|
||||
<PinSub pinname="PA14" signalname="DEBUG_JTCK_SWCLK" signaltype="2"/>
|
||||
<PinSub pinname="PB3" signalname="GPIO_Input" signaltype="3"/>
|
||||
<PinSub pinname="PB4" signalname="GPIO_Input" signaltype="3"/>
|
||||
<PinSub pinname="PB5" signalname="GPIO_Input" signaltype="3"/>
|
||||
<PinSub pinname="PB6" signalname="GPIO_Input" signaltype="3"/>
|
||||
</PINInfo>
|
||||
<ProjectInfomation>
|
||||
<ProjectName>BC2D</ProjectName>
|
||||
<ProjectLocation>C:/Users/ForgotDoge/Desktop</ProjectLocation>
|
||||
<ToolchainIDE>MDK_V5</ToolchainIDE>
|
||||
<KeepUserCode>true</KeepUserCode>
|
||||
<MinHeapSize>0x200</MinHeapSize>
|
||||
<MinStackSize>0x400</MinStackSize>
|
||||
<UseFirmware>true</UseFirmware>
|
||||
<UseFirmwareZip>true</UseFirmwareZip>
|
||||
<FirmwarePath>C:/Users/ForgotDoge/Desktop/AT32_Work_Bench_V1.0.03/AT32F413_Firmware_Library_V2.1.3.zip</FirmwarePath>
|
||||
<FirmwareFolderPath></FirmwareFolderPath>
|
||||
</ProjectInfomation>
|
||||
</Root>
|
||||
49
BC2D.code-workspace
Normal file
49
BC2D.code-workspace
Normal file
@@ -0,0 +1,49 @@
|
||||
{
|
||||
"folders": [
|
||||
{
|
||||
"path": "."
|
||||
}
|
||||
],
|
||||
"settings": {
|
||||
"files.autoGuessEncoding": true,
|
||||
"C_Cpp.default.configurationProvider": "cl.eide",
|
||||
"C_Cpp.errorSquiggles": "disabled",
|
||||
"files.associations": {
|
||||
".eideignore": "ignore",
|
||||
"*.a51": "a51",
|
||||
"*.h": "c",
|
||||
"*.c": "c",
|
||||
"*.hxx": "cpp",
|
||||
"*.hpp": "cpp",
|
||||
"*.c++": "cpp",
|
||||
"*.cpp": "cpp",
|
||||
"*.cxx": "cpp",
|
||||
"*.cc": "cpp"
|
||||
},
|
||||
"[yaml]": {
|
||||
"editor.insertSpaces": true,
|
||||
"editor.tabSize": 4,
|
||||
"editor.autoIndent": "advanced"
|
||||
},
|
||||
"workbench.colorCustomizations": {
|
||||
"activityBar.background": "#14117C",
|
||||
"titleBar.activeBackground": "#1D18AE",
|
||||
"titleBar.activeForeground": "#FAFAFE"
|
||||
}
|
||||
},
|
||||
"extensions": {
|
||||
"recommendations": [
|
||||
"cl.eide",
|
||||
"keroc.hex-fmt",
|
||||
"xiaoyongdong.srecord",
|
||||
"hars.cppsnippets",
|
||||
"zixuanwang.linkerscript",
|
||||
"redhat.vscode-yaml",
|
||||
"IBM.output-colorizer",
|
||||
"cschlosser.doxdocgen",
|
||||
"ms-vscode.vscode-serial-monitor",
|
||||
"dan-c-underwood.arm",
|
||||
"marus25.cortex-debug"
|
||||
]
|
||||
}
|
||||
}
|
||||
517
libraries/cmsis/cm4/core_support/arm_common_tables.h
Normal file
517
libraries/cmsis/cm4/core_support/arm_common_tables.h
Normal file
@@ -0,0 +1,517 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
* Description: Extern declaration for common tables
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
/* Double Precision Float CFFT twiddles */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024)
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16)
|
||||
extern const uint64_t twiddleCoefF64_16[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32)
|
||||
extern const uint64_t twiddleCoefF64_32[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64)
|
||||
extern const uint64_t twiddleCoefF64_64[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128)
|
||||
extern const uint64_t twiddleCoefF64_128[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256)
|
||||
extern const uint64_t twiddleCoefF64_256[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512)
|
||||
extern const uint64_t twiddleCoefF64_512[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024)
|
||||
extern const uint64_t twiddleCoefF64_1024[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048)
|
||||
extern const uint64_t twiddleCoefF64_2048[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096)
|
||||
extern const uint64_t twiddleCoefF64_4096[8192];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16)
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64)
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256)
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024)
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096)
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16)
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64)
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256)
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16)
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64)
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256)
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
/* Double Precision Float RFFT twiddles */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)
|
||||
extern const uint64_t twiddleCoefF64_rfft_32[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)
|
||||
extern const uint64_t twiddleCoefF64_rfft_64[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)
|
||||
extern const uint64_t twiddleCoefF64_rfft_128[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)
|
||||
extern const uint64_t twiddleCoefF64_rfft_256[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)
|
||||
extern const uint64_t twiddleCoefF64_rfft_512[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)
|
||||
extern const uint64_t twiddleCoefF64_rfft_1024[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)
|
||||
extern const uint64_t twiddleCoefF64_rfft_2048[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)
|
||||
extern const uint64_t twiddleCoefF64_rfft_4096[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
/* Double precision floating-point bit reversal tables */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16)
|
||||
#define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12)
|
||||
extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32)
|
||||
#define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24)
|
||||
extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64)
|
||||
#define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128)
|
||||
#define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112)
|
||||
extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256)
|
||||
#define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240)
|
||||
extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512)
|
||||
#define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480)
|
||||
extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024)
|
||||
#define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048)
|
||||
#define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096)
|
||||
#define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
/* floating-point bit reversal tables */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16)
|
||||
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32)
|
||||
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64)
|
||||
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128)
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256)
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512)
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024)
|
||||
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048)
|
||||
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096)
|
||||
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32)
|
||||
extern const float32_t realCoefA[8192];
|
||||
extern const float32_t realCoefB[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31)
|
||||
extern const q31_t realCoefAQ31[8192];
|
||||
extern const q31_t realCoefBQ31[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15)
|
||||
extern const q15_t realCoefAQ15[8192];
|
||||
extern const q15_t realCoefBQ15[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128)
|
||||
extern const float32_t Weights_128[256];
|
||||
extern const float32_t cos_factors_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512)
|
||||
extern const float32_t Weights_512[1024];
|
||||
extern const float32_t cos_factors_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048)
|
||||
extern const float32_t Weights_2048[4096];
|
||||
extern const float32_t cos_factors_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192)
|
||||
extern const float32_t Weights_8192[16384];
|
||||
extern const float32_t cos_factors_8192[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128)
|
||||
extern const q15_t WeightsQ15_128[256];
|
||||
extern const q15_t cos_factorsQ15_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512)
|
||||
extern const q15_t WeightsQ15_512[1024];
|
||||
extern const q15_t cos_factorsQ15_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048)
|
||||
extern const q15_t WeightsQ15_2048[4096];
|
||||
extern const q15_t cos_factorsQ15_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192)
|
||||
extern const q15_t WeightsQ15_8192[16384];
|
||||
extern const q15_t cos_factorsQ15_8192[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128)
|
||||
extern const q31_t WeightsQ31_128[256];
|
||||
extern const q31_t cos_factorsQ31_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512)
|
||||
extern const q31_t WeightsQ31_512[1024];
|
||||
extern const q31_t cos_factorsQ31_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048)
|
||||
extern const q31_t WeightsQ31_2048[4096];
|
||||
extern const q31_t cos_factorsQ31_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192)
|
||||
extern const q31_t WeightsQ31_8192[16384];
|
||||
extern const q31_t cos_factorsQ31_8192[8192];
|
||||
#endif
|
||||
|
||||
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15)
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31)
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32)
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31)
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15)
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if defined(ARM_MATH_MVEI)
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
|
||||
extern const q31_t sqrtTable_Q31[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_MVEI)
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
|
||||
extern const q15_t sqrtTable_Q15[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
#endif
|
||||
|
||||
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */
|
||||
|
||||
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
extern const float32_t exp_tab[8];
|
||||
extern const float32_t __logf_lut_f32[8];
|
||||
#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM))
|
||||
extern const unsigned char hwLUT[256];
|
||||
#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
|
||||
76
libraries/cmsis/cm4/core_support/arm_const_structs.h
Normal file
76
libraries/cmsis/cm4/core_support/arm_const_structs.h
Normal file
@@ -0,0 +1,76 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
* Description: Constant structs that are initialized for user convenience.
|
||||
* For example, some can be given as arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096;
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
348
libraries/cmsis/cm4/core_support/arm_helium_utils.h
Normal file
348
libraries/cmsis/cm4/core_support/arm_helium_utils.h
Normal file
@@ -0,0 +1,348 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_helium_utils.h
|
||||
* Description: Utility functions for Helium development
|
||||
*
|
||||
* $Date: 09. September 2019
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_UTILS_HELIUM_H_
|
||||
#define _ARM_UTILS_HELIUM_H_
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEF and MVEI
|
||||
|
||||
***************************************/
|
||||
#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)
|
||||
|
||||
#define INACTIVELANE 0 /* inactive lane content */
|
||||
|
||||
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEF only
|
||||
|
||||
***************************************/
|
||||
#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF)
|
||||
|
||||
__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in)
|
||||
{
|
||||
float32_t acc;
|
||||
|
||||
acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) +
|
||||
vgetq_lane(in, 2) + vgetq_lane(in, 3);
|
||||
|
||||
return acc;
|
||||
}
|
||||
|
||||
/* newton initial guess */
|
||||
#define INVSQRT_MAGIC_F32 0x5f3759df
|
||||
|
||||
#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\
|
||||
{ \
|
||||
float32x4_t tmp; \
|
||||
\
|
||||
/* tmp = xhalf * x * x */ \
|
||||
tmp = vmulq(xStart, xStart); \
|
||||
tmp = vmulq(tmp, xHalf); \
|
||||
/* (1.5f - xhalf * x * x) */ \
|
||||
tmp = vsubq(vdupq_n_f32(1.5f), tmp); \
|
||||
/* x = x*(1.5f-xhalf*x*x); */ \
|
||||
invSqrt = vmulq(tmp, xStart); \
|
||||
}
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEI only
|
||||
|
||||
***************************************/
|
||||
#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)
|
||||
|
||||
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
/* Following functions are used to transpose matrix in f32 and q31 cases */
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve(
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
static const uint32x4_t vecOffs = { 0, 2, 1, 3 };
|
||||
/*
|
||||
*
|
||||
* | 0 1 | => | 0 2 |
|
||||
* | 2 3 | | 1 3 |
|
||||
*
|
||||
*/
|
||||
uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc);
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve(
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
|
||||
const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
|
||||
/*
|
||||
*
|
||||
* | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 |
|
||||
* | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 |
|
||||
* | 6 7 8 | | 2 5 8 | (row major) | 8 . . . |
|
||||
*
|
||||
*/
|
||||
uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc);
|
||||
uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]);
|
||||
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1);
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2);
|
||||
|
||||
pDataDest[8] = pDataSrc[8];
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest)
|
||||
{
|
||||
/*
|
||||
* 4x4 Matrix transposition
|
||||
* is 4 x de-interleave operation
|
||||
*
|
||||
* 0 1 2 3 0 4 8 12
|
||||
* 4 5 6 7 1 5 9 13
|
||||
* 8 9 10 11 2 6 10 14
|
||||
* 12 13 14 15 3 7 11 15
|
||||
*/
|
||||
|
||||
uint32x4x4_t vecIn;
|
||||
|
||||
vecIn = vld4q((uint32_t const *) pDataSrc);
|
||||
vstrwq(pDataDest, vecIn.val[0]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[1]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[2]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[3]);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(
|
||||
uint16_t srcRows,
|
||||
uint16_t srcCols,
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
uint32x4_t vecOffs;
|
||||
uint32_t i;
|
||||
uint32_t blkCnt;
|
||||
uint32_t const *pDataC;
|
||||
uint32_t *pDataDestR;
|
||||
uint32x4_t vecIn;
|
||||
|
||||
vecOffs = vidupq_u32((uint32_t)0, 1);
|
||||
vecOffs = vecOffs * srcCols;
|
||||
|
||||
i = srcCols;
|
||||
do
|
||||
{
|
||||
pDataC = (uint32_t const *) pDataSrc;
|
||||
pDataDestR = pDataDest;
|
||||
|
||||
blkCnt = srcRows >> 2;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
|
||||
vstrwq(pDataDestR, vecIn);
|
||||
pDataDestR += 4;
|
||||
pDataC = pDataC + srcCols * 4;
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/*
|
||||
* tail
|
||||
*/
|
||||
blkCnt = srcRows & 3;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp32q(blkCnt);
|
||||
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
|
||||
vstrwq_p(pDataDestR, vecIn, p0);
|
||||
}
|
||||
|
||||
pDataSrc += 1;
|
||||
pDataDest += srcRows;
|
||||
}
|
||||
while (--i);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
|
||||
__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn)
|
||||
{
|
||||
q63x2_t vecTmpLL;
|
||||
q31x4_t vecTmp0, vecTmp1;
|
||||
q31_t scale;
|
||||
q63_t tmp64;
|
||||
q31x4_t vecNrm, vecDst, vecIdx, vecSignBits;
|
||||
|
||||
|
||||
vecSignBits = vclsq(vecIn);
|
||||
vecSignBits = vbicq(vecSignBits, 1);
|
||||
/*
|
||||
* in = in << no_of_sign_bits;
|
||||
*/
|
||||
vecNrm = vshlq(vecIn, vecSignBits);
|
||||
/*
|
||||
* index = in >> 24;
|
||||
*/
|
||||
vecIdx = vecNrm >> 24;
|
||||
vecIdx = vecIdx << 1;
|
||||
|
||||
vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx);
|
||||
|
||||
vecIdx = vecIdx + 1;
|
||||
|
||||
vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx);
|
||||
|
||||
vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
|
||||
vecTmp0 = vecTmp0 - vecTmp1;
|
||||
vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
|
||||
vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
|
||||
vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1;
|
||||
vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
|
||||
vecTmpLL = vmullbq_int(vecNrm, vecTmp0);
|
||||
|
||||
/*
|
||||
* scale elements 0, 2
|
||||
*/
|
||||
scale = 26 + (vecSignBits[0] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[0], scale);
|
||||
vecDst[0] = (q31_t) tmp64;
|
||||
|
||||
scale = 26 + (vecSignBits[2] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[1], scale);
|
||||
vecDst[2] = (q31_t) tmp64;
|
||||
|
||||
vecTmpLL = vmulltq_int(vecNrm, vecTmp0);
|
||||
|
||||
/*
|
||||
* scale elements 1, 3
|
||||
*/
|
||||
scale = 26 + (vecSignBits[1] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[0], scale);
|
||||
vecDst[1] = (q31_t) tmp64;
|
||||
|
||||
scale = 26 + (vecSignBits[3] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[1], scale);
|
||||
vecDst[3] = (q31_t) tmp64;
|
||||
/*
|
||||
* set negative values to 0
|
||||
*/
|
||||
vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0));
|
||||
|
||||
return vecDst;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
|
||||
__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn)
|
||||
{
|
||||
q31x4_t vecTmpLev, vecTmpLodd, vecSignL;
|
||||
q15x8_t vecTmp0, vecTmp1;
|
||||
q15x8_t vecNrm, vecDst, vecIdx, vecSignBits;
|
||||
|
||||
vecDst = vuninitializedq_s16();
|
||||
|
||||
vecSignBits = vclsq(vecIn);
|
||||
vecSignBits = vbicq(vecSignBits, 1);
|
||||
/*
|
||||
* in = in << no_of_sign_bits;
|
||||
*/
|
||||
vecNrm = vshlq(vecIn, vecSignBits);
|
||||
|
||||
vecIdx = vecNrm >> 8;
|
||||
vecIdx = vecIdx << 1;
|
||||
|
||||
vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx);
|
||||
|
||||
vecIdx = vecIdx + 1;
|
||||
|
||||
vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx);
|
||||
|
||||
vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
|
||||
vecTmp0 = vecTmp0 - vecTmp1;
|
||||
vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
|
||||
vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
|
||||
vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1;
|
||||
vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
|
||||
|
||||
vecSignBits = vecSignBits >> 1;
|
||||
|
||||
vecTmpLev = vmullbq_int(vecNrm, vecTmp0);
|
||||
vecTmpLodd = vmulltq_int(vecNrm, vecTmp0);
|
||||
|
||||
vecTmp0 = vecSignBits + 10;
|
||||
/*
|
||||
* negate sign to apply register based vshl
|
||||
*/
|
||||
vecTmp0 = -vecTmp0;
|
||||
|
||||
/*
|
||||
* shift even elements
|
||||
*/
|
||||
vecSignL = vmovlbq(vecTmp0);
|
||||
vecTmpLev = vshlq(vecTmpLev, vecSignL);
|
||||
/*
|
||||
* shift odd elements
|
||||
*/
|
||||
vecSignL = vmovltq(vecTmp0);
|
||||
vecTmpLodd = vshlq(vecTmpLodd, vecSignL);
|
||||
/*
|
||||
* merge and narrow odd and even parts
|
||||
*/
|
||||
vecDst = vmovnbq_s32(vecDst, vecTmpLev);
|
||||
vecDst = vmovntq_s32(vecDst, vecTmpLodd);
|
||||
/*
|
||||
* set negative values to 0
|
||||
*/
|
||||
vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0));
|
||||
|
||||
return vecDst;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */
|
||||
|
||||
#endif
|
||||
8970
libraries/cmsis/cm4/core_support/arm_math.h
Normal file
8970
libraries/cmsis/cm4/core_support/arm_math.h
Normal file
File diff suppressed because it is too large
Load Diff
235
libraries/cmsis/cm4/core_support/arm_mve_tables.h
Normal file
235
libraries/cmsis/cm4/core_support/arm_mve_tables.h
Normal file
@@ -0,0 +1,235 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_mve_tables.h
|
||||
* Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
|
||||
* used for MVE implementation only
|
||||
*
|
||||
* $Date: 08. January 2020
|
||||
* $Revision: V1.7.0
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MVE_TABLES_H
|
||||
#define _ARM_MVE_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2];
|
||||
extern float32_t rearranged_twiddle_stride1_16_f32[8];
|
||||
extern float32_t rearranged_twiddle_stride2_16_f32[8];
|
||||
extern float32_t rearranged_twiddle_stride3_16_f32[8];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3];
|
||||
extern float32_t rearranged_twiddle_stride1_64_f32[40];
|
||||
extern float32_t rearranged_twiddle_stride2_64_f32[40];
|
||||
extern float32_t rearranged_twiddle_stride3_64_f32[40];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4];
|
||||
extern float32_t rearranged_twiddle_stride1_256_f32[168];
|
||||
extern float32_t rearranged_twiddle_stride2_256_f32[168];
|
||||
extern float32_t rearranged_twiddle_stride3_256_f32[168];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5];
|
||||
extern float32_t rearranged_twiddle_stride1_1024_f32[680];
|
||||
extern float32_t rearranged_twiddle_stride2_1024_f32[680];
|
||||
extern float32_t rearranged_twiddle_stride3_1024_f32[680];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6];
|
||||
extern float32_t rearranged_twiddle_stride1_4096_f32[2728];
|
||||
extern float32_t rearranged_twiddle_stride2_4096_f32[2728];
|
||||
extern float32_t rearranged_twiddle_stride3_4096_f32[2728];
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEI)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2];
|
||||
extern q31_t rearranged_twiddle_stride1_16_q31[8];
|
||||
extern q31_t rearranged_twiddle_stride2_16_q31[8];
|
||||
extern q31_t rearranged_twiddle_stride3_16_q31[8];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3];
|
||||
extern q31_t rearranged_twiddle_stride1_64_q31[40];
|
||||
extern q31_t rearranged_twiddle_stride2_64_q31[40];
|
||||
extern q31_t rearranged_twiddle_stride3_64_q31[40];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4];
|
||||
extern q31_t rearranged_twiddle_stride1_256_q31[168];
|
||||
extern q31_t rearranged_twiddle_stride2_256_q31[168];
|
||||
extern q31_t rearranged_twiddle_stride3_256_q31[168];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5];
|
||||
extern q31_t rearranged_twiddle_stride1_1024_q31[680];
|
||||
extern q31_t rearranged_twiddle_stride2_1024_q31[680];
|
||||
extern q31_t rearranged_twiddle_stride3_1024_q31[680];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6];
|
||||
extern q31_t rearranged_twiddle_stride1_4096_q31[2728];
|
||||
extern q31_t rearranged_twiddle_stride2_4096_q31[2728];
|
||||
extern q31_t rearranged_twiddle_stride3_4096_q31[2728];
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEI) */
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEI)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2];
|
||||
extern q15_t rearranged_twiddle_stride1_16_q15[8];
|
||||
extern q15_t rearranged_twiddle_stride2_16_q15[8];
|
||||
extern q15_t rearranged_twiddle_stride3_16_q15[8];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3];
|
||||
extern q15_t rearranged_twiddle_stride1_64_q15[40];
|
||||
extern q15_t rearranged_twiddle_stride2_64_q15[40];
|
||||
extern q15_t rearranged_twiddle_stride3_64_q15[40];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4];
|
||||
extern q15_t rearranged_twiddle_stride1_256_q15[168];
|
||||
extern q15_t rearranged_twiddle_stride2_256_q15[168];
|
||||
extern q15_t rearranged_twiddle_stride3_256_q15[168];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5];
|
||||
extern q15_t rearranged_twiddle_stride1_1024_q15[680];
|
||||
extern q15_t rearranged_twiddle_stride2_1024_q15[680];
|
||||
extern q15_t rearranged_twiddle_stride3_1024_q15[680];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6];
|
||||
extern q15_t rearranged_twiddle_stride1_4096_q15[2728];
|
||||
extern q15_t rearranged_twiddle_stride2_4096_q15[2728];
|
||||
extern q15_t rearranged_twiddle_stride3_4096_q15[2728];
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEI) */
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEI)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEI) */
|
||||
|
||||
|
||||
|
||||
#endif /*_ARM_MVE_TABLES_H*/
|
||||
|
||||
372
libraries/cmsis/cm4/core_support/arm_vec_math.h
Normal file
372
libraries/cmsis/cm4/core_support/arm_vec_math.h
Normal file
@@ -0,0 +1,372 @@
|
||||
/******************************************************************************
|
||||
* @file arm_vec_math.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.7.0
|
||||
* @date 15. October 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_VEC_MATH_H
|
||||
#define _ARM_VEC_MATH_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#define INV_NEWTON_INIT_F32 0x7EF127EA
|
||||
|
||||
static const float32_t __logf_rng_f32=0.693147180f;
|
||||
|
||||
|
||||
/* fast inverse approximation (3x newton) */
|
||||
__STATIC_INLINE f32x4_t vrecip_medprec_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
q31x4_t m;
|
||||
f32x4_t b;
|
||||
any32x4_t xinv;
|
||||
f32x4_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
m = 0x3F800000 - (xinv.i & 0x7F800000);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f - 0.47058824f * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
/* fast inverse approximation (4x newton) */
|
||||
__STATIC_INLINE f32x4_t vrecip_hiprec_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
q31x4_t m;
|
||||
f32x4_t b;
|
||||
any32x4_t xinv;
|
||||
f32x4_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
|
||||
m = 0x3F800000 - (xinv.i & 0x7F800000);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f - 0.47058824f * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vdiv_f32(
|
||||
f32x4_t num, f32x4_t den)
|
||||
{
|
||||
return vmulq(num, vrecip_hiprec_f32(den));
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Single-precision taylor dev.
|
||||
@param[in] x f32 quad vector input
|
||||
@param[in] coeffs f32 quad vector coeffs
|
||||
@return destination f32 quad vector
|
||||
*/
|
||||
|
||||
__STATIC_INLINE f32x4_t vtaylor_polyq_f32(
|
||||
f32x4_t x,
|
||||
const float32_t * coeffs)
|
||||
{
|
||||
f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]);
|
||||
f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]);
|
||||
f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]);
|
||||
f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]);
|
||||
f32x4_t x2 = vmulq(x, x);
|
||||
f32x4_t x4 = vmulq(x2, x2);
|
||||
f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vmant_exp_f32(
|
||||
f32x4_t x,
|
||||
int32x4_t * e)
|
||||
{
|
||||
any32x4_t r;
|
||||
int32x4_t n;
|
||||
|
||||
r.f = x;
|
||||
n = r.i >> 23;
|
||||
n = n - 127;
|
||||
r.i = r.i - (n << 23);
|
||||
|
||||
*e = n;
|
||||
return r.f;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn)
|
||||
{
|
||||
q31x4_t vecExpUnBiased;
|
||||
f32x4_t vecTmpFlt0, vecTmpFlt1;
|
||||
f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3;
|
||||
f32x4_t vecExpUnBiasedFlt;
|
||||
|
||||
/*
|
||||
* extract exponent
|
||||
*/
|
||||
vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased);
|
||||
|
||||
vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1;
|
||||
/*
|
||||
* a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]);
|
||||
*/
|
||||
vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]);
|
||||
vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]);
|
||||
/*
|
||||
* b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]);
|
||||
*/
|
||||
vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]);
|
||||
vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]);
|
||||
/*
|
||||
* c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]);
|
||||
*/
|
||||
vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]);
|
||||
vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]);
|
||||
/*
|
||||
* d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]);
|
||||
*/
|
||||
vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]);
|
||||
vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]);
|
||||
/*
|
||||
* a = a + b * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0);
|
||||
/*
|
||||
* c = c + d * xx;
|
||||
*/
|
||||
vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0);
|
||||
/*
|
||||
* xx = xx * xx;
|
||||
*/
|
||||
vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0;
|
||||
vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased);
|
||||
/*
|
||||
* r.f = a + c * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0);
|
||||
/*
|
||||
* add exponent
|
||||
* r.f = r.f + ((float32_t) m) * __logf_rng_f32;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32);
|
||||
// set log0 down to -inf
|
||||
vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f));
|
||||
return vecAcc0;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vexpq_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
// Perform range reduction [-log(2),log(2)]
|
||||
int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f));
|
||||
f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f));
|
||||
|
||||
// Polynomial Approximation
|
||||
f32x4_t poly = vtaylor_polyq_f32(val, exp_tab);
|
||||
|
||||
// Reconstruct
|
||||
poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23)));
|
||||
|
||||
poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126));
|
||||
return poly;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb)
|
||||
{
|
||||
f32x4_t r = x;
|
||||
nb--;
|
||||
while (nb > 0) {
|
||||
r = vmulq(r, x);
|
||||
nb--;
|
||||
}
|
||||
return (r);
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn)
|
||||
{
|
||||
f32x4_t vecSx, vecW, vecTmp;
|
||||
any32x4_t v;
|
||||
|
||||
vecSx = vabsq(vecIn);
|
||||
|
||||
v.f = vecIn;
|
||||
v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i);
|
||||
|
||||
vecW = vmulq(vecSx, v.f);
|
||||
|
||||
// v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w)))))));
|
||||
vecTmp = vsubq(vdupq_n_f32(8.0f), vecW);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -28.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 56.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -70.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 56.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -28.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 8.0f);
|
||||
v.f = vmulq(v.f, vecTmp);
|
||||
|
||||
v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f));
|
||||
return v.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vtanhq_f32(
|
||||
f32x4_t val)
|
||||
{
|
||||
f32x4_t x =
|
||||
vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f));
|
||||
f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f));
|
||||
f32x4_t num = vsubq_n_f32(exp2x, 1.f);
|
||||
f32x4_t den = vaddq_n_f32(exp2x, 1.f);
|
||||
f32x4_t tanh = vmulq_f32(num, vrecip_f32(den));
|
||||
return tanh;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vpowq_f32(
|
||||
f32x4_t val,
|
||||
f32x4_t n)
|
||||
{
|
||||
return vexpq_f32(vmulq_f32(n, vlogq_f32(val)));
|
||||
}
|
||||
|
||||
#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/
|
||||
|
||||
#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM))
|
||||
#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
|
||||
|
||||
#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "NEMath.h"
|
||||
/**
|
||||
* @brief Vectorized integer exponentiation
|
||||
* @param[in] x value
|
||||
* @param[in] nb integer exponent >= 1
|
||||
* @return x^nb
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb)
|
||||
{
|
||||
float32x4_t r = x;
|
||||
nb --;
|
||||
while(nb > 0)
|
||||
{
|
||||
r = vmulq_f32(r , x);
|
||||
nb--;
|
||||
}
|
||||
return(r);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x)
|
||||
{
|
||||
float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN));
|
||||
float32x4_t e = vrsqrteq_f32(x1);
|
||||
e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
|
||||
e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
|
||||
return vmulq_f32(x, e);
|
||||
}
|
||||
|
||||
__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec)
|
||||
{
|
||||
float32x4_t tempF;
|
||||
int32x4_t tempHI,tempLO;
|
||||
|
||||
tempLO = vmovl_s16(vget_low_s16(vec));
|
||||
tempF = vcvtq_n_f32_s32(tempLO,15);
|
||||
tempF = __arm_vec_sqrt_f32_neon(tempF);
|
||||
tempLO = vcvtq_n_s32_f32(tempF,15);
|
||||
|
||||
tempHI = vmovl_s16(vget_high_s16(vec));
|
||||
tempF = vcvtq_n_f32_s32(tempHI,15);
|
||||
tempF = __arm_vec_sqrt_f32_neon(tempF);
|
||||
tempHI = vcvtq_n_s32_f32(tempF,15);
|
||||
|
||||
return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI)));
|
||||
}
|
||||
|
||||
__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec)
|
||||
{
|
||||
float32x4_t temp;
|
||||
|
||||
temp = vcvtq_n_f32_s32(vec,31);
|
||||
temp = __arm_vec_sqrt_f32_neon(temp);
|
||||
return(vcvtq_n_s32_f32(temp,31));
|
||||
}
|
||||
|
||||
#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _ARM_VEC_MATH_H */
|
||||
|
||||
/**
|
||||
*
|
||||
* End of file.
|
||||
*/
|
||||
885
libraries/cmsis/cm4/core_support/cmsis_armcc.h
Normal file
885
libraries/cmsis/cm4/core_support/cmsis_armcc.h
Normal file
@@ -0,0 +1,885 @@
|
||||
/******************************************************************************
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||
* @version V5.2.1
|
||||
* @date 26. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
/* __ARM_ARCH_8_1M_MAIN__ not applicable */
|
||||
|
||||
/* CMSIS compiler control DSP macros */
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __ARM_FEATURE_DSP 1
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __memory_changed()
|
||||
#endif
|
||||
|
||||
/* ######################### Startup and Lowlevel Init ######################## */
|
||||
|
||||
#ifndef __PROGRAM_START
|
||||
#define __PROGRAM_START __main
|
||||
#endif
|
||||
|
||||
#ifndef __INITIAL_SP
|
||||
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
|
||||
#endif
|
||||
|
||||
#ifndef __STACK_LIMIT
|
||||
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE
|
||||
#define __VECTOR_TABLE __Vectors
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
|
||||
#endif
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
1467
libraries/cmsis/cm4/core_support/cmsis_armclang.h
Normal file
1467
libraries/cmsis/cm4/core_support/cmsis_armclang.h
Normal file
File diff suppressed because it is too large
Load Diff
1893
libraries/cmsis/cm4/core_support/cmsis_armclang_ltm.h
Normal file
1893
libraries/cmsis/cm4/core_support/cmsis_armclang_ltm.h
Normal file
File diff suppressed because it is too large
Load Diff
283
libraries/cmsis/cm4/core_support/cmsis_compiler.h
Normal file
283
libraries/cmsis/cm4/core_support/cmsis_compiler.h
Normal file
@@ -0,0 +1,283 @@
|
||||
/******************************************************************************
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
2177
libraries/cmsis/cm4/core_support/cmsis_gcc.h
Normal file
2177
libraries/cmsis/cm4/core_support/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load Diff
968
libraries/cmsis/cm4/core_support/cmsis_iccarm.h
Normal file
968
libraries/cmsis/cm4/core_support/cmsis_iccarm.h
Normal file
@@ -0,0 +1,968 @@
|
||||
/******************************************************************************
|
||||
* @file cmsis_iccarm.h
|
||||
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||
* @version V5.2.0
|
||||
* @date 28. January 2020
|
||||
******************************************************************************/
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2017-2019 IAR Systems
|
||||
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
#ifndef __CMSIS_ICCARM_H__
|
||||
#define __CMSIS_ICCARM_H__
|
||||
|
||||
#ifndef __ICCARM__
|
||||
#error This file should only be compiled by ICCARM
|
||||
#endif
|
||||
|
||||
#pragma system_include
|
||||
|
||||
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||
|
||||
#if (__VER__ >= 8000000)
|
||||
#define __ICCARM_V8 1
|
||||
#else
|
||||
#define __ICCARM_V8 0
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGNED
|
||||
#if __ICCARM_V8
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#elif (__VER__ >= 7080000)
|
||||
/* Needs IAR language extensions */
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#else
|
||||
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||
*/
|
||||
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||
/* Macros already defined */
|
||||
#else
|
||||
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
|
||||
#if __ARM_ARCH == 6
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif __ARM_ARCH == 7
|
||||
#if __ARM_FEATURE_DSP
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#else
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
#endif /* __ARM_ARCH */
|
||||
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||
#endif
|
||||
|
||||
/* Alternativ core deduction for older ICCARM's */
|
||||
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
|
||||
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
|
||||
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#else
|
||||
#error "Unknown target."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#else
|
||||
#define __IAR_M0_FAMILY 0
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#if __ICCARM_V8
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#else
|
||||
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_STRUCT
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_UNION
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __RESTRICT
|
||||
#if __ICCARM_V8
|
||||
#define __RESTRICT __restrict
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __RESTRICT restrict
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
|
||||
#ifndef __FORCEINLINE
|
||||
#define __FORCEINLINE _Pragma("inline=forced")
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint16_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||
{
|
||||
*(__packed uint16_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint32_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||
{
|
||||
*(__packed uint32_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__packed struct __iar_u32 { uint32_t v; };
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
|
||||
#endif
|
||||
|
||||
#ifndef __USED
|
||||
#if __ICCARM_V8
|
||||
#define __USED __attribute__((used))
|
||||
#else
|
||||
#define __USED _Pragma("__root")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#if __ICCARM_V8
|
||||
#define __WEAK __attribute__((weak))
|
||||
#else
|
||||
#define __WEAK _Pragma("__weak")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PROGRAM_START
|
||||
#define __PROGRAM_START __iar_program_start
|
||||
#endif
|
||||
|
||||
#ifndef __INITIAL_SP
|
||||
#define __INITIAL_SP CSTACK$$Limit
|
||||
#endif
|
||||
|
||||
#ifndef __STACK_LIMIT
|
||||
#define __STACK_LIMIT CSTACK$$Base
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE
|
||||
#define __VECTOR_TABLE __vector_table
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
|
||||
#endif
|
||||
|
||||
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||
#endif
|
||||
|
||||
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||
|
||||
#if defined(__CLZ)
|
||||
#undef __CLZ
|
||||
#endif
|
||||
#if defined(__REVSH)
|
||||
#undef __REVSH
|
||||
#endif
|
||||
#if defined(__RBIT)
|
||||
#undef __RBIT
|
||||
#endif
|
||||
#if defined(__SSAT)
|
||||
#undef __SSAT
|
||||
#endif
|
||||
#if defined(__USAT)
|
||||
#undef __USAT
|
||||
#endif
|
||||
|
||||
#include "iccarm_builtin.h"
|
||||
|
||||
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||
#define __disable_irq __iar_builtin_disable_interrupt
|
||||
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||
#define __enable_irq __iar_builtin_enable_interrupt
|
||||
#define __arm_rsr __iar_builtin_rsr
|
||||
#define __arm_wsr __iar_builtin_wsr
|
||||
|
||||
|
||||
#define __get_APSR() (__arm_rsr("APSR"))
|
||||
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||
#else
|
||||
#define __get_FPSCR() ( 0 )
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||
#define __get_MSP() (__arm_rsr("MSP"))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __get_MSPLIM() (0U)
|
||||
#else
|
||||
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
|
||||
#endif
|
||||
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
|
||||
#define __get_PSP() (__arm_rsr("PSP"))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __get_PSPLIM() (0U)
|
||||
#else
|
||||
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
|
||||
#endif
|
||||
|
||||
#define __get_xPSR() (__arm_rsr("xPSR"))
|
||||
|
||||
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
|
||||
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
|
||||
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
|
||||
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
|
||||
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
|
||||
#endif
|
||||
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
|
||||
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
|
||||
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
|
||||
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
|
||||
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
|
||||
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
|
||||
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
|
||||
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
|
||||
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
|
||||
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
|
||||
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
|
||||
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
|
||||
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
|
||||
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __TZ_get_PSPLIM_NS() (0U)
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
|
||||
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
|
||||
|
||||
#define __NOP __iar_builtin_no_operation
|
||||
|
||||
#define __CLZ __iar_builtin_CLZ
|
||||
#define __CLREX __iar_builtin_CLREX
|
||||
|
||||
#define __DMB __iar_builtin_DMB
|
||||
#define __DSB __iar_builtin_DSB
|
||||
#define __ISB __iar_builtin_ISB
|
||||
|
||||
#define __LDREXB __iar_builtin_LDREXB
|
||||
#define __LDREXH __iar_builtin_LDREXH
|
||||
#define __LDREXW __iar_builtin_LDREX
|
||||
|
||||
#define __RBIT __iar_builtin_RBIT
|
||||
#define __REV __iar_builtin_REV
|
||||
#define __REV16 __iar_builtin_REV16
|
||||
|
||||
__IAR_FT int16_t __REVSH(int16_t val)
|
||||
{
|
||||
return (int16_t) __iar_builtin_REVSH(val);
|
||||
}
|
||||
|
||||
#define __ROR __iar_builtin_ROR
|
||||
#define __RRX __iar_builtin_RRX
|
||||
|
||||
#define __SEV __iar_builtin_SEV
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __SSAT __iar_builtin_SSAT
|
||||
#endif
|
||||
|
||||
#define __STREXB __iar_builtin_STREXB
|
||||
#define __STREXH __iar_builtin_STREXH
|
||||
#define __STREXW __iar_builtin_STREX
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __USAT __iar_builtin_USAT
|
||||
#endif
|
||||
|
||||
#define __WFE __iar_builtin_WFE
|
||||
#define __WFI __iar_builtin_WFI
|
||||
|
||||
#if __ARM_MEDIA__
|
||||
#define __SADD8 __iar_builtin_SADD8
|
||||
#define __QADD8 __iar_builtin_QADD8
|
||||
#define __SHADD8 __iar_builtin_SHADD8
|
||||
#define __UADD8 __iar_builtin_UADD8
|
||||
#define __UQADD8 __iar_builtin_UQADD8
|
||||
#define __UHADD8 __iar_builtin_UHADD8
|
||||
#define __SSUB8 __iar_builtin_SSUB8
|
||||
#define __QSUB8 __iar_builtin_QSUB8
|
||||
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||
#define __USUB8 __iar_builtin_USUB8
|
||||
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||
#define __SADD16 __iar_builtin_SADD16
|
||||
#define __QADD16 __iar_builtin_QADD16
|
||||
#define __SHADD16 __iar_builtin_SHADD16
|
||||
#define __UADD16 __iar_builtin_UADD16
|
||||
#define __UQADD16 __iar_builtin_UQADD16
|
||||
#define __UHADD16 __iar_builtin_UHADD16
|
||||
#define __SSUB16 __iar_builtin_SSUB16
|
||||
#define __QSUB16 __iar_builtin_QSUB16
|
||||
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||
#define __USUB16 __iar_builtin_USUB16
|
||||
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||
#define __SASX __iar_builtin_SASX
|
||||
#define __QASX __iar_builtin_QASX
|
||||
#define __SHASX __iar_builtin_SHASX
|
||||
#define __UASX __iar_builtin_UASX
|
||||
#define __UQASX __iar_builtin_UQASX
|
||||
#define __UHASX __iar_builtin_UHASX
|
||||
#define __SSAX __iar_builtin_SSAX
|
||||
#define __QSAX __iar_builtin_QSAX
|
||||
#define __SHSAX __iar_builtin_SHSAX
|
||||
#define __USAX __iar_builtin_USAX
|
||||
#define __UQSAX __iar_builtin_UQSAX
|
||||
#define __UHSAX __iar_builtin_UHSAX
|
||||
#define __USAD8 __iar_builtin_USAD8
|
||||
#define __USADA8 __iar_builtin_USADA8
|
||||
#define __SSAT16 __iar_builtin_SSAT16
|
||||
#define __USAT16 __iar_builtin_USAT16
|
||||
#define __UXTB16 __iar_builtin_UXTB16
|
||||
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||
#define __SXTB16 __iar_builtin_SXTB16
|
||||
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||
#define __SMUAD __iar_builtin_SMUAD
|
||||
#define __SMUADX __iar_builtin_SMUADX
|
||||
#define __SMMLA __iar_builtin_SMMLA
|
||||
#define __SMLAD __iar_builtin_SMLAD
|
||||
#define __SMLADX __iar_builtin_SMLADX
|
||||
#define __SMLALD __iar_builtin_SMLALD
|
||||
#define __SMLALDX __iar_builtin_SMLALDX
|
||||
#define __SMUSD __iar_builtin_SMUSD
|
||||
#define __SMUSDX __iar_builtin_SMUSDX
|
||||
#define __SMLSD __iar_builtin_SMLSD
|
||||
#define __SMLSDX __iar_builtin_SMLSDX
|
||||
#define __SMLSLD __iar_builtin_SMLSLD
|
||||
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||
#define __SEL __iar_builtin_SEL
|
||||
#define __QADD __iar_builtin_QADD
|
||||
#define __QSUB __iar_builtin_QSUB
|
||||
#define __PKHBT __iar_builtin_PKHBT
|
||||
#define __PKHTB __iar_builtin_PKHTB
|
||||
#endif
|
||||
|
||||
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#define __CLZ __cmsis_iar_clz_not_active
|
||||
#define __SSAT __cmsis_iar_ssat_not_active
|
||||
#define __USAT __cmsis_iar_usat_not_active
|
||||
#define __RBIT __cmsis_iar_rbit_not_active
|
||||
#define __get_APSR __cmsis_iar_get_APSR_not_active
|
||||
#endif
|
||||
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
|
||||
#endif
|
||||
|
||||
#ifdef __INTRINSICS_INCLUDED
|
||||
#error intrinsics.h is already included previously!
|
||||
#endif
|
||||
|
||||
#include <intrinsics.h>
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#undef __CLZ
|
||||
#undef __SSAT
|
||||
#undef __USAT
|
||||
#undef __RBIT
|
||||
#undef __get_APSR
|
||||
|
||||
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
|
||||
{
|
||||
if (data == 0U) { return 32U; }
|
||||
|
||||
uint32_t count = 0U;
|
||||
uint32_t mask = 0x80000000U;
|
||||
|
||||
while ((data & mask) == 0U)
|
||||
{
|
||||
count += 1U;
|
||||
mask = mask >> 1U;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
|
||||
{
|
||||
uint8_t sc = 31U;
|
||||
uint32_t r = v;
|
||||
for (v >>= 1U; v; v >>= 1U)
|
||||
{
|
||||
r <<= 1U;
|
||||
r |= v & 1U;
|
||||
sc--;
|
||||
}
|
||||
return (r << sc);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm("MRS %0,APSR" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#undef __get_FPSCR
|
||||
#undef __set_FPSCR
|
||||
#define __get_FPSCR() (0)
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
#pragma diag_suppress=Pe177
|
||||
|
||||
#define __enable_irq __enable_interrupt
|
||||
#define __disable_irq __disable_interrupt
|
||||
#define __NOP __no_operation
|
||||
|
||||
#define __get_xPSR __get_PSR
|
||||
|
||||
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
|
||||
|
||||
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||
{
|
||||
return __LDREX((unsigned long *)ptr);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||
{
|
||||
return __STREX(value, (unsigned long *)ptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||
}
|
||||
|
||||
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||
}
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __get_PSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_SP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,SP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR SP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
|
||||
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
|
||||
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#undef __IAR_FT
|
||||
#undef __IAR_M0_FAMILY
|
||||
#undef __ICCARM_V8
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
#pragma diag_default=Pe177
|
||||
|
||||
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
||||
|
||||
#endif /* __CMSIS_ICCARM_H__ */
|
||||
39
libraries/cmsis/cm4/core_support/cmsis_version.h
Normal file
39
libraries/cmsis/cm4/core_support/cmsis_version.h
Normal file
@@ -0,0 +1,39 @@
|
||||
/******************************************************************************
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.4
|
||||
* @date 23. July 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
2129
libraries/cmsis/cm4/core_support/core_cm4.h
Normal file
2129
libraries/cmsis/cm4/core_support/core_cm4.h
Normal file
File diff suppressed because it is too large
Load Diff
275
libraries/cmsis/cm4/core_support/mpu_armv7.h
Normal file
275
libraries/cmsis/cm4/core_support/mpu_armv7.h
Normal file
@@ -0,0 +1,275 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.1.1
|
||||
* @date 10. February 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
352
libraries/cmsis/cm4/core_support/mpu_armv8.h
Normal file
352
libraries/cmsis/cm4/core_support/mpu_armv8.h
Normal file
@@ -0,0 +1,352 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.1.2
|
||||
* @date 10. February 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
(((BASE) & MPU_RBAR_BASE_Msk) | \
|
||||
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
337
libraries/cmsis/cm4/core_support/pmu_armv8.h
Normal file
337
libraries/cmsis/cm4/core_support/pmu_armv8.h
Normal file
@@ -0,0 +1,337 @@
|
||||
/******************************************************************************
|
||||
* @file pmu_armv8.h
|
||||
* @brief CMSIS PMU API for Armv8.1-M PMU
|
||||
* @version V1.0.0
|
||||
* @date 24. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_PMU_ARMV8_H
|
||||
#define ARM_PMU_ARMV8_H
|
||||
|
||||
/**
|
||||
* \brief PMU Events
|
||||
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
|
||||
* */
|
||||
|
||||
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
|
||||
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
|
||||
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
|
||||
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
|
||||
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
|
||||
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
|
||||
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
|
||||
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
|
||||
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
|
||||
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
|
||||
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
|
||||
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
|
||||
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
|
||||
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
|
||||
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
|
||||
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
|
||||
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
|
||||
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
|
||||
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
|
||||
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
|
||||
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
|
||||
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
|
||||
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
|
||||
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
|
||||
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
|
||||
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
|
||||
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
|
||||
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
|
||||
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
|
||||
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
|
||||
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
|
||||
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
|
||||
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
|
||||
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
|
||||
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
|
||||
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
|
||||
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
|
||||
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
|
||||
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
|
||||
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
|
||||
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
|
||||
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
|
||||
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
|
||||
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
|
||||
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
|
||||
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
|
||||
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
|
||||
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
|
||||
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
|
||||
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
|
||||
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
|
||||
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
|
||||
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
|
||||
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
|
||||
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
|
||||
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
|
||||
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
|
||||
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
|
||||
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
|
||||
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
|
||||
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
|
||||
|
||||
/** \brief PMU Functions */
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void);
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
|
||||
|
||||
/**
|
||||
\brief Enable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void)
|
||||
{
|
||||
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Set event to count for PMU eventer counter
|
||||
\param [in] num Event counter (0-30) to configure
|
||||
\param [in] type Event to count
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
|
||||
{
|
||||
PMU->EVTYPER[num] = type;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset all event counters
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Enables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Disables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read cycle counter
|
||||
\return Cycle count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
|
||||
{
|
||||
return PMU->CCNTR;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read event counter
|
||||
\param [in] num Event counter (0-30) to read
|
||||
\return Event count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
|
||||
{
|
||||
return PMU->EVCNTR[num];
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read counter overflow status
|
||||
\return Counter overflow status bits for the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
|
||||
{
|
||||
return PMU->OVSSET;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Clear counter overflow status
|
||||
\param [in] mask Counter overflow status bits to clear
|
||||
\note Clears overflow status bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
|
||||
{
|
||||
PMU->OVSCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to set
|
||||
\note Sets overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to clear
|
||||
\note Clears overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Software increment event counter
|
||||
\param [in] mask Counters to increment
|
||||
\note Software increment bits for one or more event counters (0-30)
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
|
||||
{
|
||||
PMU->SWINC = mask;
|
||||
}
|
||||
|
||||
#endif
|
||||
419
libraries/cmsis/cm4/device_support/at32f413.h
Normal file
419
libraries/cmsis/cm4/device_support/at32f413.h
Normal file
@@ -0,0 +1,419 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413.h
|
||||
* @brief at32f413 header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __AT32F413_H
|
||||
#define __AT32F413_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup AT32F413
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* tip: to avoid modifying this file each time you need to switch between these
|
||||
* devices, you can define the device in your toolchain compiler preprocessor.
|
||||
*/
|
||||
|
||||
#if !defined (AT32F413KBU7_4) && !defined (AT32F413KCU7_4) && !defined (AT32F413CBU7) && \
|
||||
!defined (AT32F413CCU7) && !defined (AT32F413C8T7) && !defined (AT32F413CBT7) && \
|
||||
!defined (AT32F413CCT7) && !defined (AT32F413RBT7) && !defined (AT32F413RCT7) && \
|
||||
!defined (AT32FEBKC8T7) && !defined (AT32F413TBU7)
|
||||
|
||||
#error "Please select first the target device used in your application (in at32f413.h file)"
|
||||
#endif
|
||||
|
||||
#if defined (AT32F413KBU7_4) || defined (AT32F413KCU7_4) || defined (AT32F413CBU7) || \
|
||||
defined (AT32F413CCU7) || defined (AT32F413C8T7) || defined (AT32F413CBT7) || \
|
||||
defined (AT32F413CCT7) || defined (AT32F413RBT7) || defined (AT32F413RCT7) || \
|
||||
defined (AT32FEBKC8T7) || defined (AT32F413TBU7)
|
||||
|
||||
#define AT32F413xx
|
||||
#endif
|
||||
|
||||
/**
|
||||
* define with package
|
||||
*/
|
||||
#if defined (AT32F413RBT7) || defined (AT32F413RCT7)
|
||||
|
||||
#define AT32F413Rx
|
||||
#endif
|
||||
|
||||
#if defined (AT32F413CBU7) || defined (AT32F413CCU7) || defined (AT32F413C8T7) || \
|
||||
defined (AT32F413CBT7) || defined (AT32F413CCT7)
|
||||
|
||||
#define AT32F413Cx
|
||||
#endif
|
||||
|
||||
#if defined (AT32F413KBU7_4) || defined (AT32F413KCU7_4)
|
||||
|
||||
#define AT32F413Kx
|
||||
#endif
|
||||
|
||||
/**
|
||||
* define with memory density
|
||||
*/
|
||||
#if defined (AT32F413C8T7) || defined (AT32FEBKC8T7)
|
||||
|
||||
#define AT32F413x8
|
||||
#endif
|
||||
|
||||
#if defined (AT32F413KBU7_4) || defined (AT32F413CBU7) || defined (AT32F413CBT7) || \
|
||||
defined (AT32F413RBT7) || defined (AT32F413TBU7)
|
||||
|
||||
#define AT32F413xB
|
||||
#endif
|
||||
|
||||
#if defined (AT32F413KCU7_4) || defined (AT32F413CCU7) || defined (AT32F413CCT7) || \
|
||||
defined (AT32F413RCT7)
|
||||
|
||||
#define AT32F413xC
|
||||
#endif
|
||||
|
||||
#ifndef USE_STDPERIPH_DRIVER
|
||||
/**
|
||||
* @brief comment the line below if you will not use the peripherals drivers.
|
||||
* in this case, these drivers will not be included and the application code will
|
||||
* be based on direct access to peripherals registers
|
||||
*/
|
||||
#ifdef _RTE_
|
||||
#include "RTE_Components.h"
|
||||
#ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
|
||||
#define USE_STDPERIPH_DRIVER
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief at32f413 standard peripheral library version number
|
||||
*/
|
||||
#define __AT32F413_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
|
||||
#define __AT32F413_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */
|
||||
#define __AT32F413_LIBRARY_VERSION_MINOR (0x03) /*!< [15:8] minor version */
|
||||
#define __AT32F413_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __AT32F413_LIBRARY_VERSION ((__AT32F413_LIBRARY_VERSION_MAJOR << 24) | \
|
||||
(__AT32F413_LIBRARY_VERSION_MIDDLE << 16) | \
|
||||
(__AT32F413_LIBRARY_VERSION_MINOR << 8) | \
|
||||
(__AT32F413_LIBRARY_VERSION_RC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Configuration_section_for_CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief configuration of the cortex-m4 processor and core peripherals
|
||||
*/
|
||||
#define __CM4_REV 0x0001U /*!< core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< mpu present */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< at32 uses 4 bits for the priority levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< set to 1 if different systick config is used */
|
||||
#define __FPU_PRESENT 1U /*!< fpu present */
|
||||
|
||||
/**
|
||||
* @brief at32f413 interrupt number definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** cortex-m4 processor exceptions numbers ***************************************************/
|
||||
Reset_IRQn = -15, /*!< 1 reset vector, invoked on power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 hard fault, all classes of fault */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 cortex-m4 memory management interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 cortex-m4 bus fault interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 cortex-m4 usage fault interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 cortex-m4 sv call interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 cortex-m4 debug monitor interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 cortex-m4 pend sv interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 cortex-m4 system tick interrupt */
|
||||
|
||||
/****** at32 specific interrupt numbers *********************************************************/
|
||||
WWDT_IRQn = 0, /*!< window watchdog timer interrupt */
|
||||
PVM_IRQn = 1, /*!< pvm through exint line detection interrupt */
|
||||
TAMPER_IRQn = 2, /*!< tamper interrupt */
|
||||
RTC_IRQn = 3, /*!< rtc global interrupt */
|
||||
FLASH_IRQn = 4, /*!< flash global interrupt */
|
||||
CRM_IRQn = 5, /*!< crm global interrupt */
|
||||
EXINT0_IRQn = 6, /*!< external line0 interrupt */
|
||||
EXINT1_IRQn = 7, /*!< external line1 interrupt */
|
||||
EXINT2_IRQn = 8, /*!< external line2 interrupt */
|
||||
EXINT3_IRQn = 9, /*!< external line3 interrupt */
|
||||
EXINT4_IRQn = 10, /*!< external line4 interrupt */
|
||||
DMA1_Channel1_IRQn = 11, /*!< dma1 channel 1 global interrupt */
|
||||
DMA1_Channel2_IRQn = 12, /*!< dma1 channel 2 global interrupt */
|
||||
DMA1_Channel3_IRQn = 13, /*!< dma1 channel 3 global interrupt */
|
||||
DMA1_Channel4_IRQn = 14, /*!< dma1 channel 4 global interrupt */
|
||||
DMA1_Channel5_IRQn = 15, /*!< dma1 channel 5 global interrupt */
|
||||
DMA1_Channel6_IRQn = 16, /*!< dma1 channel 6 global interrupt */
|
||||
DMA1_Channel7_IRQn = 17, /*!< dma1 channel 7 global interrupt */
|
||||
|
||||
ADC1_2_IRQn = 18, /*!< adc1 and adc2 global interrupt */
|
||||
USBFS_H_CAN1_TX_IRQn = 19, /*!< usb device high priority or can1 tx interrupts */
|
||||
USBFS_L_CAN1_RX0_IRQn = 20, /*!< usb device low priority or can1 rx0 interrupts */
|
||||
CAN1_RX1_IRQn = 21, /*!< can1 rx1 interrupt */
|
||||
CAN1_SE_IRQn = 22, /*!< can1 se interrupt */
|
||||
EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */
|
||||
TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake interrupt */
|
||||
TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow interrupt */
|
||||
TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall interrupt */
|
||||
TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */
|
||||
TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */
|
||||
TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */
|
||||
TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */
|
||||
I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */
|
||||
I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
|
||||
I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */
|
||||
I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
|
||||
SPI1_IRQn = 35, /*!< spi1 global interrupt */
|
||||
SPI2_IRQn = 36, /*!< spi2 global interrupt */
|
||||
USART1_IRQn = 37, /*!< usart1 global interrupt */
|
||||
USART2_IRQn = 38, /*!< usart2 global interrupt */
|
||||
USART3_IRQn = 39, /*!< usart3 global interrupt */
|
||||
EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */
|
||||
RTCAlarm_IRQn = 41, /*!< rtc alarm through exint line interrupt */
|
||||
USBFSWakeUp_IRQn = 42, /*!< usb device wakeup from suspend through exint line interrupt */
|
||||
TMR8_BRK_IRQn = 43, /*!< tmr8 brake interrupt */
|
||||
TMR8_OVF_IRQn = 44, /*!< tmr8 overflow interrupt */
|
||||
TMR8_TRG_HALL_IRQn = 45, /*!< tmr8 trigger and hall interrupt */
|
||||
TMR8_CH_IRQn = 46, /*!< tmr8 channel interrupt */
|
||||
SDIO1_IRQn = 49, /*!< sdio1 global interrupt */
|
||||
TMR5_GLOBAL_IRQn = 50, /*!< tmr5 global interrupt */
|
||||
UART4_IRQn = 52, /*!< uart4 global interrupt */
|
||||
UART5_IRQn = 53, /*!< uart5 global interrupt */
|
||||
DMA2_Channel1_IRQn = 56, /*!< dma2 channel 1 global interrupt */
|
||||
DMA2_Channel2_IRQn = 57, /*!< dma2 channel 2 global interrupt */
|
||||
DMA2_Channel3_IRQn = 58, /*!< dma2 channel 3 global interrupt */
|
||||
DMA2_Channel4_5_IRQn = 59, /*!< dma2 channel 4 and channel 5 global interrupt */
|
||||
CAN2_TX_IRQn = 68, /*!< can2 tx interrupt */
|
||||
CAN2_RX0_IRQn = 69, /*!< can2 rx0 interrupt */
|
||||
CAN2_RX1_IRQn = 70, /*!< can2 rx1 interrupt */
|
||||
CAN2_SE_IRQn = 71, /*!< can2 se interrupt */
|
||||
ACC_IRQn = 72, /*!< acc interrupt */
|
||||
USBFS_MAPH_IRQn = 73, /*!< usb map hp interrupt */
|
||||
USBFS_MAPL_IRQn = 74, /*!< usb map lp interrupt */
|
||||
DMA2_Channel6_7_IRQn = 75 /*!< dma2 channel 6 and channel 7 global interrupt */
|
||||
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include "core_cm4.h"
|
||||
#include "system_at32f413.h"
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef int32_t INT32;
|
||||
typedef int16_t INT16;
|
||||
typedef int8_t INT8;
|
||||
typedef uint32_t UINT32;
|
||||
typedef uint16_t UINT16;
|
||||
typedef uint8_t UINT8;
|
||||
|
||||
typedef int32_t s32;
|
||||
typedef int16_t s16;
|
||||
typedef int8_t s8;
|
||||
|
||||
typedef const int32_t sc32; /*!< read only */
|
||||
typedef const int16_t sc16; /*!< read only */
|
||||
typedef const int8_t sc8; /*!< read only */
|
||||
|
||||
typedef __IO int32_t vs32;
|
||||
typedef __IO int16_t vs16;
|
||||
typedef __IO int8_t vs8;
|
||||
|
||||
typedef __I int32_t vsc32; /*!< read only */
|
||||
typedef __I int16_t vsc16; /*!< read only */
|
||||
typedef __I int8_t vsc8; /*!< read only */
|
||||
|
||||
typedef uint32_t u32;
|
||||
typedef uint16_t u16;
|
||||
typedef uint8_t u8;
|
||||
|
||||
typedef const uint32_t uc32; /*!< read only */
|
||||
typedef const uint16_t uc16; /*!< read only */
|
||||
typedef const uint8_t uc8; /*!< read only */
|
||||
|
||||
typedef __IO uint32_t vu32;
|
||||
typedef __IO uint16_t vu16;
|
||||
typedef __IO uint8_t vu8;
|
||||
|
||||
typedef __I uint32_t vuc32; /*!< read only */
|
||||
typedef __I uint16_t vuc16; /*!< read only */
|
||||
typedef __I uint8_t vuc8; /*!< read only */
|
||||
|
||||
/**
|
||||
* @brief flag status
|
||||
*/
|
||||
typedef enum {RESET = 0, SET = !RESET} flag_status;
|
||||
|
||||
/**
|
||||
* @brief confirm state
|
||||
*/
|
||||
typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
|
||||
|
||||
/**
|
||||
* @brief error status
|
||||
*/
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define REG8(addr) *(volatile uint8_t *)(addr)
|
||||
#define REG16(addr) *(volatile uint16_t *)(addr)
|
||||
#define REG32(addr) *(volatile uint32_t *)(addr)
|
||||
|
||||
#define MAKE_VALUE(reg_offset, bit_num) (uint32_t)(((reg_offset) << 16) | (bit_num & 0x1F))
|
||||
|
||||
#define PERIPH_REG(periph_base, value) REG32((periph_base + (value >> 16)))
|
||||
#define PERIPH_REG_BIT(value) (0x1U << (value & 0x1F))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_BASE ((uint32_t)0x08000000)
|
||||
#define SPIM_FLASH_BASE ((uint32_t)0x08400000)
|
||||
#define USD_BASE ((uint32_t)0x1FFFF800)
|
||||
#define SRAM_BASE ((uint32_t)0x20000000)
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000)
|
||||
#define XMC_REG_BASE ((uint32_t)0xA0000000)
|
||||
#define DEBUG_BASE ((uint32_t)0xE0042000)
|
||||
|
||||
#define APB1PERIPH_BASE (PERIPH_BASE + 0x00000)
|
||||
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
|
||||
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
|
||||
|
||||
/* apb1 bus base address */
|
||||
#define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
|
||||
#define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
|
||||
#define TMR4_BASE (APB1PERIPH_BASE + 0x0800)
|
||||
#define TMR5_BASE (APB1PERIPH_BASE + 0x0C00)
|
||||
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
|
||||
#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
|
||||
#define WDT_BASE (APB1PERIPH_BASE + 0x3000)
|
||||
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
|
||||
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
|
||||
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
|
||||
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
|
||||
#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
|
||||
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
|
||||
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
|
||||
#define USBFS_BASE (APB1PERIPH_BASE + 0x5C00)
|
||||
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
|
||||
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
|
||||
#define BPR_BASE (APB1PERIPH_BASE + 0x6C00)
|
||||
#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
|
||||
/* apb2 bus base address */
|
||||
#define IOMUX_BASE (APB2PERIPH_BASE + 0x0000)
|
||||
#define EXINT_BASE (APB2PERIPH_BASE + 0x0400)
|
||||
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
|
||||
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
|
||||
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
|
||||
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
|
||||
#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
|
||||
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
|
||||
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
|
||||
#define TMR1_BASE (APB2PERIPH_BASE + 0x2C00)
|
||||
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
|
||||
#define TMR8_BASE (APB2PERIPH_BASE + 0x3400)
|
||||
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
|
||||
#define TMR9_BASE (APB2PERIPH_BASE + 0x4C00)
|
||||
#define TMR10_BASE (APB2PERIPH_BASE + 0x5000)
|
||||
#define TMR11_BASE (APB2PERIPH_BASE + 0x5400)
|
||||
#define ACC_BASE (APB2PERIPH_BASE + 0x5800)
|
||||
#define SDIO1_BASE (APB2PERIPH_BASE + 0x8000)
|
||||
/* ahb bus base address */
|
||||
#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
|
||||
#define DMA1_CHANNEL1_BASE (AHBPERIPH_BASE + 0x0008)
|
||||
#define DMA1_CHANNEL2_BASE (AHBPERIPH_BASE + 0x001C)
|
||||
#define DMA1_CHANNEL3_BASE (AHBPERIPH_BASE + 0x0030)
|
||||
#define DMA1_CHANNEL4_BASE (AHBPERIPH_BASE + 0x0044)
|
||||
#define DMA1_CHANNEL5_BASE (AHBPERIPH_BASE + 0x0058)
|
||||
#define DMA1_CHANNEL6_BASE (AHBPERIPH_BASE + 0x006C)
|
||||
#define DMA1_CHANNEL7_BASE (AHBPERIPH_BASE + 0x0080)
|
||||
#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
|
||||
#define DMA2_CHANNEL1_BASE (AHBPERIPH_BASE + 0x0408)
|
||||
#define DMA2_CHANNEL2_BASE (AHBPERIPH_BASE + 0x041C)
|
||||
#define DMA2_CHANNEL3_BASE (AHBPERIPH_BASE + 0x0430)
|
||||
#define DMA2_CHANNEL4_BASE (AHBPERIPH_BASE + 0x0444)
|
||||
#define DMA2_CHANNEL5_BASE (AHBPERIPH_BASE + 0x0458)
|
||||
#define DMA2_CHANNEL6_BASE (AHBPERIPH_BASE + 0x046C)
|
||||
#define DMA2_CHANNEL7_BASE (AHBPERIPH_BASE + 0x0480)
|
||||
#define CRM_BASE (AHBPERIPH_BASE + 0x1000)
|
||||
#define FLASH_REG_BASE (AHBPERIPH_BASE + 0x2000)
|
||||
#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include "at32f413_def.h"
|
||||
#include "at32f413_conf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
150
libraries/cmsis/cm4/device_support/at32f413_conf_template.h
Normal file
150
libraries/cmsis/cm4/device_support/at32f413_conf_template.h
Normal file
@@ -0,0 +1,150 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_conf.h
|
||||
* @brief at32f413 config header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F413_CONF_H
|
||||
#define __AT32F413_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief in the following line adjust the value of high speed external crystal (hext)
|
||||
* used in your application
|
||||
* tip: to avoid modifying this file each time you need to use different hext, you
|
||||
* can define the hext value in your toolchain compiler preprocessor.
|
||||
*/
|
||||
#if !defined HEXT_VALUE
|
||||
#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed external crystal in hz */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief in the following line adjust the high speed external crystal (hext) startup
|
||||
* timeout value
|
||||
*/
|
||||
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
|
||||
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
|
||||
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed external clock in hz */
|
||||
|
||||
/* module define -------------------------------------------------------------*/
|
||||
#define CRM_MODULE_ENABLED
|
||||
#define TMR_MODULE_ENABLED
|
||||
#define RTC_MODULE_ENABLED
|
||||
#define BPR_MODULE_ENABLED
|
||||
#define GPIO_MODULE_ENABLED
|
||||
#define I2C_MODULE_ENABLED
|
||||
#define USART_MODULE_ENABLED
|
||||
#define PWC_MODULE_ENABLED
|
||||
#define CAN_MODULE_ENABLED
|
||||
#define ADC_MODULE_ENABLED
|
||||
#define SPI_MODULE_ENABLED
|
||||
#define DMA_MODULE_ENABLED
|
||||
#define DEBUG_MODULE_ENABLED
|
||||
#define FLASH_MODULE_ENABLED
|
||||
#define CRC_MODULE_ENABLED
|
||||
#define WWDT_MODULE_ENABLED
|
||||
#define WDT_MODULE_ENABLED
|
||||
#define EXINT_MODULE_ENABLED
|
||||
#define SDIO_MODULE_ENABLED
|
||||
#define USB_MODULE_ENABLED
|
||||
#define ACC_MODULE_ENABLED
|
||||
#define MISC_MODULE_ENABLED
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#ifdef CRM_MODULE_ENABLED
|
||||
#include "at32f413_crm.h"
|
||||
#endif
|
||||
#ifdef TMR_MODULE_ENABLED
|
||||
#include "at32f413_tmr.h"
|
||||
#endif
|
||||
#ifdef RTC_MODULE_ENABLED
|
||||
#include "at32f413_rtc.h"
|
||||
#endif
|
||||
#ifdef BPR_MODULE_ENABLED
|
||||
#include "at32f413_bpr.h"
|
||||
#endif
|
||||
#ifdef GPIO_MODULE_ENABLED
|
||||
#include "at32f413_gpio.h"
|
||||
#endif
|
||||
#ifdef I2C_MODULE_ENABLED
|
||||
#include "at32f413_i2c.h"
|
||||
#endif
|
||||
#ifdef USART_MODULE_ENABLED
|
||||
#include "at32f413_usart.h"
|
||||
#endif
|
||||
#ifdef PWC_MODULE_ENABLED
|
||||
#include "at32f413_pwc.h"
|
||||
#endif
|
||||
#ifdef CAN_MODULE_ENABLED
|
||||
#include "at32f413_can.h"
|
||||
#endif
|
||||
#ifdef ADC_MODULE_ENABLED
|
||||
#include "at32f413_adc.h"
|
||||
#endif
|
||||
#ifdef SPI_MODULE_ENABLED
|
||||
#include "at32f413_spi.h"
|
||||
#endif
|
||||
#ifdef DMA_MODULE_ENABLED
|
||||
#include "at32f413_dma.h"
|
||||
#endif
|
||||
#ifdef DEBUG_MODULE_ENABLED
|
||||
#include "at32f413_debug.h"
|
||||
#endif
|
||||
#ifdef FLASH_MODULE_ENABLED
|
||||
#include "at32f413_flash.h"
|
||||
#endif
|
||||
#ifdef CRC_MODULE_ENABLED
|
||||
#include "at32f413_crc.h"
|
||||
#endif
|
||||
#ifdef WWDT_MODULE_ENABLED
|
||||
#include "at32f413_wwdt.h"
|
||||
#endif
|
||||
#ifdef WDT_MODULE_ENABLED
|
||||
#include "at32f413_wdt.h"
|
||||
#endif
|
||||
#ifdef EXINT_MODULE_ENABLED
|
||||
#include "at32f413_exint.h"
|
||||
#endif
|
||||
#ifdef SDIO_MODULE_ENABLED
|
||||
#include "at32f413_sdio.h"
|
||||
#endif
|
||||
#ifdef ACC_MODULE_ENABLED
|
||||
#include "at32f413_acc.h"
|
||||
#endif
|
||||
#ifdef MISC_MODULE_ENABLED
|
||||
#include "at32f413_misc.h"
|
||||
#endif
|
||||
#ifdef USB_MODULE_ENABLED
|
||||
#include "at32f413_usb.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __AT32F413_CONF_H */
|
||||
|
||||
|
||||
@@ -0,0 +1,168 @@
|
||||
/*
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : AT32F413x8_FLASH.ld
|
||||
**
|
||||
** Abstract : Linker script for AT32F413x8 Device with
|
||||
** 64KByte FLASH, 32KByte RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : Artery Tek AT32
|
||||
**
|
||||
** Environment : Arm gcc toolchain
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20008000; /* end of RAM */
|
||||
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
SPIM (rx) : ORIGIN = 0x08400000, LENGTH = 16384K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
_spim_init_base = LOADADDR(.spim);
|
||||
_spim_init_length = SIZEOF(.spim);
|
||||
|
||||
.spim :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_spim_start = .; /* create a global symbol at spim start */
|
||||
*(.spim) /* .spim sections */
|
||||
*(.spim*) /* .spim* sections */
|
||||
. = ALIGN(4);
|
||||
_spim_end = .; /* define a global symbols at end of spim */
|
||||
} >SPIM
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -0,0 +1,168 @@
|
||||
/*
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : AT32F413xB_FLASH.ld
|
||||
**
|
||||
** Abstract : Linker script for AT32F413xB Device with
|
||||
** 128KByte FLASH, 32KByte RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : Artery Tek AT32
|
||||
**
|
||||
** Environment : Arm gcc toolchain
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20008000; /* end of RAM */
|
||||
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
SPIM (rx) : ORIGIN = 0x08400000, LENGTH = 16384K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
_spim_init_base = LOADADDR(.spim);
|
||||
_spim_init_length = SIZEOF(.spim);
|
||||
|
||||
.spim :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_spim_start = .; /* create a global symbol at spim start */
|
||||
*(.spim) /* .spim sections */
|
||||
*(.spim*) /* .spim* sections */
|
||||
. = ALIGN(4);
|
||||
_spim_end = .; /* define a global symbols at end of spim */
|
||||
} >SPIM
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -0,0 +1,168 @@
|
||||
/*
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : AT32F413xC_FLASH.ld
|
||||
**
|
||||
** Abstract : Linker script for AT32F413xC Device with
|
||||
** 256KByte FLASH, 32KByte RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : Artery Tek AT32
|
||||
**
|
||||
** Environment : Arm gcc toolchain
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20008000; /* end of RAM */
|
||||
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
SPIM (rx) : ORIGIN = 0x08400000, LENGTH = 16384K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
_spim_init_base = LOADADDR(.spim);
|
||||
_spim_init_length = SIZEOF(.spim);
|
||||
|
||||
.spim :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_spim_start = .; /* create a global symbol at spim start */
|
||||
*(.spim) /* .spim sections */
|
||||
*(.spim*) /* .spim* sections */
|
||||
. = ALIGN(4);
|
||||
_spim_end = .; /* define a global symbols at end of spim */
|
||||
} >SPIM
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -0,0 +1,431 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_at32f413.s
|
||||
* @brief at32f413xx devices vector table for gcc toolchain.
|
||||
* this module performs:
|
||||
* - set the initial sp
|
||||
* - set the initial pc == reset_handler,
|
||||
* - set the vector table entries with the exceptions isr address
|
||||
* - configure the clock system and the external sram to
|
||||
* be used as data memory (optional, to be enabled by user)
|
||||
* - branches to main in the c library (which eventually
|
||||
* calls main()).
|
||||
* after reset the cortex-m4 processor is in thread mode,
|
||||
* priority is privileged, and the stack is set to main.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.word WWDT_IRQHandler /* Window Watchdog Timer */
|
||||
.word PVM_IRQHandler /* PVM through EXINT Line detect */
|
||||
.word TAMPER_IRQHandler /* Tamper */
|
||||
.word RTC_IRQHandler /* RTC */
|
||||
.word FLASH_IRQHandler /* Flash */
|
||||
.word CRM_IRQHandler /* CRM */
|
||||
.word EXINT0_IRQHandler /* EXINT Line 0 */
|
||||
.word EXINT1_IRQHandler /* EXINT Line 1 */
|
||||
.word EXINT2_IRQHandler /* EXINT Line 2 */
|
||||
.word EXINT3_IRQHandler /* EXINT Line 3 */
|
||||
.word EXINT4_IRQHandler /* EXINT Line 4 */
|
||||
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||
.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||
.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||
.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||
.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||
.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||
.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||
.word ADC1_2_IRQHandler /* ADC1 & ADC2 */
|
||||
.word USBFS_H_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */
|
||||
.word USBFS_L_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.word CAN1_SE_IRQHandler /* CAN1 SE */
|
||||
.word EXINT9_5_IRQHandler /* EXINT Line [9:5] */
|
||||
.word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */
|
||||
.word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */
|
||||
.word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */
|
||||
.word TMR1_CH_IRQHandler /* TMR1 Channel */
|
||||
.word TMR2_GLOBAL_IRQHandler /* TMR2 */
|
||||
.word TMR3_GLOBAL_IRQHandler /* TMR3 */
|
||||
.word TMR4_GLOBAL_IRQHandler /* TMR4 */
|
||||
.word I2C1_EVT_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ERR_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EVT_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ERR_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* Reserved */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXINT15_10_IRQHandler /* EXINT Line [15:10] */
|
||||
.word RTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */
|
||||
.word USBFSWakeUp_IRQHandler /* USB Wakeup from suspend */
|
||||
.word TMR8_BRK_IRQHandler /* TMR8 Brake */
|
||||
.word TMR8_OVF_IRQHandler /* TMR8 Overflow */
|
||||
.word TMR8_TRG_HALL_IRQHandler /* TMR8 Trigger and hall */
|
||||
.word TMR8_CH_IRQHandler /* TMR8 Channel */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word SDIO1_IRQHandler /* SDIO1 */
|
||||
.word TMR5_GLOBAL_IRQHandler /* TMR5 */
|
||||
.word 0 /* Reserved */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */
|
||||
.word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */
|
||||
.word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */
|
||||
.word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 & Channel5 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word CAN2_TX_IRQHandler /* CAN2 TX */
|
||||
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
|
||||
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
|
||||
.word CAN2_SE_IRQHandler /* CAN2 SE */
|
||||
.word ACC_IRQHandler /* ACC */
|
||||
.word USBFS_MAPH_IRQHandler /* USB Map HP */
|
||||
.word USBFS_MAPL_IRQHandler /* USB Map LP */
|
||||
.word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDT_IRQHandler
|
||||
.thumb_set WWDT_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVM_IRQHandler
|
||||
.thumb_set PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_IRQHandler
|
||||
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRM_IRQHandler
|
||||
.thumb_set CRM_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXINT0_IRQHandler
|
||||
.thumb_set EXINT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXINT1_IRQHandler
|
||||
.thumb_set EXINT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXINT2_IRQHandler
|
||||
.thumb_set EXINT2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXINT3_IRQHandler
|
||||
.thumb_set EXINT3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXINT4_IRQHandler
|
||||
.thumb_set EXINT4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_2_IRQHandler
|
||||
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_H_CAN1_TX_IRQHandler
|
||||
.thumb_set USBFS_H_CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_L_CAN1_RX0_IRQHandler
|
||||
.thumb_set USBFS_L_CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SE_IRQHandler
|
||||
.thumb_set CAN1_SE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXINT9_5_IRQHandler
|
||||
.thumb_set EXINT9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR1_BRK_TMR9_IRQHandler
|
||||
.thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR1_OVF_TMR10_IRQHandler
|
||||
.thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR1_TRG_HALL_TMR11_IRQHandler
|
||||
.thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR1_CH_IRQHandler
|
||||
.thumb_set TMR1_CH_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR2_GLOBAL_IRQHandler
|
||||
.thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR3_GLOBAL_IRQHandler
|
||||
.thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR4_GLOBAL_IRQHandler
|
||||
.thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EVT_IRQHandler
|
||||
.thumb_set I2C1_EVT_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ERR_IRQHandler
|
||||
.thumb_set I2C1_ERR_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EVT_IRQHandler
|
||||
.thumb_set I2C2_EVT_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ERR_IRQHandler
|
||||
.thumb_set I2C2_ERR_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXINT15_10_IRQHandler
|
||||
.thumb_set EXINT15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTCAlarm_IRQHandler
|
||||
.thumb_set RTCAlarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFSWakeUp_IRQHandler
|
||||
.thumb_set USBFSWakeUp_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR8_BRK_IRQHandler
|
||||
.thumb_set TMR8_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR8_OVF_IRQHandler
|
||||
.thumb_set TMR8_OVF_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR8_TRG_HALL_IRQHandler
|
||||
.thumb_set TMR8_TRG_HALL_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR8_CH_IRQHandler
|
||||
.thumb_set TMR8_CH_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO1_IRQHandler
|
||||
.thumb_set SDIO1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR5_GLOBAL_IRQHandler
|
||||
.thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_5_IRQHandler
|
||||
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_TX_IRQHandler
|
||||
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX0_IRQHandler
|
||||
.thumb_set CAN2_RX0_IRQHandler ,Default_Handler
|
||||
|
||||
.weak CAN2_RX1_IRQHandler
|
||||
.thumb_set CAN2_RX1_IRQHandler ,Default_Handler
|
||||
|
||||
.weak CAN2_SE_IRQHandler
|
||||
.thumb_set CAN2_SE_IRQHandler,Default_Handler
|
||||
|
||||
.weak ACC_IRQHandler
|
||||
.thumb_set ACC_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_MAPH_IRQHandler
|
||||
.thumb_set USBFS_MAPH_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_MAPL_IRQHandler
|
||||
.thumb_set USBFS_MAPL_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel6_7_IRQHandler
|
||||
.thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
|
||||
@@ -0,0 +1,30 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -0,0 +1,30 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -0,0 +1,30 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -0,0 +1,496 @@
|
||||
;**************************************************************************
|
||||
;* @file startup_at32f413.s
|
||||
;* @brief at32f413 startup file for IAR Systems
|
||||
;**************************************************************************
|
||||
;
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDT_IRQHandler ; Window Watchdog Timer
|
||||
DCD PVM_IRQHandler ; PVM through EXINT Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD CRM_IRQHandler ; CRM
|
||||
DCD EXINT0_IRQHandler ; EXINT Line 0
|
||||
DCD EXINT1_IRQHandler ; EXINT Line 1
|
||||
DCD EXINT2_IRQHandler ; EXINT Line 2
|
||||
DCD EXINT3_IRQHandler ; EXINT Line 3
|
||||
DCD EXINT4_IRQHandler ; EXINT Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||
DCD USBFS_H_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||
DCD USBFS_L_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SE_IRQHandler ; CAN1 SE
|
||||
DCD EXINT9_5_IRQHandler ; EXINT Line [9:5]
|
||||
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Brake and TMR9
|
||||
DCD TMR1_OVF_TMR10_IRQHandler ; TMR1 Overflow and TMR10
|
||||
DCD TMR1_TRG_HALL_TMR11_IRQHandler ; TMR1 Trigger and hall and TMR11
|
||||
DCD TMR1_CH_IRQHandler ; TMR1 Channel
|
||||
DCD TMR2_GLOBAL_IRQHandler ; TMR2
|
||||
DCD TMR3_GLOBAL_IRQHandler ; TMR3
|
||||
DCD TMR4_GLOBAL_IRQHandler ; TMR4
|
||||
DCD I2C1_EVT_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ERR_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EVT_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ERR_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXINT15_10_IRQHandler ; EXINT Line [15:10]
|
||||
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXINT Line
|
||||
DCD USBFSWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||
DCD TMR8_BRK_IRQHandler ; TMR8 Brake
|
||||
DCD TMR8_OVF_IRQHandler ; TMR8 Overflow
|
||||
DCD TMR8_TRG_HALL_IRQHandler ; TMR8 Trigger and hall
|
||||
DCD TMR8_CH_IRQHandler ; TMR8 Channel
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SDIO1_IRQHandler ; SDIO1
|
||||
DCD TMR5_GLOBAL_IRQHandler ; TMR5
|
||||
DCD 0 ; Reserved
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SE_IRQHandler ; CAN2 SE
|
||||
DCD ACC_IRQHandler ; ACC
|
||||
DCD USBFS_MAPH_IRQHandler ; USB Map HP
|
||||
DCD USBFS_MAPL_IRQHandler ; USB Map LP
|
||||
DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WWDT_IRQHandler
|
||||
B WWDT_IRQHandler
|
||||
|
||||
PUBWEAK PVM_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PVM_IRQHandler
|
||||
B PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMPER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TAMPER_IRQHandler
|
||||
B TAMPER_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK CRM_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CRM_IRQHandler
|
||||
B CRM_IRQHandler
|
||||
|
||||
PUBWEAK EXINT0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT0_IRQHandler
|
||||
B EXINT0_IRQHandler
|
||||
|
||||
PUBWEAK EXINT1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT1_IRQHandler
|
||||
B EXINT1_IRQHandler
|
||||
|
||||
PUBWEAK EXINT2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT2_IRQHandler
|
||||
B EXINT2_IRQHandler
|
||||
|
||||
PUBWEAK EXINT3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT3_IRQHandler
|
||||
B EXINT3_IRQHandler
|
||||
|
||||
PUBWEAK EXINT4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT4_IRQHandler
|
||||
B EXINT4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ADC1_2_IRQHandler
|
||||
B ADC1_2_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_H_CAN1_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBFS_H_CAN1_TX_IRQHandler
|
||||
B USBFS_H_CAN1_TX_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_L_CAN1_RX0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBFS_L_CAN1_RX0_IRQHandler
|
||||
B USBFS_L_CAN1_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN1_RX1_IRQHandler
|
||||
B CAN1_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_SE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN1_SE_IRQHandler
|
||||
B CAN1_SE_IRQHandler
|
||||
|
||||
PUBWEAK EXINT9_5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT9_5_IRQHandler
|
||||
B EXINT9_5_IRQHandler
|
||||
|
||||
PUBWEAK TMR1_BRK_TMR9_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR1_BRK_TMR9_IRQHandler
|
||||
B TMR1_BRK_TMR9_IRQHandler
|
||||
|
||||
PUBWEAK TMR1_OVF_TMR10_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR1_OVF_TMR10_IRQHandler
|
||||
B TMR1_OVF_TMR10_IRQHandler
|
||||
|
||||
PUBWEAK TMR1_TRG_HALL_TMR11_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR1_TRG_HALL_TMR11_IRQHandler
|
||||
B TMR1_TRG_HALL_TMR11_IRQHandler
|
||||
|
||||
PUBWEAK TMR1_CH_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR1_CH_IRQHandler
|
||||
B TMR1_CH_IRQHandler
|
||||
|
||||
PUBWEAK TMR2_GLOBAL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR2_GLOBAL_IRQHandler
|
||||
B TMR2_GLOBAL_IRQHandler
|
||||
|
||||
PUBWEAK TMR3_GLOBAL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR3_GLOBAL_IRQHandler
|
||||
B TMR3_GLOBAL_IRQHandler
|
||||
|
||||
PUBWEAK TMR4_GLOBAL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR4_GLOBAL_IRQHandler
|
||||
B TMR4_GLOBAL_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EVT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C1_EVT_IRQHandler
|
||||
B I2C1_EVT_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ERR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C1_ERR_IRQHandler
|
||||
B I2C1_ERR_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EVT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C2_EVT_IRQHandler
|
||||
B I2C2_EVT_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ERR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C2_ERR_IRQHandler
|
||||
B I2C2_ERR_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK USART3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART3_IRQHandler
|
||||
B USART3_IRQHandler
|
||||
|
||||
PUBWEAK EXINT15_10_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT15_10_IRQHandler
|
||||
B EXINT15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTCAlarm_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTCAlarm_IRQHandler
|
||||
B RTCAlarm_IRQHandler
|
||||
|
||||
PUBWEAK USBFSWakeUp_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBFSWakeUp_IRQHandler
|
||||
B USBFSWakeUp_IRQHandler
|
||||
|
||||
PUBWEAK TMR8_BRK_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR8_BRK_IRQHandler
|
||||
B TMR8_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TMR8_OVF_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR8_OVF_IRQHandler
|
||||
B TMR8_OVF_IRQHandler
|
||||
|
||||
PUBWEAK TMR8_TRG_HALL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR8_TRG_HALL_IRQHandler
|
||||
B TMR8_TRG_HALL_IRQHandler
|
||||
|
||||
PUBWEAK TMR8_CH_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR8_CH_IRQHandler
|
||||
B TMR8_CH_IRQHandler
|
||||
|
||||
PUBWEAK SDIO1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SDIO1_IRQHandler
|
||||
B SDIO1_IRQHandler
|
||||
|
||||
PUBWEAK TMR5_GLOBAL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR5_GLOBAL_IRQHandler
|
||||
B TMR5_GLOBAL_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel4_5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel4_5_IRQHandler
|
||||
B DMA2_Channel4_5_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_TX_IRQHandler
|
||||
B CAN2_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_RX0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_RX0_IRQHandler
|
||||
B CAN2_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_RX1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_RX1_IRQHandler
|
||||
B CAN2_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_SE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_SE_IRQHandler
|
||||
B CAN2_SE_IRQHandler
|
||||
|
||||
PUBWEAK ACC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ACC_IRQHandler
|
||||
B ACC_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_MAPH_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBFS_MAPH_IRQHandler
|
||||
B USBFS_MAPH_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_MAPL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBFS_MAPL_IRQHandler
|
||||
B USBFS_MAPL_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel6_7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel6_7_IRQHandler
|
||||
B DMA2_Channel6_7_IRQHandler
|
||||
|
||||
END
|
||||
@@ -0,0 +1,357 @@
|
||||
;**************************************************************************
|
||||
;* @file startup_at32f413.s
|
||||
;* @brief at32f413 startup file for keil
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;**************************************************************************
|
||||
;
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDT_IRQHandler ; Window Watchdog Timer
|
||||
DCD PVM_IRQHandler ; PVM through EXINT Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD CRM_IRQHandler ; CRM
|
||||
DCD EXINT0_IRQHandler ; EXINT Line 0
|
||||
DCD EXINT1_IRQHandler ; EXINT Line 1
|
||||
DCD EXINT2_IRQHandler ; EXINT Line 2
|
||||
DCD EXINT3_IRQHandler ; EXINT Line 3
|
||||
DCD EXINT4_IRQHandler ; EXINT Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||
DCD USBFS_H_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||
DCD USBFS_L_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SE_IRQHandler ; CAN1 SE
|
||||
DCD EXINT9_5_IRQHandler ; EXINT Line [9:5]
|
||||
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Brake and TMR9
|
||||
DCD TMR1_OVF_TMR10_IRQHandler ; TMR1 overflow and TMR10
|
||||
DCD TMR1_TRG_HALL_TMR11_IRQHandler ; TMR1 Trigger and hall and TMR11
|
||||
DCD TMR1_CH_IRQHandler ; TMR1 channel
|
||||
DCD TMR2_GLOBAL_IRQHandler ; TMR2
|
||||
DCD TMR3_GLOBAL_IRQHandler ; TMR3
|
||||
DCD TMR4_GLOBAL_IRQHandler ; TMR4
|
||||
DCD I2C1_EVT_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ERR_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EVT_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ERR_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXINT15_10_IRQHandler ; EXINT Line [15:10]
|
||||
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXINT Line
|
||||
DCD USBFSWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||
DCD TMR8_BRK_IRQHandler ; TMR8 Brake
|
||||
DCD TMR8_OVF_IRQHandler ; TMR8 overflow
|
||||
DCD TMR8_TRG_HALL_IRQHandler ; TMR8 Trigger and hall
|
||||
DCD TMR8_CH_IRQHandler ; TMR8 channel
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SDIO1_IRQHandler ; SDIO1
|
||||
DCD TMR5_GLOBAL_IRQHandler ; TMR5
|
||||
DCD 0 ; Reserved
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SE_IRQHandler ; CAN2 SE
|
||||
DCD ACC_IRQHandler ; ACC
|
||||
DCD USBFS_MAPH_IRQHandler ; USB Map High
|
||||
DCD USBFS_MAPL_IRQHandler ; USB Map Low
|
||||
DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT __main
|
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDT_IRQHandler [WEAK]
|
||||
EXPORT PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT CRM_IRQHandler [WEAK]
|
||||
EXPORT EXINT0_IRQHandler [WEAK]
|
||||
EXPORT EXINT1_IRQHandler [WEAK]
|
||||
EXPORT EXINT2_IRQHandler [WEAK]
|
||||
EXPORT EXINT3_IRQHandler [WEAK]
|
||||
EXPORT EXINT4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT USBFS_H_CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT USBFS_L_CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SE_IRQHandler [WEAK]
|
||||
EXPORT EXINT9_5_IRQHandler [WEAK]
|
||||
EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
|
||||
EXPORT TMR1_OVF_TMR10_IRQHandler [WEAK]
|
||||
EXPORT TMR1_TRG_HALL_TMR11_IRQHandler [WEAK]
|
||||
EXPORT TMR1_CH_IRQHandler [WEAK]
|
||||
EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
|
||||
EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
|
||||
EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EVT_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ERR_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EVT_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ERR_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXINT15_10_IRQHandler [WEAK]
|
||||
EXPORT RTCAlarm_IRQHandler [WEAK]
|
||||
EXPORT USBFSWakeUp_IRQHandler [WEAK]
|
||||
EXPORT TMR8_BRK_IRQHandler [WEAK]
|
||||
EXPORT TMR8_OVF_IRQHandler [WEAK]
|
||||
EXPORT TMR8_TRG_HALL_IRQHandler [WEAK]
|
||||
EXPORT TMR8_CH_IRQHandler [WEAK]
|
||||
EXPORT SDIO1_IRQHandler [WEAK]
|
||||
EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
|
||||
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_SE_IRQHandler [WEAK]
|
||||
EXPORT ACC_IRQHandler [WEAK]
|
||||
EXPORT USBFS_MAPH_IRQHandler [WEAK]
|
||||
EXPORT USBFS_MAPL_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel6_7_IRQHandler [WEAK]
|
||||
|
||||
WWDT_IRQHandler
|
||||
PVM_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
CRM_IRQHandler
|
||||
EXINT0_IRQHandler
|
||||
EXINT1_IRQHandler
|
||||
EXINT2_IRQHandler
|
||||
EXINT3_IRQHandler
|
||||
EXINT4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
USBFS_H_CAN1_TX_IRQHandler
|
||||
USBFS_L_CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SE_IRQHandler
|
||||
EXINT9_5_IRQHandler
|
||||
TMR1_BRK_TMR9_IRQHandler
|
||||
TMR1_OVF_TMR10_IRQHandler
|
||||
TMR1_TRG_HALL_TMR11_IRQHandler
|
||||
TMR1_CH_IRQHandler
|
||||
TMR2_GLOBAL_IRQHandler
|
||||
TMR3_GLOBAL_IRQHandler
|
||||
TMR4_GLOBAL_IRQHandler
|
||||
I2C1_EVT_IRQHandler
|
||||
I2C1_ERR_IRQHandler
|
||||
I2C2_EVT_IRQHandler
|
||||
I2C2_ERR_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXINT15_10_IRQHandler
|
||||
RTCAlarm_IRQHandler
|
||||
USBFSWakeUp_IRQHandler
|
||||
TMR8_BRK_IRQHandler
|
||||
TMR8_OVF_IRQHandler
|
||||
TMR8_TRG_HALL_IRQHandler
|
||||
TMR8_CH_IRQHandler
|
||||
SDIO1_IRQHandler
|
||||
TMR5_GLOBAL_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_5_IRQHandler
|
||||
CAN2_TX_IRQHandler
|
||||
CAN2_RX0_IRQHandler
|
||||
CAN2_RX1_IRQHandler
|
||||
CAN2_SE_IRQHandler
|
||||
ACC_IRQHandler
|
||||
USBFS_MAPH_IRQHandler
|
||||
USBFS_MAPL_IRQHandler
|
||||
DMA2_Channel6_7_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
189
libraries/cmsis/cm4/device_support/system_at32f413.c
Normal file
189
libraries/cmsis/cm4/device_support/system_at32f413.c
Normal file
@@ -0,0 +1,189 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file system_at32f413.c
|
||||
* @brief contains all the functions for cmsis cortex-m4 system source file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup AT32F413_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "at32f413.h"
|
||||
|
||||
/** @addtogroup AT32F413_system_private_defines
|
||||
* @{
|
||||
*/
|
||||
#define VECT_TAB_OFFSET 0x0 /*!< vector table base offset field. this value must be a multiple of 0x200. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup AT32F413_system_private_variables
|
||||
* @{
|
||||
*/
|
||||
unsigned int system_core_clock = HICK_VALUE; /*!< system clock frequency (core clock) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup AT32F413_system_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief setup the microcontroller system
|
||||
* initialize the flash interface.
|
||||
* @note this function should be used only after reset.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if defined (__FPU_USED) && (__FPU_USED == 1U)
|
||||
SCB->CPACR |= ((3U << 10U * 2U) | /* set cp10 full access */
|
||||
(3U << 11U * 2U) ); /* set cp11 full access */
|
||||
#endif
|
||||
|
||||
/* reset the crm clock configuration to the default reset state(for debug purpose) */
|
||||
/* set hicken bit */
|
||||
CRM->ctrl_bit.hicken = TRUE;
|
||||
|
||||
/* wait hick stable */
|
||||
while(CRM->ctrl_bit.hickstbl != SET);
|
||||
|
||||
/* hick used as system clock */
|
||||
CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
|
||||
|
||||
/* wait sclk switch status */
|
||||
while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
|
||||
|
||||
/* reset hexten, hextbyps, cfden and pllen bits */
|
||||
CRM->ctrl &= ~(0x010D0000U);
|
||||
|
||||
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
|
||||
clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */
|
||||
CRM->cfg = 0;
|
||||
|
||||
/* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
|
||||
CRM->misc1 = 0;
|
||||
|
||||
/* disable all interrupts enable and clear pending bits */
|
||||
CRM->clkint = 0x009F0000;
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* vector table relocation in internal sram. */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* vector table relocation in internal flash. */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief update system_core_clock variable according to clock register values.
|
||||
* the system_core_clock variable contains the core clock (hclk), it can
|
||||
* be used by the user application to setup the systick timer or configure
|
||||
* other parameters.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void system_core_clock_update(void)
|
||||
{
|
||||
uint32_t pll_mult = 0, pll_mult_h = 0, pll_clock_source = 0, temp = 0, div_value = 0;
|
||||
crm_sclk_type sclk_source;
|
||||
|
||||
static const uint8_t sys_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/* get sclk source */
|
||||
sclk_source = crm_sysclk_switch_status_get();
|
||||
|
||||
switch(sclk_source)
|
||||
{
|
||||
case CRM_SCLK_HICK:
|
||||
if(((CRM->misc3_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
|
||||
system_core_clock = HICK_VALUE * 6;
|
||||
else
|
||||
system_core_clock = HICK_VALUE;
|
||||
break;
|
||||
case CRM_SCLK_HEXT:
|
||||
system_core_clock = HEXT_VALUE;
|
||||
break;
|
||||
case CRM_SCLK_PLL:
|
||||
pll_clock_source = CRM->cfg_bit.pllrcs;
|
||||
{
|
||||
/* get multiplication factor */
|
||||
pll_mult = CRM->cfg_bit.pllmult_l;
|
||||
pll_mult_h = CRM->cfg_bit.pllmult_h;
|
||||
/* process high bits */
|
||||
if((pll_mult_h != 0U) || (pll_mult == 15U)){
|
||||
pll_mult += ((16U * pll_mult_h) + 1U);
|
||||
}
|
||||
else
|
||||
{
|
||||
pll_mult += 2U;
|
||||
}
|
||||
|
||||
if (pll_clock_source == 0x00)
|
||||
{
|
||||
/* hick divided by 2 selected as pll clock entry */
|
||||
system_core_clock = (HICK_VALUE >> 1) * pll_mult;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* hext selected as pll clock entry */
|
||||
if (CRM->cfg_bit.pllhextdiv != RESET)
|
||||
{
|
||||
/* hext clock divided by 2 */
|
||||
system_core_clock = (HEXT_VALUE / 2) * pll_mult;
|
||||
}
|
||||
else
|
||||
{
|
||||
system_core_clock = HEXT_VALUE * pll_mult;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
system_core_clock = HICK_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
/* compute sclk, ahbclk frequency */
|
||||
/* get ahb division */
|
||||
temp = CRM->cfg_bit.ahbdiv;
|
||||
div_value = sys_ahb_div_table[temp];
|
||||
/* ahbclk frequency */
|
||||
system_core_clock = system_core_clock >> div_value;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
89
libraries/cmsis/cm4/device_support/system_at32f413.h
Normal file
89
libraries/cmsis/cm4/device_support/system_at32f413.h
Normal file
@@ -0,0 +1,89 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file system_at32f413.h
|
||||
* @brief cmsis cortex-m4 system header file.
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __SYSTEM_AT32F413_H
|
||||
#define __SYSTEM_AT32F413_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup AT32F413_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup AT32F413_system_clock_stable_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define HEXT_STABLE_DELAY (5000u)
|
||||
#define PLL_STABLE_DELAY (500u)
|
||||
#define SystemCoreClock system_core_clock
|
||||
#define DUMMY_NOP() {__NOP();__NOP();__NOP();__NOP();__NOP(); \
|
||||
__NOP();__NOP();__NOP();__NOP();__NOP(); \
|
||||
__NOP();__NOP();__NOP();__NOP();__NOP(); \
|
||||
__NOP();__NOP();__NOP();__NOP();__NOP();}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AT32F413_system_exported_variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern unsigned int system_core_clock; /*!< system clock frequency (core clock) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AT32F413_system_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void system_core_clock_update(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
988
libraries/drivers/inc/at32f413_can.h
Normal file
988
libraries/drivers/inc/at32f413_can.h
Normal file
@@ -0,0 +1,988 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_can.h
|
||||
* @brief at32f413 can header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F413_CAN_H
|
||||
#define __AT32F413_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f413.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_timeout_count
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FZC_TIMEOUT ((uint32_t)0x0000FFFF) /*!< time out for fzc bit */
|
||||
#define DZC_TIMEOUT ((uint32_t)0x0000FFFF) /*!< time out for dzc bit */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags_definition
|
||||
* @brief can flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_EAF_FLAG ((uint32_t)0x01) /*!< error active flag */
|
||||
#define CAN_EPF_FLAG ((uint32_t)0x02) /*!< error passive flag */
|
||||
#define CAN_BOF_FLAG ((uint32_t)0x03) /*!< bus-off flag */
|
||||
#define CAN_ETR_FLAG ((uint32_t)0x04) /*!< error type record flag */
|
||||
#define CAN_EOIF_FLAG ((uint32_t)0x05) /*!< error occur interrupt flag */
|
||||
#define CAN_TM0TCF_FLAG ((uint32_t)0x06) /*!< transmit mailbox 0 transmission completed flag */
|
||||
#define CAN_TM1TCF_FLAG ((uint32_t)0x07) /*!< transmit mailbox 1 transmission completed flag */
|
||||
#define CAN_TM2TCF_FLAG ((uint32_t)0x08) /*!< transmit mailbox 2 transmission completed flag */
|
||||
#define CAN_RF0MN_FLAG ((uint32_t)0x09) /*!< receive fifo 0 message num flag */
|
||||
#define CAN_RF0FF_FLAG ((uint32_t)0x0A) /*!< receive fifo 0 full flag */
|
||||
#define CAN_RF0OF_FLAG ((uint32_t)0x0B) /*!< receive fifo 0 overflow flag */
|
||||
#define CAN_RF1MN_FLAG ((uint32_t)0x0C) /*!< receive fifo 1 message num flag */
|
||||
#define CAN_RF1FF_FLAG ((uint32_t)0x0D) /*!< receive fifo 1 full flag */
|
||||
#define CAN_RF1OF_FLAG ((uint32_t)0x0E) /*!< receive fifo 1 overflow flag */
|
||||
#define CAN_QDZIF_FLAG ((uint32_t)0x0F) /*!< quit doze mode interrupt flag */
|
||||
#define CAN_EDZC_FLAG ((uint32_t)0x10) /*!< enter doze mode confirm flag */
|
||||
#define CAN_TMEF_FLAG ((uint32_t)0x11) /*!< transmit mailbox empty flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_interrupts_definition
|
||||
* @brief can interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_TCIEN_INT ((uint32_t)0x00000001) /*!< transmission complete interrupt */
|
||||
#define CAN_RF0MIEN_INT ((uint32_t)0x00000002) /*!< receive fifo 0 message interrupt */
|
||||
#define CAN_RF0FIEN_INT ((uint32_t)0x00000004) /*!< receive fifo 0 full interrupt */
|
||||
#define CAN_RF0OIEN_INT ((uint32_t)0x00000008) /*!< receive fifo 0 overflow interrupt */
|
||||
#define CAN_RF1MIEN_INT ((uint32_t)0x00000010) /*!< receive fifo 1 message interrupt */
|
||||
#define CAN_RF1FIEN_INT ((uint32_t)0x00000020) /*!< receive fifo 1 full interrupt */
|
||||
#define CAN_RF1OIEN_INT ((uint32_t)0x00000040) /*!< receive fifo 1 overflow interrupt */
|
||||
#define CAN_EAIEN_INT ((uint32_t)0x00000100) /*!< error active interrupt */
|
||||
#define CAN_EPIEN_INT ((uint32_t)0x00000200) /*!< error passive interrupt */
|
||||
#define CAN_BOIEN_INT ((uint32_t)0x00000400) /*!< bus-off interrupt */
|
||||
#define CAN_ETRIEN_INT ((uint32_t)0x00000800) /*!< error type record interrupt */
|
||||
#define CAN_EOIEN_INT ((uint32_t)0x00008000) /*!< error occur interrupt */
|
||||
#define CAN_QDZIEN_INT ((uint32_t)0x00010000) /*!< quit doze mode interrupt */
|
||||
#define CAN_EDZIEN_INT ((uint32_t)0x00020000) /*!< enter doze mode confirm interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief can flag clear operation macro definition val
|
||||
*/
|
||||
#define CAN_MSTS_EOIF_VAL ((uint32_t)0x00000004) /*!< eoif bit value, it clear by writing 1 */
|
||||
#define CAN_MSTS_QDZIF_VAL ((uint32_t)0x00000008) /*!< qdzif bit value, it clear by writing 1 */
|
||||
#define CAN_MSTS_EDZIF_VAL ((uint32_t)0x00000010) /*!< edzif bit value, it clear by writing 1 */
|
||||
#define CAN_TSTS_TM0TCF_VAL ((uint32_t)0x00000001) /*!< tm0tcf bit value, it clear by writing 1 */
|
||||
#define CAN_TSTS_TM1TCF_VAL ((uint32_t)0x00000100) /*!< tm1tcf bit value, it clear by writing 1 */
|
||||
#define CAN_TSTS_TM2TCF_VAL ((uint32_t)0x00010000) /*!< tm2tcf bit value, it clear by writing 1 */
|
||||
#define CAN_TSTS_TM0CT_VAL ((uint32_t)0x00000080) /*!< tm0ct bit value, it clear by writing 1 */
|
||||
#define CAN_TSTS_TM1CT_VAL ((uint32_t)0x00008000) /*!< tm1ct bit value, it clear by writing 1 */
|
||||
#define CAN_TSTS_TM2CT_VAL ((uint32_t)0x00800000) /*!< tm2ct bit value, it clear by writing 1 */
|
||||
#define CAN_RF0_RF0FF_VAL ((uint32_t)0x00000008) /*!< rf0ff bit value, it clear by writing 1 */
|
||||
#define CAN_RF0_RF0OF_VAL ((uint32_t)0x00000010) /*!< rf0of bit value, it clear by writing 1 */
|
||||
#define CAN_RF0_RF0R_VAL ((uint32_t)0x00000020) /*!< rf0r bit value, it clear by writing 1 */
|
||||
#define CAN_RF1_RF1FF_VAL ((uint32_t)0x00000008) /*!< rf1ff bit value, it clear by writing 1 */
|
||||
#define CAN_RF1_RF1OF_VAL ((uint32_t)0x00000010) /*!< rf1of bit value, it clear by writing 1 */
|
||||
#define CAN_RF1_RF1R_VAL ((uint32_t)0x00000020) /*!< rf1r bit value, it clear by writing 1 */
|
||||
|
||||
/** @defgroup CAN_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief can filter fifo
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_FILTER_FIFO0 = 0x00, /*!< filter fifo 0 assignment for filter x */
|
||||
CAN_FILTER_FIFO1 = 0x01 /*!< filter fifo 1 assignment for filter x */
|
||||
} can_filter_fifo_type;
|
||||
|
||||
/**
|
||||
* @brief can filter mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_FILTER_MODE_ID_MASK = 0x00, /*!< identifier mask mode */
|
||||
CAN_FILTER_MODE_ID_LIST = 0x01 /*!< identifier list mode */
|
||||
} can_filter_mode_type;
|
||||
|
||||
/**
|
||||
* @brief can filter bit width select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_FILTER_16BIT = 0x00, /*!< two 16-bit filters */
|
||||
CAN_FILTER_32BIT = 0x01 /*!< one 32-bit filter */
|
||||
} can_filter_bit_width_type;
|
||||
|
||||
/**
|
||||
* @brief can mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_MODE_COMMUNICATE = 0x00, /*!< communication mode */
|
||||
CAN_MODE_LOOPBACK = 0x01, /*!< loopback mode */
|
||||
CAN_MODE_LISTENONLY = 0x02, /*!< listen-only mode */
|
||||
CAN_MODE_LISTENONLY_LOOPBACK = 0x03 /*!< loopback combined with listen-only mode */
|
||||
} can_mode_type;
|
||||
|
||||
/**
|
||||
* @brief can operating mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_OPERATINGMODE_FREEZE = 0x00, /*!< freeze mode */
|
||||
CAN_OPERATINGMODE_DOZE = 0x01, /*!< doze mode */
|
||||
CAN_OPERATINGMODE_COMMUNICATE = 0x02 /*!< communication mode */
|
||||
} can_operating_mode_type;
|
||||
|
||||
/**
|
||||
* @brief can resynchronization adjust width
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_RSAW_1TQ = 0x00, /*!< 1 time quantum */
|
||||
CAN_RSAW_2TQ = 0x01, /*!< 2 time quantum */
|
||||
CAN_RSAW_3TQ = 0x02, /*!< 3 time quantum */
|
||||
CAN_RSAW_4TQ = 0x03 /*!< 4 time quantum */
|
||||
} can_rsaw_type;
|
||||
|
||||
/**
|
||||
* @brief can bit time segment 1
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_BTS1_1TQ = 0x00, /*!< 1 time quantum */
|
||||
CAN_BTS1_2TQ = 0x01, /*!< 2 time quantum */
|
||||
CAN_BTS1_3TQ = 0x02, /*!< 3 time quantum */
|
||||
CAN_BTS1_4TQ = 0x03, /*!< 4 time quantum */
|
||||
CAN_BTS1_5TQ = 0x04, /*!< 5 time quantum */
|
||||
CAN_BTS1_6TQ = 0x05, /*!< 6 time quantum */
|
||||
CAN_BTS1_7TQ = 0x06, /*!< 7 time quantum */
|
||||
CAN_BTS1_8TQ = 0x07, /*!< 8 time quantum */
|
||||
CAN_BTS1_9TQ = 0x08, /*!< 9 time quantum */
|
||||
CAN_BTS1_10TQ = 0x09, /*!< 10 time quantum */
|
||||
CAN_BTS1_11TQ = 0x0A, /*!< 11 time quantum */
|
||||
CAN_BTS1_12TQ = 0x0B, /*!< 12 time quantum */
|
||||
CAN_BTS1_13TQ = 0x0C, /*!< 13 time quantum */
|
||||
CAN_BTS1_14TQ = 0x0D, /*!< 14 time quantum */
|
||||
CAN_BTS1_15TQ = 0x0E, /*!< 15 time quantum */
|
||||
CAN_BTS1_16TQ = 0x0F /*!< 16 time quantum */
|
||||
} can_bts1_type;
|
||||
|
||||
/**
|
||||
* @brief can bit time segment 2
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_BTS2_1TQ = 0x00, /*!< 1 time quantum */
|
||||
CAN_BTS2_2TQ = 0x01, /*!< 2 time quantum */
|
||||
CAN_BTS2_3TQ = 0x02, /*!< 3 time quantum */
|
||||
CAN_BTS2_4TQ = 0x03, /*!< 4 time quantum */
|
||||
CAN_BTS2_5TQ = 0x04, /*!< 5 time quantum */
|
||||
CAN_BTS2_6TQ = 0x05, /*!< 6 time quantum */
|
||||
CAN_BTS2_7TQ = 0x06, /*!< 7 time quantum */
|
||||
CAN_BTS2_8TQ = 0x07 /*!< 8 time quantum */
|
||||
} can_bts2_type;
|
||||
|
||||
/**
|
||||
* @brief can identifier type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_ID_STANDARD = 0x00, /*!< standard Id */
|
||||
CAN_ID_EXTENDED = 0x01 /*!< extended Id */
|
||||
} can_identifier_type;
|
||||
|
||||
/**
|
||||
* @brief can transmission frame type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_TFT_DATA = 0x00, /*!< data frame */
|
||||
CAN_TFT_REMOTE = 0x01 /*!< remote frame */
|
||||
} can_trans_frame_type;
|
||||
|
||||
/**
|
||||
* @brief can tx mailboxes
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_TX_MAILBOX0 = 0x00, /*!< can tx mailbox 0 */
|
||||
CAN_TX_MAILBOX1 = 0x01, /*!< can tx mailbox 1 */
|
||||
CAN_TX_MAILBOX2 = 0x02 /*!< can tx mailbox 2 */
|
||||
} can_tx_mailbox_num_type;
|
||||
|
||||
/**
|
||||
* @brief can receive fifo
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_RX_FIFO0 = 0x00, /*!< can fifo 0 used to receive */
|
||||
CAN_RX_FIFO1 = 0x01 /*!< can fifo 1 used to receive */
|
||||
} can_rx_fifo_num_type;
|
||||
|
||||
/**
|
||||
* @brief can transmit status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_TX_STATUS_FAILED = 0x00, /*!< can transmission failed */
|
||||
CAN_TX_STATUS_SUCCESSFUL = 0x01, /*!< can transmission successful */
|
||||
CAN_TX_STATUS_PENDING = 0x02, /*!< can transmission pending */
|
||||
CAN_TX_STATUS_NO_EMPTY = 0x04 /*!< can transmission no empty mailbox */
|
||||
} can_transmit_status_type;
|
||||
|
||||
/**
|
||||
* @brief can enter doze mode status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_ENTER_DOZE_FAILED = 0x00, /*!< can enter the doze mode failed */
|
||||
CAN_ENTER_DOZE_SUCCESSFUL = 0x01 /*!< can enter the doze mode successful */
|
||||
} can_enter_doze_status_type;
|
||||
|
||||
/**
|
||||
* @brief can quit doze mode status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_QUIT_DOZE_FAILED = 0x00, /*!< can quit doze mode failed */
|
||||
CAN_QUIT_DOZE_SUCCESSFUL = 0x01 /*!< can quit doze mode successful */
|
||||
} can_quit_doze_status_type;
|
||||
|
||||
/**
|
||||
* @brief can message discarding rule select when overflow
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_DISCARDING_FIRST_RECEIVED = 0x00, /*!< can discarding the first received message */
|
||||
CAN_DISCARDING_LAST_RECEIVED = 0x01 /*!< can discarding the last received message */
|
||||
} can_msg_discarding_rule_type;
|
||||
|
||||
/**
|
||||
* @brief can multiple message sending sequence rule
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_SENDING_BY_ID = 0x00, /*!< can sending the minimum id message first*/
|
||||
CAN_SENDING_BY_REQUEST = 0x01 /*!< can sending the first request message first */
|
||||
} can_msg_sending_rule_type;
|
||||
|
||||
/**
|
||||
* @brief can error type record
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_ERRORRECORD_NOERR = 0x00, /*!< no error */
|
||||
CAN_ERRORRECORD_STUFFERR = 0x01, /*!< stuff error */
|
||||
CAN_ERRORRECORD_FORMERR = 0x02, /*!< form error */
|
||||
CAN_ERRORRECORD_ACKERR = 0x03, /*!< acknowledgment error */
|
||||
CAN_ERRORRECORD_BITRECESSIVEERR = 0x04, /*!< bit recessive error */
|
||||
CAN_ERRORRECORD_BITDOMINANTERR = 0x05, /*!< bit dominant error */
|
||||
CAN_ERRORRECORD_CRCERR = 0x06, /*!< crc error */
|
||||
CAN_ERRORRECORD_SOFTWARESETERR = 0x07 /*!< software set error */
|
||||
} can_error_record_type;
|
||||
|
||||
/**
|
||||
* @brief can init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
can_mode_type mode_selection; /*!< specifies the can mode.*/
|
||||
|
||||
confirm_state ttc_enable; /*!< time triggered communication mode enable */
|
||||
|
||||
confirm_state aebo_enable; /*!< automatic exit bus-off enable */
|
||||
|
||||
confirm_state aed_enable; /*!< automatic exit doze mode enable */
|
||||
|
||||
confirm_state prsf_enable; /*!< prohibit retransmission when sending fails enable */
|
||||
|
||||
can_msg_discarding_rule_type mdrsel_selection; /*!< message discarding rule select when overflow */
|
||||
|
||||
can_msg_sending_rule_type mmssr_selection; /*!< multiple message sending sequence rule */
|
||||
|
||||
} can_base_type;
|
||||
|
||||
/**
|
||||
* @brief can baudrate structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/
|
||||
|
||||
can_rsaw_type rsaw_size; /*!< resynchronization adjust width */
|
||||
|
||||
can_bts1_type bts1_size; /*!< bit time segment 1 */
|
||||
|
||||
can_bts2_type bts2_size; /*!< bit time segment 2 */
|
||||
|
||||
} can_baudrate_type;
|
||||
|
||||
/**
|
||||
* @brief can filter init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
confirm_state filter_activate_enable; /*!< enable or disable the filter activate.*/
|
||||
|
||||
can_filter_mode_type filter_mode; /*!< config the filter mode mask or list.*/
|
||||
|
||||
can_filter_fifo_type filter_fifo; /*!< config the fifo which will be assigned to the filter. */
|
||||
|
||||
uint8_t filter_number; /*!< config the filter number, parameter ranges from 0 to 13. */
|
||||
|
||||
can_filter_bit_width_type filter_bit; /*!< config the filter bit width 16bit or 32bit.*/
|
||||
|
||||
uint16_t filter_id_high; /*!< config the filter identification, for 32-bit configuration
|
||||
it's high 16 bits, for 16-bit configuration it's first. */
|
||||
|
||||
uint16_t filter_id_low; /*!< config the filter identification, for 32-bit configuration
|
||||
it's low 16 bits, for 16-bit configuration it's second. */
|
||||
|
||||
uint16_t filter_mask_high; /*!< config the filter mask or identification, according to the filtering mode,
|
||||
for 32-bit configuration it's high 16 bits, for 16-bit configuration it's first. */
|
||||
|
||||
uint16_t filter_mask_low; /*!< config the filter mask or identification, according to the filtering mode,
|
||||
for 32-bit configuration it's low 16 bits, for 16-bit configuration it's second. */
|
||||
} can_filter_init_type;
|
||||
|
||||
/**
|
||||
* @brief can tx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t standard_id; /*!< specifies the 11 bits standard identifier.
|
||||
this parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
|
||||
this parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
can_identifier_type id_type; /*!< specifies identifier type for the transmit message.*/
|
||||
|
||||
can_trans_frame_type frame_type; /*!< specifies frame type for the transmit message.*/
|
||||
|
||||
uint8_t dlc; /*!< specifies frame data length that will be transmitted.
|
||||
this parameter can be a value between 0 to 8 */
|
||||
|
||||
uint8_t data[8]; /*!< contains the transmit data. it ranges from 0 to 0xFF. */
|
||||
|
||||
} can_tx_message_type;
|
||||
|
||||
/**
|
||||
* @brief can rx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t standard_id; /*!< specifies the 11 bits standard identifier
|
||||
this parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
|
||||
this parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
can_identifier_type id_type; /*!< specifies identifier type for the receive message.*/
|
||||
|
||||
can_trans_frame_type frame_type; /*!< specifies frame type for the receive message.*/
|
||||
|
||||
uint8_t dlc; /*!< specifies the frame data length that will be received.
|
||||
this parameter can be a value between 0 to 8 */
|
||||
|
||||
uint8_t data[8]; /*!< contains the receive data. it ranges from 0 to 0xFF.*/
|
||||
|
||||
uint8_t filter_index; /*!< specifies the message stored in which filter
|
||||
this parameter can be a value between 0 to 0xFF */
|
||||
} can_rx_message_type;
|
||||
|
||||
/**
|
||||
* @brief can controller area network tx mailbox
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief can tmi register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tmi;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmsr : 1; /* [0] */
|
||||
__IO uint32_t tmfrsel : 1; /* [1] */
|
||||
__IO uint32_t tmidsel : 1; /* [2] */
|
||||
__IO uint32_t tmeid : 18;/* [20:3] */
|
||||
__IO uint32_t tmsid : 11;/* [31:21] */
|
||||
} tmi_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can tmc register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tmc;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmdtbl : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 4; /* [7:4] */
|
||||
__IO uint32_t tmtsten : 1; /* [8] */
|
||||
__IO uint32_t reserved2 : 7; /* [15:9] */
|
||||
__IO uint32_t tmts : 16;/* [31:16] */
|
||||
} tmc_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can tmdtl register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tmdtl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmdt0 : 8; /* [7:0] */
|
||||
__IO uint32_t tmdt1 : 8; /* [15:8] */
|
||||
__IO uint32_t tmdt2 : 8; /* [23:16] */
|
||||
__IO uint32_t tmdt3 : 8; /* [31:24] */
|
||||
} tmdtl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can tmdth register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tmdth;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmdt4 : 8; /* [7:0] */
|
||||
__IO uint32_t tmdt5 : 8; /* [15:8] */
|
||||
__IO uint32_t tmdt6 : 8; /* [23:16] */
|
||||
__IO uint32_t tmdt7 : 8; /* [31:24] */
|
||||
} tmdth_bit;
|
||||
};
|
||||
} can_tx_mailbox_type;
|
||||
|
||||
/**
|
||||
* @brief can controller area network fifo mailbox
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief can rfi register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rfi;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 1; /* [0] */
|
||||
__IO uint32_t rffri : 1; /* [1] */
|
||||
__IO uint32_t rfidi : 1; /* [2] */
|
||||
__IO uint32_t rfeid : 18;/* [20:3] */
|
||||
__IO uint32_t rfsid : 11;/* [31:21] */
|
||||
} rfi_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can rfc register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rfc;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rfdtl : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 4; /* [7:4] */
|
||||
__IO uint32_t rffmn : 8; /* [15:8] */
|
||||
__IO uint32_t rfts : 16;/* [31:16] */
|
||||
} rfc_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can rfdtl register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rfdtl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rfdt0 : 8; /* [7:0] */
|
||||
__IO uint32_t rfdt1 : 8; /* [15:8] */
|
||||
__IO uint32_t rfdt2 : 8; /* [23:16] */
|
||||
__IO uint32_t rfdt3 : 8; /* [31:24] */
|
||||
} rfdtl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can rfdth register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rfdth;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rfdt4 : 8; /* [7:0] */
|
||||
__IO uint32_t rfdt5 : 8; /* [15:8] */
|
||||
__IO uint32_t rfdt6 : 8; /* [23:16] */
|
||||
__IO uint32_t rfdt7 : 8; /* [31:24] */
|
||||
} rfdth_bit;
|
||||
};
|
||||
} can_fifo_mailbox_type;
|
||||
|
||||
/**
|
||||
* @brief can controller area network filter bit register
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ffdb1;
|
||||
__IO uint32_t ffdb2;
|
||||
} can_filter_register_type;
|
||||
|
||||
/**
|
||||
* @brief type define can register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief can mctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t mctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fzen : 1; /* [0] */
|
||||
__IO uint32_t dzen : 1; /* [1] */
|
||||
__IO uint32_t mmssr : 1; /* [2] */
|
||||
__IO uint32_t mdrsel : 1; /* [3] */
|
||||
__IO uint32_t prsfen : 1; /* [4] */
|
||||
__IO uint32_t aeden : 1; /* [5] */
|
||||
__IO uint32_t aeboen : 1; /* [6] */
|
||||
__IO uint32_t ttcen : 1; /* [7] */
|
||||
__IO uint32_t reserved1 : 7; /* [14:8] */
|
||||
__IO uint32_t sprst : 1; /* [15] */
|
||||
__IO uint32_t ptd : 1; /* [16] */
|
||||
__IO uint32_t reserved2 : 15;/*[31:17] */
|
||||
} mctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can msts register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t msts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fzc : 1; /* [0] */
|
||||
__IO uint32_t dzc : 1; /* [1] */
|
||||
__IO uint32_t eoif : 1; /* [2] */
|
||||
__IO uint32_t qdzif : 1; /* [3] */
|
||||
__IO uint32_t edzif : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 3; /* [7:5] */
|
||||
__IO uint32_t cuss : 1; /* [8] */
|
||||
__IO uint32_t curs : 1; /* [9] */
|
||||
__IO uint32_t lsamprx : 1; /* [10] */
|
||||
__IO uint32_t realrx : 1; /* [11] */
|
||||
__IO uint32_t reserved2 : 20;/*[31:12] */
|
||||
} msts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can tsts register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tm0tcf : 1; /* [0] */
|
||||
__IO uint32_t tm0tsf : 1; /* [1] */
|
||||
__IO uint32_t tm0alf : 1; /* [2] */
|
||||
__IO uint32_t tm0tef : 1; /* [3] */
|
||||
__IO uint32_t reserved1 : 3; /* [6:4] */
|
||||
__IO uint32_t tm0ct : 1; /* [7] */
|
||||
__IO uint32_t tm1tcf : 1; /* [8] */
|
||||
__IO uint32_t tm1tsf : 1; /* [9] */
|
||||
__IO uint32_t tm1alf : 1; /* [10] */
|
||||
__IO uint32_t tm1tef : 1; /* [11] */
|
||||
__IO uint32_t reserved2 : 3; /* [14:12] */
|
||||
__IO uint32_t tm1ct : 1; /* [15] */
|
||||
__IO uint32_t tm2tcf : 1; /* [16] */
|
||||
__IO uint32_t tm2tsf : 1; /* [17] */
|
||||
__IO uint32_t tm2alf : 1; /* [18] */
|
||||
__IO uint32_t tm2tef : 1; /* [19] */
|
||||
__IO uint32_t reserved3 : 3; /* [22:20] */
|
||||
__IO uint32_t tm2ct : 1; /* [23] */
|
||||
__IO uint32_t tmnr : 2; /* [25:24] */
|
||||
__IO uint32_t tm0ef : 1; /* [26] */
|
||||
__IO uint32_t tm1ef : 1; /* [27] */
|
||||
__IO uint32_t tm2ef : 1; /* [28] */
|
||||
__IO uint32_t tm0lpf : 1; /* [29] */
|
||||
__IO uint32_t tm1lpf : 1; /* [30] */
|
||||
__IO uint32_t tm2lpf : 1; /* [31] */
|
||||
} tsts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can rf0 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rf0;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rf0mn : 2; /* [1:0] */
|
||||
__IO uint32_t reserved1 : 1; /* [2] */
|
||||
__IO uint32_t rf0ff : 1; /* [3] */
|
||||
__IO uint32_t rf0of : 1; /* [4] */
|
||||
__IO uint32_t rf0r : 1; /* [5] */
|
||||
__IO uint32_t reserved2 : 26;/* [31:6] */
|
||||
} rf0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can rf1 register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rf1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rf1mn : 2; /* [1:0] */
|
||||
__IO uint32_t reserved1 : 1; /* [2] */
|
||||
__IO uint32_t rf1ff : 1; /* [3] */
|
||||
__IO uint32_t rf1of : 1; /* [4] */
|
||||
__IO uint32_t rf1r : 1; /* [5] */
|
||||
__IO uint32_t reserved2 : 26;/* [31:6] */
|
||||
} rf1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can inten register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t inten;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tcien : 1; /* [0] */
|
||||
__IO uint32_t rf0mien : 1; /* [1] */
|
||||
__IO uint32_t rf0fien : 1; /* [2] */
|
||||
__IO uint32_t rf0oien : 1; /* [3] */
|
||||
__IO uint32_t rf1mien : 1; /* [4] */
|
||||
__IO uint32_t rf1fien : 1; /* [5] */
|
||||
__IO uint32_t rf1oien : 1; /* [6] */
|
||||
__IO uint32_t reserved1 : 1; /* [7] */
|
||||
__IO uint32_t eaien : 1; /* [8] */
|
||||
__IO uint32_t epien : 1; /* [9] */
|
||||
__IO uint32_t boien : 1; /* [10] */
|
||||
__IO uint32_t etrien : 1; /* [11] */
|
||||
__IO uint32_t reserved2 : 3; /* [14:12] */
|
||||
__IO uint32_t eoien : 1; /* [15] */
|
||||
__IO uint32_t qdzien : 1; /* [16] */
|
||||
__IO uint32_t edzien : 1; /* [17] */
|
||||
__IO uint32_t reserved3 : 14;/* [31:18] */
|
||||
} inten_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can ests register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ests;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t eaf : 1; /* [0] */
|
||||
__IO uint32_t epf : 1; /* [1] */
|
||||
__IO uint32_t bof : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 1; /* [3] */
|
||||
__IO uint32_t etr : 3; /* [6:4] */
|
||||
__IO uint32_t reserved2 : 9; /* [15:7] */
|
||||
__IO uint32_t tec : 8; /* [23:16] */
|
||||
__IO uint32_t rec : 8; /* [31:24] */
|
||||
} ests_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can btmg register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t btmg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t brdiv : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 4; /* [15:12] */
|
||||
__IO uint32_t bts1 : 4; /* [19:16] */
|
||||
__IO uint32_t bts2 : 3; /* [22:20] */
|
||||
__IO uint32_t reserved2 : 1; /* [23] */
|
||||
__IO uint32_t rsaw : 2; /* [25:24] */
|
||||
__IO uint32_t reserved3 : 4; /* [29:26] */
|
||||
__IO uint32_t lben : 1; /* [30] */
|
||||
__IO uint32_t loen : 1; /* [31] */
|
||||
} btmg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can reserved register, offset:0x20~0x17C
|
||||
*/
|
||||
__IO uint32_t reserved1[88];
|
||||
|
||||
/**
|
||||
* @brief can controller area network tx mailbox register, offset:0x180~0x1AC
|
||||
*/
|
||||
can_tx_mailbox_type tx_mailbox[3];
|
||||
|
||||
/**
|
||||
* @brief can controller area network fifo mailbox register, offset:0x1B0~0x1CC
|
||||
*/
|
||||
can_fifo_mailbox_type fifo_mailbox[2];
|
||||
|
||||
/**
|
||||
* @brief can reserved register, offset:0x1D0~0x1FC
|
||||
*/
|
||||
__IO uint32_t reserved2[12];
|
||||
|
||||
/**
|
||||
* @brief can fctrl register, offset:0x200
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t fctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fcs : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 31;/* [31:1] */
|
||||
} fctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can fmcfg register, offset:0x204
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t fmcfg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fmsel0 : 1; /* [0] */
|
||||
__IO uint32_t fmsel1 : 1; /* [1] */
|
||||
__IO uint32_t fmsel2 : 1; /* [2] */
|
||||
__IO uint32_t fmsel3 : 1; /* [3] */
|
||||
__IO uint32_t fmsel4 : 1; /* [4] */
|
||||
__IO uint32_t fmsel5 : 1; /* [5] */
|
||||
__IO uint32_t fmsel6 : 1; /* [6] */
|
||||
__IO uint32_t fmsel7 : 1; /* [7] */
|
||||
__IO uint32_t fmsel8 : 1; /* [8] */
|
||||
__IO uint32_t fmsel9 : 1; /* [9] */
|
||||
__IO uint32_t fmsel10 : 1; /* [10] */
|
||||
__IO uint32_t fmsel11 : 1; /* [11] */
|
||||
__IO uint32_t fmsel12 : 1; /* [12] */
|
||||
__IO uint32_t fmsel13 : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 18;/* [31:14] */
|
||||
} fmcfg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can reserved register, offset:0x208
|
||||
*/
|
||||
__IO uint32_t reserved3;
|
||||
|
||||
/**
|
||||
* @brief can fbwcfg register, offset:0x20C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t fbwcfg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fbwsel0 : 1; /* [0] */
|
||||
__IO uint32_t fbwsel1 : 1; /* [1] */
|
||||
__IO uint32_t fbwsel2 : 1; /* [2] */
|
||||
__IO uint32_t fbwsel3 : 1; /* [3] */
|
||||
__IO uint32_t fbwsel4 : 1; /* [4] */
|
||||
__IO uint32_t fbwsel5 : 1; /* [5] */
|
||||
__IO uint32_t fbwsel6 : 1; /* [6] */
|
||||
__IO uint32_t fbwsel7 : 1; /* [7] */
|
||||
__IO uint32_t fbwsel8 : 1; /* [8] */
|
||||
__IO uint32_t fbwsel9 : 1; /* [9] */
|
||||
__IO uint32_t fbwsel10 : 1; /* [10] */
|
||||
__IO uint32_t fbwsel11 : 1; /* [11] */
|
||||
__IO uint32_t fbwsel12 : 1; /* [12] */
|
||||
__IO uint32_t fbwsel13 : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 18;/* [31:14] */
|
||||
} fbwcfg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can reserved register, offset:0x210
|
||||
*/
|
||||
__IO uint32_t reserved4;
|
||||
|
||||
/**
|
||||
* @brief can frf register, offset:0x214
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t frf;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t frfsel0 : 1; /* [0] */
|
||||
__IO uint32_t frfsel1 : 1; /* [1] */
|
||||
__IO uint32_t frfsel2 : 1; /* [2] */
|
||||
__IO uint32_t frfsel3 : 1; /* [3] */
|
||||
__IO uint32_t frfsel4 : 1; /* [4] */
|
||||
__IO uint32_t frfsel5 : 1; /* [5] */
|
||||
__IO uint32_t frfsel6 : 1; /* [6] */
|
||||
__IO uint32_t frfsel7 : 1; /* [7] */
|
||||
__IO uint32_t frfsel8 : 1; /* [8] */
|
||||
__IO uint32_t frfsel9 : 1; /* [9] */
|
||||
__IO uint32_t frfsel10 : 1; /* [10] */
|
||||
__IO uint32_t frfsel11 : 1; /* [11] */
|
||||
__IO uint32_t frfsel12 : 1; /* [12] */
|
||||
__IO uint32_t frfsel13 : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 18;/* [31:14] */
|
||||
} frf_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can reserved register, offset:0x218
|
||||
*/
|
||||
__IO uint32_t reserved5;
|
||||
|
||||
/**
|
||||
* @brief can facfg register, offset:0x21C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t facfg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t faen0 : 1; /* [0] */
|
||||
__IO uint32_t faen1 : 1; /* [1] */
|
||||
__IO uint32_t faen2 : 1; /* [2] */
|
||||
__IO uint32_t faen3 : 1; /* [3] */
|
||||
__IO uint32_t faen4 : 1; /* [4] */
|
||||
__IO uint32_t faen5 : 1; /* [5] */
|
||||
__IO uint32_t faen6 : 1; /* [6] */
|
||||
__IO uint32_t faen7 : 1; /* [7] */
|
||||
__IO uint32_t faen8 : 1; /* [8] */
|
||||
__IO uint32_t faen9 : 1; /* [9] */
|
||||
__IO uint32_t faen10 : 1; /* [10] */
|
||||
__IO uint32_t faen11 : 1; /* [11] */
|
||||
__IO uint32_t faen12 : 1; /* [12] */
|
||||
__IO uint32_t faen13 : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 18;/* [31:14] */
|
||||
} facfg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can reserved register, offset:0x220~0x23C
|
||||
*/
|
||||
__IO uint32_t reserved6[8];
|
||||
|
||||
/**
|
||||
* @brief can ffb register, offset:0x240~0x2AC
|
||||
*/
|
||||
can_filter_register_type ffb[14];
|
||||
} can_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define CAN1 ((can_type *) CAN1_BASE)
|
||||
#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \
|
||||
defined (AT32F413Kx)
|
||||
#define CAN2 ((can_type *) CAN2_BASE)
|
||||
#endif
|
||||
|
||||
/** @defgroup CAN_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void can_reset(can_type* can_x);
|
||||
void can_baudrate_default_para_init(can_baudrate_type* can_baudrate_struct);
|
||||
error_status can_baudrate_set(can_type* can_x, can_baudrate_type* can_baudrate_struct);
|
||||
void can_default_para_init(can_base_type* can_base_struct);
|
||||
error_status can_base_init(can_type* can_x, can_base_type* can_base_struct);
|
||||
void can_filter_default_para_init(can_filter_init_type* can_filter_init_struct);
|
||||
void can_filter_init(can_type* can_x, can_filter_init_type* can_filter_init_struct);
|
||||
void can_debug_transmission_prohibit(can_type* can_x, confirm_state new_state);
|
||||
void can_ttc_mode_enable(can_type* can_x, confirm_state new_state);
|
||||
uint8_t can_message_transmit(can_type* can_x, can_tx_message_type* tx_message_struct);
|
||||
can_transmit_status_type can_transmit_status_get(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
|
||||
void can_transmit_cancel(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
|
||||
void can_message_receive(can_type* can_x, can_rx_fifo_num_type fifo_number, can_rx_message_type* rx_message_struct);
|
||||
void can_receive_fifo_release(can_type* can_x, can_rx_fifo_num_type fifo_number);
|
||||
uint8_t can_receive_message_pending_get(can_type* can_x, can_rx_fifo_num_type fifo_number);
|
||||
error_status can_operating_mode_set(can_type* can_x, can_operating_mode_type can_operating_mode);
|
||||
can_enter_doze_status_type can_doze_mode_enter(can_type* can_x);
|
||||
can_quit_doze_status_type can_doze_mode_exit(can_type* can_x);
|
||||
can_error_record_type can_error_type_record_get(can_type* can_x);
|
||||
uint8_t can_receive_error_counter_get(can_type* can_x);
|
||||
uint8_t can_transmit_error_counter_get(can_type* can_x);
|
||||
void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state);
|
||||
flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag);
|
||||
flag_status can_flag_get(can_type* can_x, uint32_t can_flag);
|
||||
void can_flag_clear(can_type* can_x, uint32_t can_flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
900
libraries/drivers/inc/at32f413_crm.h
Normal file
900
libraries/drivers/inc/at32f413_crm.h
Normal file
@@ -0,0 +1,900 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_crm.h
|
||||
* @brief at32f413 crm header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F413_CRM_H
|
||||
#define __AT32F413_CRM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f413.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRM
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRM_REG(value) PERIPH_REG(CRM_BASE, value)
|
||||
#define CRM_REG_BIT(value) PERIPH_REG_BIT(value)
|
||||
|
||||
/** @defgroup CRM_flags_definition
|
||||
* @brief crm flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRM_HICK_STABLE_FLAG MAKE_VALUE(0x00, 1) /*!< high speed internal clock stable flag */
|
||||
#define CRM_HEXT_STABLE_FLAG MAKE_VALUE(0x00, 17) /*!< high speed external crystal stable flag */
|
||||
#define CRM_PLL_STABLE_FLAG MAKE_VALUE(0x00, 25) /*!< phase locking loop stable flag */
|
||||
#define CRM_LEXT_STABLE_FLAG MAKE_VALUE(0x20, 1) /*!< low speed external crystal stable flag */
|
||||
#define CRM_LICK_STABLE_FLAG MAKE_VALUE(0x24, 1) /*!< low speed internal clock stable flag */
|
||||
#define CRM_ALL_RESET_FLAG MAKE_VALUE(0x24, 24) /*!< all reset flag */
|
||||
#define CRM_NRST_RESET_FLAG MAKE_VALUE(0x24, 26) /*!< nrst pin reset flag */
|
||||
#define CRM_POR_RESET_FLAG MAKE_VALUE(0x24, 27) /*!< power on reset flag */
|
||||
#define CRM_SW_RESET_FLAG MAKE_VALUE(0x24, 28) /*!< software reset flag */
|
||||
#define CRM_WDT_RESET_FLAG MAKE_VALUE(0x24, 29) /*!< watchdog timer reset flag */
|
||||
#define CRM_WWDT_RESET_FLAG MAKE_VALUE(0x24, 30) /*!< window watchdog timer reset flag */
|
||||
#define CRM_LOWPOWER_RESET_FLAG MAKE_VALUE(0x24, 31) /*!< low-power reset flag */
|
||||
#define CRM_LICK_READY_INT_FLAG MAKE_VALUE(0x08, 0) /*!< low speed internal clock stable interrupt ready flag */
|
||||
#define CRM_LEXT_READY_INT_FLAG MAKE_VALUE(0x08, 1) /*!< low speed external crystal stable interrupt ready flag */
|
||||
#define CRM_HICK_READY_INT_FLAG MAKE_VALUE(0x08, 2) /*!< high speed internal clock stable interrupt ready flag */
|
||||
#define CRM_HEXT_READY_INT_FLAG MAKE_VALUE(0x08, 3) /*!< high speed external crystal stable interrupt ready flag */
|
||||
#define CRM_PLL_READY_INT_FLAG MAKE_VALUE(0x08, 4) /*!< phase locking loop stable interrupt ready flag */
|
||||
#define CRM_CLOCK_FAILURE_INT_FLAG MAKE_VALUE(0x08, 7) /*!< clock failure interrupt ready flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRM_interrupts_definition
|
||||
* @brief crm interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRM_LICK_STABLE_INT ((uint32_t)0x00000100) /*!< low speed internal clock stable interrupt */
|
||||
#define CRM_LEXT_STABLE_INT ((uint32_t)0x00000200) /*!< low speed external crystal stable interrupt */
|
||||
#define CRM_HICK_STABLE_INT ((uint32_t)0x00000400) /*!< high speed internal clock stable interrupt */
|
||||
#define CRM_HEXT_STABLE_INT ((uint32_t)0x00000800) /*!< high speed external crystal stable interrupt */
|
||||
#define CRM_PLL_STABLE_INT ((uint32_t)0x00001000) /*!< phase locking loop stable interrupt */
|
||||
#define CRM_CLOCK_FAILURE_INT ((uint32_t)0x00800000) /*!< clock failure interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRM_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief crm periph clock
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/* ahb periph */
|
||||
CRM_DMA1_PERIPH_CLOCK = MAKE_VALUE(0x14, 0), /*!< dma1 periph clock */
|
||||
CRM_DMA2_PERIPH_CLOCK = MAKE_VALUE(0x14, 1), /*!< dma2 periph clock */
|
||||
CRM_CRC_PERIPH_CLOCK = MAKE_VALUE(0x14, 6), /*!< crc periph clock */
|
||||
CRM_SDIO1_PERIPH_CLOCK = MAKE_VALUE(0x14, 10), /*!< sdio1 periph clock */
|
||||
/* apb2 periph */
|
||||
CRM_IOMUX_PERIPH_CLOCK = MAKE_VALUE(0x18, 0), /*!< iomux periph clock */
|
||||
CRM_GPIOA_PERIPH_CLOCK = MAKE_VALUE(0x18, 2), /*!< gpioa periph clock */
|
||||
CRM_GPIOB_PERIPH_CLOCK = MAKE_VALUE(0x18, 3), /*!< gpiob periph clock */
|
||||
CRM_GPIOC_PERIPH_CLOCK = MAKE_VALUE(0x18, 4), /*!< gpioc periph clock */
|
||||
CRM_GPIOD_PERIPH_CLOCK = MAKE_VALUE(0x18, 5), /*!< gpiod periph clock */
|
||||
CRM_GPIOF_PERIPH_CLOCK = MAKE_VALUE(0x18, 7), /*!< gpiof periph clock */
|
||||
CRM_ADC1_PERIPH_CLOCK = MAKE_VALUE(0x18, 9), /*!< adc1 periph clock */
|
||||
CRM_ADC2_PERIPH_CLOCK = MAKE_VALUE(0x18, 10), /*!< adc2 periph clock */
|
||||
CRM_TMR1_PERIPH_CLOCK = MAKE_VALUE(0x18, 11), /*!< tmr1 periph clock */
|
||||
CRM_SPI1_PERIPH_CLOCK = MAKE_VALUE(0x18, 12), /*!< spi1 periph clock */
|
||||
CRM_TMR8_PERIPH_CLOCK = MAKE_VALUE(0x18, 13), /*!< tmr8 periph clock */
|
||||
CRM_USART1_PERIPH_CLOCK = MAKE_VALUE(0x18, 14), /*!< usart1 periph clock */
|
||||
CRM_TMR9_PERIPH_CLOCK = MAKE_VALUE(0x18, 19), /*!< tmr9 periph clock */
|
||||
CRM_TMR10_PERIPH_CLOCK = MAKE_VALUE(0x18, 20), /*!< tmr10 periph clock */
|
||||
CRM_TMR11_PERIPH_CLOCK = MAKE_VALUE(0x18, 21), /*!< tmr11 periph clock */
|
||||
CRM_ACC_PERIPH_CLOCK = MAKE_VALUE(0x18, 22), /*!< acc periph clock */
|
||||
/* apb1 periph */
|
||||
CRM_TMR2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 0), /*!< tmr2 periph clock */
|
||||
CRM_TMR3_PERIPH_CLOCK = MAKE_VALUE(0x1C, 1), /*!< tmr3 periph clock */
|
||||
CRM_TMR4_PERIPH_CLOCK = MAKE_VALUE(0x1C, 2), /*!< tmr4 periph clock */
|
||||
CRM_TMR5_PERIPH_CLOCK = MAKE_VALUE(0x1C, 3), /*!< tmr5 periph clock */
|
||||
CRM_WWDT_PERIPH_CLOCK = MAKE_VALUE(0x1C, 11), /*!< wwdt periph clock */
|
||||
CRM_SPI2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 14), /*!< spi2 periph clock */
|
||||
CRM_USART2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 17), /*!< usart2 periph clock */
|
||||
CRM_USART3_PERIPH_CLOCK = MAKE_VALUE(0x1C, 18), /*!< usart3 periph clock */
|
||||
CRM_UART4_PERIPH_CLOCK = MAKE_VALUE(0x1C, 19), /*!< uart4 periph clock */
|
||||
CRM_UART5_PERIPH_CLOCK = MAKE_VALUE(0x1C, 20), /*!< uart5 periph clock */
|
||||
CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 21), /*!< i2c1 periph clock */
|
||||
CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 22), /*!< i2c2 periph clock */
|
||||
CRM_USB_PERIPH_CLOCK = MAKE_VALUE(0x1C, 23), /*!< usb periph clock */
|
||||
CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 25), /*!< can1 periph clock */
|
||||
CRM_BPR_PERIPH_CLOCK = MAKE_VALUE(0x1C, 27), /*!< bpr periph clock */
|
||||
CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28), /*!< pwc periph clock */
|
||||
CRM_CAN2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 31) /*!< can2 periph clock */
|
||||
|
||||
} crm_periph_clock_type;
|
||||
|
||||
/**
|
||||
* @brief crm periph reset
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/* apb2 periph */
|
||||
CRM_IOMUX_PERIPH_RESET = MAKE_VALUE(0x0C, 0), /*!< iomux periph reset */
|
||||
CRM_EXINT_PERIPH_RESET = MAKE_VALUE(0x0C, 1), /*!< exint periph reset */
|
||||
CRM_GPIOA_PERIPH_RESET = MAKE_VALUE(0x0C, 2), /*!< gpioa periph reset */
|
||||
CRM_GPIOB_PERIPH_RESET = MAKE_VALUE(0x0C, 3), /*!< gpiob periph reset */
|
||||
CRM_GPIOC_PERIPH_RESET = MAKE_VALUE(0x0C, 4), /*!< gpioc periph reset */
|
||||
CRM_GPIOD_PERIPH_RESET = MAKE_VALUE(0x0C, 5), /*!< gpiod periph reset */
|
||||
CRM_GPIOF_PERIPH_RESET = MAKE_VALUE(0x0C, 7), /*!< gpiof periph reset */
|
||||
CRM_ADC1_PERIPH_RESET = MAKE_VALUE(0x0C, 9), /*!< adc1 periph reset */
|
||||
CRM_ADC2_PERIPH_RESET = MAKE_VALUE(0x0C, 10), /*!< adc2 periph reset */
|
||||
CRM_TMR1_PERIPH_RESET = MAKE_VALUE(0x0C, 11), /*!< tmr1 periph reset */
|
||||
CRM_SPI1_PERIPH_RESET = MAKE_VALUE(0x0C, 12), /*!< spi2 periph reset */
|
||||
CRM_TMR8_PERIPH_RESET = MAKE_VALUE(0x0C, 13), /*!< tmr8 periph reset */
|
||||
CRM_USART1_PERIPH_RESET = MAKE_VALUE(0x0C, 14), /*!< usart1 periph reset */
|
||||
CRM_TMR9_PERIPH_RESET = MAKE_VALUE(0x0C, 19), /*!< tmr9 periph reset */
|
||||
CRM_TMR10_PERIPH_RESET = MAKE_VALUE(0x0C, 20), /*!< tmr10 periph reset */
|
||||
CRM_TMR11_PERIPH_RESET = MAKE_VALUE(0x0C, 21), /*!< tmr11 periph reset */
|
||||
CRM_ACC_PERIPH_RESET = MAKE_VALUE(0x0C, 22), /*!< acc periph reset */
|
||||
/* apb1 periph */
|
||||
CRM_TMR2_PERIPH_RESET = MAKE_VALUE(0x10, 0), /*!< tmr2 periph reset */
|
||||
CRM_TMR3_PERIPH_RESET = MAKE_VALUE(0x10, 1), /*!< tmr3 periph reset */
|
||||
CRM_TMR4_PERIPH_RESET = MAKE_VALUE(0x10, 2), /*!< tmr4 periph reset */
|
||||
CRM_TMR5_PERIPH_RESET = MAKE_VALUE(0x10, 3), /*!< tmr5 periph reset */
|
||||
CRM_WWDT_PERIPH_RESET = MAKE_VALUE(0x10, 11), /*!< wwdt periph reset */
|
||||
CRM_SPI2_PERIPH_RESET = MAKE_VALUE(0x10, 14), /*!< spi2 periph reset */
|
||||
CRM_USART2_PERIPH_RESET = MAKE_VALUE(0x10, 17), /*!< usart2 periph reset */
|
||||
CRM_USART3_PERIPH_RESET = MAKE_VALUE(0x10, 18), /*!< usart3 periph reset */
|
||||
CRM_UART4_PERIPH_RESET = MAKE_VALUE(0x10, 19), /*!< uart4 periph reset */
|
||||
CRM_UART5_PERIPH_RESET = MAKE_VALUE(0x10, 20), /*!< uart5 periph reset */
|
||||
CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x10, 21), /*!< i2c1 periph reset */
|
||||
CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< i2c2 periph reset */
|
||||
CRM_USB_PERIPH_RESET = MAKE_VALUE(0x10, 23), /*!< usb periph reset */
|
||||
CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x10, 25), /*!< can1 periph reset */
|
||||
CRM_BPR_PERIPH_RESET = MAKE_VALUE(0x10, 27), /*!< bpr periph reset */
|
||||
CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28), /*!< pwc periph reset */
|
||||
CRM_CAN2_PERIPH_RESET = MAKE_VALUE(0x10, 31) /*!< can2 periph reset */
|
||||
|
||||
} crm_periph_reset_type;
|
||||
|
||||
/**
|
||||
* @brief crm periph clock in sleep mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/* ahb periph */
|
||||
CRM_SRAM_PERIPH_CLOCK_SLEEP_MODE = MAKE_VALUE(0x14, 2), /*!< sram sleep mode periph clock */
|
||||
CRM_FLASH_PERIPH_CLOCK_SLEEP_MODE = MAKE_VALUE(0x14, 4) /*!< flash sleep mode periph clock */
|
||||
} crm_periph_clock_sleepmd_type;
|
||||
|
||||
/**
|
||||
* @brief crm pll mult_x
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_PLL_MULT_2 = 0, /*!< pll multiplication factor 2 */
|
||||
CRM_PLL_MULT_3 = 1, /*!< pll multiplication factor 3 */
|
||||
CRM_PLL_MULT_4 = 2, /*!< pll multiplication factor 4 */
|
||||
CRM_PLL_MULT_5 = 3, /*!< pll multiplication factor 5 */
|
||||
CRM_PLL_MULT_6 = 4, /*!< pll multiplication factor 6 */
|
||||
CRM_PLL_MULT_7 = 5, /*!< pll multiplication factor 7 */
|
||||
CRM_PLL_MULT_8 = 6, /*!< pll multiplication factor 8 */
|
||||
CRM_PLL_MULT_9 = 7, /*!< pll multiplication factor 9 */
|
||||
CRM_PLL_MULT_10 = 8, /*!< pll multiplication factor 10 */
|
||||
CRM_PLL_MULT_11 = 9, /*!< pll multiplication factor 11 */
|
||||
CRM_PLL_MULT_12 = 10, /*!< pll multiplication factor 12 */
|
||||
CRM_PLL_MULT_13 = 11, /*!< pll multiplication factor 13 */
|
||||
CRM_PLL_MULT_14 = 12, /*!< pll multiplication factor 14 */
|
||||
CRM_PLL_MULT_15 = 13, /*!< pll multiplication factor 15 */
|
||||
CRM_PLL_MULT_16 = 15, /*!< pll multiplication factor 16 */
|
||||
CRM_PLL_MULT_17 = 16, /*!< pll multiplication factor 17 */
|
||||
CRM_PLL_MULT_18 = 17, /*!< pll multiplication factor 18 */
|
||||
CRM_PLL_MULT_19 = 18, /*!< pll multiplication factor 19 */
|
||||
CRM_PLL_MULT_20 = 19, /*!< pll multiplication factor 20 */
|
||||
CRM_PLL_MULT_21 = 20, /*!< pll multiplication factor 21 */
|
||||
CRM_PLL_MULT_22 = 21, /*!< pll multiplication factor 22 */
|
||||
CRM_PLL_MULT_23 = 22, /*!< pll multiplication factor 23 */
|
||||
CRM_PLL_MULT_24 = 23, /*!< pll multiplication factor 24 */
|
||||
CRM_PLL_MULT_25 = 24, /*!< pll multiplication factor 25 */
|
||||
CRM_PLL_MULT_26 = 25, /*!< pll multiplication factor 26 */
|
||||
CRM_PLL_MULT_27 = 26, /*!< pll multiplication factor 27 */
|
||||
CRM_PLL_MULT_28 = 27, /*!< pll multiplication factor 28 */
|
||||
CRM_PLL_MULT_29 = 28, /*!< pll multiplication factor 29 */
|
||||
CRM_PLL_MULT_30 = 29, /*!< pll multiplication factor 30 */
|
||||
CRM_PLL_MULT_31 = 30, /*!< pll multiplication factor 31 */
|
||||
CRM_PLL_MULT_32 = 31, /*!< pll multiplication factor 32 */
|
||||
CRM_PLL_MULT_33 = 32, /*!< pll multiplication factor 33 */
|
||||
CRM_PLL_MULT_34 = 33, /*!< pll multiplication factor 34 */
|
||||
CRM_PLL_MULT_35 = 34, /*!< pll multiplication factor 35 */
|
||||
CRM_PLL_MULT_36 = 35, /*!< pll multiplication factor 36 */
|
||||
CRM_PLL_MULT_37 = 36, /*!< pll multiplication factor 37 */
|
||||
CRM_PLL_MULT_38 = 37, /*!< pll multiplication factor 38 */
|
||||
CRM_PLL_MULT_39 = 38, /*!< pll multiplication factor 39 */
|
||||
CRM_PLL_MULT_40 = 39, /*!< pll multiplication factor 40 */
|
||||
CRM_PLL_MULT_41 = 40, /*!< pll multiplication factor 41 */
|
||||
CRM_PLL_MULT_42 = 41, /*!< pll multiplication factor 42 */
|
||||
CRM_PLL_MULT_43 = 42, /*!< pll multiplication factor 43 */
|
||||
CRM_PLL_MULT_44 = 43, /*!< pll multiplication factor 44 */
|
||||
CRM_PLL_MULT_45 = 44, /*!< pll multiplication factor 45 */
|
||||
CRM_PLL_MULT_46 = 45, /*!< pll multiplication factor 46 */
|
||||
CRM_PLL_MULT_47 = 46, /*!< pll multiplication factor 47 */
|
||||
CRM_PLL_MULT_48 = 47, /*!< pll multiplication factor 48 */
|
||||
CRM_PLL_MULT_49 = 48, /*!< pll multiplication factor 49 */
|
||||
CRM_PLL_MULT_50 = 49, /*!< pll multiplication factor 50 */
|
||||
CRM_PLL_MULT_51 = 50, /*!< pll multiplication factor 51 */
|
||||
CRM_PLL_MULT_52 = 51, /*!< pll multiplication factor 52 */
|
||||
CRM_PLL_MULT_53 = 52, /*!< pll multiplication factor 53 */
|
||||
CRM_PLL_MULT_54 = 53, /*!< pll multiplication factor 54 */
|
||||
CRM_PLL_MULT_55 = 54, /*!< pll multiplication factor 55 */
|
||||
CRM_PLL_MULT_56 = 55, /*!< pll multiplication factor 56 */
|
||||
CRM_PLL_MULT_57 = 56, /*!< pll multiplication factor 57 */
|
||||
CRM_PLL_MULT_58 = 57, /*!< pll multiplication factor 58 */
|
||||
CRM_PLL_MULT_59 = 58, /*!< pll multiplication factor 59 */
|
||||
CRM_PLL_MULT_60 = 59, /*!< pll multiplication factor 60 */
|
||||
CRM_PLL_MULT_61 = 60, /*!< pll multiplication factor 61 */
|
||||
CRM_PLL_MULT_62 = 61, /*!< pll multiplication factor 62 */
|
||||
CRM_PLL_MULT_63 = 62, /*!< pll multiplication factor 63 */
|
||||
CRM_PLL_MULT_64 = 63 /*!< pll multiplication factor 64 */
|
||||
} crm_pll_mult_type;
|
||||
|
||||
/**
|
||||
* @brief crm pll clock source
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_PLL_SOURCE_HICK = 0x00, /*!< high speed internal clock as pll reference clock source */
|
||||
CRM_PLL_SOURCE_HEXT = 0x01, /*!< high speed external crystal as pll reference clock source */
|
||||
CRM_PLL_SOURCE_HEXT_DIV = 0x02 /*!< high speed external crystal div as pll reference clock source */
|
||||
} crm_pll_clock_source_type;
|
||||
|
||||
/**
|
||||
* @brief crm pll clock output range
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_PLL_OUTPUT_RANGE_LE72MHZ = 0x00, /*!< pll clock output range less than or equal to 72mhz */
|
||||
CRM_PLL_OUTPUT_RANGE_GT72MHZ = 0x01 /*!< pll clock output range greater than 72mhz */
|
||||
} crm_pll_output_range_type;
|
||||
|
||||
/**
|
||||
* @brief crm clock source
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_CLOCK_SOURCE_HICK = 0x00, /*!< high speed internal clock */
|
||||
CRM_CLOCK_SOURCE_HEXT = 0x01, /*!< high speed external crystal */
|
||||
CRM_CLOCK_SOURCE_PLL = 0x02, /*!< phase locking loop */
|
||||
CRM_CLOCK_SOURCE_LEXT = 0x03, /*!< low speed external crystal */
|
||||
CRM_CLOCK_SOURCE_LICK = 0x04 /*!< low speed internal clock */
|
||||
} crm_clock_source_type;
|
||||
|
||||
/**
|
||||
* @brief crm ahb division
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_AHB_DIV_1 = 0x00, /*!< sclk div1 to ahbclk */
|
||||
CRM_AHB_DIV_2 = 0x08, /*!< sclk div2 to ahbclk */
|
||||
CRM_AHB_DIV_4 = 0x09, /*!< sclk div4 to ahbclk */
|
||||
CRM_AHB_DIV_8 = 0x0A, /*!< sclk div8 to ahbclk */
|
||||
CRM_AHB_DIV_16 = 0x0B, /*!< sclk div16 to ahbclk */
|
||||
CRM_AHB_DIV_64 = 0x0C, /*!< sclk div64 to ahbclk */
|
||||
CRM_AHB_DIV_128 = 0x0D, /*!< sclk div128 to ahbclk */
|
||||
CRM_AHB_DIV_256 = 0x0E, /*!< sclk div256 to ahbclk */
|
||||
CRM_AHB_DIV_512 = 0x0F /*!< sclk div512 to ahbclk */
|
||||
} crm_ahb_div_type;
|
||||
|
||||
/**
|
||||
* @brief crm apb1 division
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_APB1_DIV_1 = 0x00, /*!< ahbclk div1 to apb1clk */
|
||||
CRM_APB1_DIV_2 = 0x04, /*!< ahbclk div2 to apb1clk */
|
||||
CRM_APB1_DIV_4 = 0x05, /*!< ahbclk div4 to apb1clk */
|
||||
CRM_APB1_DIV_8 = 0x06, /*!< ahbclk div8 to apb1clk */
|
||||
CRM_APB1_DIV_16 = 0x07 /*!< ahbclk div16 to apb1clk */
|
||||
} crm_apb1_div_type;
|
||||
|
||||
/**
|
||||
* @brief crm apb2 division
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_APB2_DIV_1 = 0x00, /*!< ahbclk div1 to apb2clk */
|
||||
CRM_APB2_DIV_2 = 0x04, /*!< ahbclk div2 to apb2clk */
|
||||
CRM_APB2_DIV_4 = 0x05, /*!< ahbclk div4 to apb2clk */
|
||||
CRM_APB2_DIV_8 = 0x06, /*!< ahbclk div8 to apb2clk */
|
||||
CRM_APB2_DIV_16 = 0x07 /*!< ahbclk div16 to apb2clk */
|
||||
} crm_apb2_div_type;
|
||||
|
||||
/**
|
||||
* @brief crm adc division
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_ADC_DIV_2 = 0x00, /*!< apb2clk div2 to adcclk */
|
||||
CRM_ADC_DIV_4 = 0x01, /*!< apb2clk div4 to adcclk */
|
||||
CRM_ADC_DIV_6 = 0x02, /*!< apb2clk div6 to adcclk */
|
||||
CRM_ADC_DIV_8 = 0x03, /*!< apb2clk div8 to adcclk */
|
||||
CRM_ADC_DIV_12 = 0x05, /*!< apb2clk div12 to adcclk */
|
||||
CRM_ADC_DIV_16 = 0x07 /*!< apb2clk div16 to adcclk */
|
||||
} crm_adc_div_type;
|
||||
|
||||
/**
|
||||
* @brief crm usb division
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_USB_DIV_1_5 = 0x00, /*!< pllclk div1.5 to usbclk */
|
||||
CRM_USB_DIV_1 = 0x01, /*!< pllclk div1 to usbclk */
|
||||
CRM_USB_DIV_2_5 = 0x02, /*!< pllclk div2.5 to usbclk */
|
||||
CRM_USB_DIV_2 = 0x03, /*!< pllclk div2 to usbclk */
|
||||
CRM_USB_DIV_3_5 = 0x04, /*!< pllclk div3.5 to usbclk */
|
||||
CRM_USB_DIV_3 = 0x05, /*!< pllclk div3 to usbclk */
|
||||
CRM_USB_DIV_4 = 0x06 /*!< pllclk div4 to usbclk */
|
||||
} crm_usb_div_type;
|
||||
|
||||
/**
|
||||
* @brief crm rtc clock
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_RTC_CLOCK_NOCLK = 0x00, /*!< no clock as rtc clock source */
|
||||
CRM_RTC_CLOCK_LEXT = 0x01, /*!< low speed external crystal as rtc clock source */
|
||||
CRM_RTC_CLOCK_LICK = 0x02, /*!< low speed internal clock as rtc clock source */
|
||||
CRM_RTC_CLOCK_HEXT_DIV = 0x03 /*!< high speed external crystal div as rtc clock source */
|
||||
} crm_rtc_clock_type;
|
||||
|
||||
/**
|
||||
* @brief crm hick 48mhz division
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_HICK48_DIV6 = 0x00, /*!< high speed internal clock (48 mhz) div6 */
|
||||
CRM_HICK48_NODIV = 0x01 /*!< high speed internal clock (48 mhz) no div */
|
||||
} crm_hick_div_6_type;
|
||||
|
||||
/**
|
||||
* @brief crm sclk select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_SCLK_HICK = 0x00, /*!< select high speed internal clock as sclk */
|
||||
CRM_SCLK_HEXT = 0x01, /*!< select high speed external crystal as sclk */
|
||||
CRM_SCLK_PLL = 0x02 /*!< select phase locking loop clock as sclk */
|
||||
} crm_sclk_type;
|
||||
|
||||
/**
|
||||
* @brief crm clkout select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_CLKOUT_NOCLK = 0x00, /*!< output no clock to clkout pin */
|
||||
CRM_CLKOUT_LICK = 0x02, /*!< output low speed internal clock to clkout pin */
|
||||
CRM_CLKOUT_LEXT = 0x03, /*!< output low speed external crystal to clkout pin */
|
||||
CRM_CLKOUT_SCLK = 0x04, /*!< output system clock to clkout pin */
|
||||
CRM_CLKOUT_HICK = 0x05, /*!< output high speed internal clock to clkout pin */
|
||||
CRM_CLKOUT_HEXT = 0x06, /*!< output high speed external crystal to clkout pin */
|
||||
CRM_CLKOUT_PLL_DIV_2 = 0x07, /*!< output phase locking loop clock div2 to clkout pin */
|
||||
CRM_CLKOUT_PLL_DIV_4 = 0x0C, /*!< output phase locking loop clock div4 to clkout pin */
|
||||
CRM_CLKOUT_USB = 0x0D, /*!< output usbclk to clkout pin */
|
||||
CRM_CLKOUT_ADC = 0x0E /*!< output adcclk to clkout pin */
|
||||
} crm_clkout_select_type;
|
||||
|
||||
/**
|
||||
* @brief crm clkout division
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_CLKOUT_DIV_1 = 0x00, /*!< clkout div1 */
|
||||
CRM_CLKOUT_DIV_2 = 0x08, /*!< clkout div2 */
|
||||
CRM_CLKOUT_DIV_4 = 0x09, /*!< clkout div4 */
|
||||
CRM_CLKOUT_DIV_8 = 0x0A, /*!< clkout div8 */
|
||||
CRM_CLKOUT_DIV_16 = 0x0B, /*!< clkout div16 */
|
||||
CRM_CLKOUT_DIV_64 = 0x0C, /*!< clkout div64 */
|
||||
CRM_CLKOUT_DIV_128 = 0x0D, /*!< clkout div128 */
|
||||
CRM_CLKOUT_DIV_256 = 0x0E, /*!< clkout div256 */
|
||||
CRM_CLKOUT_DIV_512 = 0x0F /*!< clkout div512 */
|
||||
} crm_clkout_div_type;
|
||||
|
||||
/**
|
||||
* @brief crm auto step mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_AUTO_STEP_MODE_DISABLE = 0x00, /*!< disable auto step mode */
|
||||
CRM_AUTO_STEP_MODE_ENABLE = 0x03 /*!< enable auto step mode */
|
||||
} crm_auto_step_mode_type;
|
||||
|
||||
/**
|
||||
* @brief crm usbdev interrupt remap
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_USB_INT19_INT20 = 0x00, /*!< usb high and low priority irq numer use 19 and 20 */
|
||||
CRM_USB_INT73_INT74 = 0x01 /*!< usb high and low priority irq numer use 73 and 74 */
|
||||
} crm_usb_int_map_type;
|
||||
|
||||
/**
|
||||
* @brief crm usb 48 mhz clock source select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_USB_CLOCK_SOURCE_PLL = 0x00, /*!< select phase locking loop clock as usb clock source */
|
||||
CRM_USB_CLOCK_SOURCE_HICK = 0x01 /*!< select high speed internal clock as usb clock source */
|
||||
} crm_usb_clock_source_type;
|
||||
|
||||
/**
|
||||
* @brief crm hick as system clock frequency select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRM_HICK_SCLK_8MHZ = 0x00, /*!< fixed 8 mhz when hick is selected as sclk */
|
||||
CRM_HICK_SCLK_48MHZ = 0x01 /*!< 8 mhz or 48 mhz depend on hickdiv when hick is selected as sclk */
|
||||
} crm_hick_sclk_frequency_type;
|
||||
|
||||
/**
|
||||
* @brief crm clocks freqency structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t sclk_freq; /*!< system clock frequency */
|
||||
uint32_t ahb_freq; /*!< ahb bus clock frequency */
|
||||
uint32_t apb2_freq; /*!< apb2 bus clock frequency */
|
||||
uint32_t apb1_freq; /*!< apb1 bus clock frequency */
|
||||
uint32_t adc_freq; /*!< adc clock frequency */
|
||||
} crm_clocks_freq_type;
|
||||
|
||||
/**
|
||||
* @brief type define crm register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief crm ctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t hicken : 1; /* [0] */
|
||||
__IO uint32_t hickstbl : 1; /* [1] */
|
||||
__IO uint32_t hicktrim : 6; /* [7:2] */
|
||||
__IO uint32_t hickcal : 8; /* [15:8] */
|
||||
__IO uint32_t hexten : 1; /* [16] */
|
||||
__IO uint32_t hextstbl : 1; /* [17] */
|
||||
__IO uint32_t hextbyps : 1; /* [18] */
|
||||
__IO uint32_t cfden : 1; /* [19] */
|
||||
__IO uint32_t reserved1 : 4; /* [23:20] */
|
||||
__IO uint32_t pllen : 1; /* [24] */
|
||||
__IO uint32_t pllstbl : 1; /* [25] */
|
||||
__IO uint32_t reserved2 : 6; /* [31:26] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm cfg register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t sclksel : 2; /* [1:0] */
|
||||
__IO uint32_t sclksts : 2; /* [3:2] */
|
||||
__IO uint32_t ahbdiv : 4; /* [7:4] */
|
||||
__IO uint32_t apb1div : 3; /* [10:8] */
|
||||
__IO uint32_t apb2div : 3; /* [13:11] */
|
||||
__IO uint32_t adcdiv_l : 2; /* [15:14] */
|
||||
__IO uint32_t pllrcs : 1; /* [16] */
|
||||
__IO uint32_t pllhextdiv : 1; /* [17] */
|
||||
__IO uint32_t pllmult_l : 4; /* [21:18] */
|
||||
__IO uint32_t usbdiv_l : 2; /* [23:22] */
|
||||
__IO uint32_t clkout_sel : 3; /* [26:24] */
|
||||
__IO uint32_t usbdiv_h : 1; /* [27] */
|
||||
__IO uint32_t adcdiv_h : 1; /* [28] */
|
||||
__IO uint32_t pllmult_h : 2; /* [30:29] */
|
||||
__IO uint32_t pllrange : 1; /* [31] */
|
||||
} cfg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm clkint register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clkint;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t lickstblf : 1; /* [0] */
|
||||
__IO uint32_t lextstblf : 1; /* [1] */
|
||||
__IO uint32_t hickstblf : 1; /* [2] */
|
||||
__IO uint32_t hextstblf : 1; /* [3] */
|
||||
__IO uint32_t pllstblf : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 2; /* [6:5] */
|
||||
__IO uint32_t cfdf : 1; /* [7] */
|
||||
__IO uint32_t lickstblien : 1; /* [8] */
|
||||
__IO uint32_t lextstblien : 1; /* [9] */
|
||||
__IO uint32_t hickstblien : 1; /* [10] */
|
||||
__IO uint32_t hextstblien : 1; /* [11] */
|
||||
__IO uint32_t pllstblien : 1; /* [12] */
|
||||
__IO uint32_t reserved2 : 3; /* [15:13] */
|
||||
__IO uint32_t lickstblfc : 1; /* [16] */
|
||||
__IO uint32_t lextstblfc : 1; /* [17] */
|
||||
__IO uint32_t hickstblfc : 1; /* [18] */
|
||||
__IO uint32_t hextstblfc : 1; /* [19] */
|
||||
__IO uint32_t pllstblfc : 1; /* [20] */
|
||||
__IO uint32_t reserved3 : 2; /* [22:21] */
|
||||
__IO uint32_t cfdfc : 1; /* [23] */
|
||||
__IO uint32_t reserved4 : 8; /* [31:24] */
|
||||
} clkint_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm apb2rst register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t apb2rst;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iomuxrst : 1; /* [0] */
|
||||
__IO uint32_t exintrst : 1; /* [1] */
|
||||
__IO uint32_t gpioarst : 1; /* [2] */
|
||||
__IO uint32_t gpiobrst : 1; /* [3] */
|
||||
__IO uint32_t gpiocrst : 1; /* [4] */
|
||||
__IO uint32_t gpiodrst : 1; /* [5] */
|
||||
__IO uint32_t reserved1 : 1; /* [6] */
|
||||
__IO uint32_t gpioerst : 1; /* [7] */
|
||||
__IO uint32_t reserved2 : 1; /* [8] */
|
||||
__IO uint32_t adc1rst : 1; /* [9] */
|
||||
__IO uint32_t adc2rst : 1; /* [10] */
|
||||
__IO uint32_t tmr1rst : 1; /* [11] */
|
||||
__IO uint32_t spi1rst : 1; /* [12] */
|
||||
__IO uint32_t tmr8rst : 1; /* [13] */
|
||||
__IO uint32_t usart1rst : 1; /* [14] */
|
||||
__IO uint32_t reserved3 : 4; /* [18:15] */
|
||||
__IO uint32_t tmr9rst : 1; /* [19] */
|
||||
__IO uint32_t tmr10rst : 1; /* [20] */
|
||||
__IO uint32_t tmr11rst : 1; /* [21] */
|
||||
__IO uint32_t accrst : 1; /* [22] */
|
||||
__IO uint32_t reserved4 : 9; /* [31:23] */
|
||||
} apb2rst_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm apb1rst register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t apb1rst;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmr2rst : 1; /* [0] */
|
||||
__IO uint32_t tmr3rst : 1; /* [1] */
|
||||
__IO uint32_t tmr4rst : 1; /* [2] */
|
||||
__IO uint32_t tmr5rst : 1; /* [3] */
|
||||
__IO uint32_t reserved1 : 7; /* [10:4] */
|
||||
__IO uint32_t wwdtrst : 1; /* [11] */
|
||||
__IO uint32_t reserved2 : 2; /* [13:12] */
|
||||
__IO uint32_t spi2rst : 1; /* [14] */
|
||||
__IO uint32_t reserved3 : 2; /* [16:15] */
|
||||
__IO uint32_t usart2rst : 1; /* [17] */
|
||||
__IO uint32_t usart3rst : 1; /* [18] */
|
||||
__IO uint32_t uart4rst : 1; /* [19] */
|
||||
__IO uint32_t uart5rst : 1; /* [20] */
|
||||
__IO uint32_t i2c1rst : 1; /* [21] */
|
||||
__IO uint32_t i2c2rst : 1; /* [22] */
|
||||
__IO uint32_t usbrst : 1; /* [23] */
|
||||
__IO uint32_t reserved4 : 1; /* [24] */
|
||||
__IO uint32_t can1rst : 1; /* [25] */
|
||||
__IO uint32_t reserved5 : 1; /* [26] */
|
||||
__IO uint32_t bprrst : 1; /* [27] */
|
||||
__IO uint32_t pwcrst : 1; /* [28] */
|
||||
__IO uint32_t reserved6 : 2; /* [31:30] */
|
||||
__IO uint32_t can2rst : 1; /* [31] */
|
||||
} apb1rst_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm ahben register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ahben;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dma1en : 1; /* [0] */
|
||||
__IO uint32_t dma2en : 1; /* [1] */
|
||||
__IO uint32_t sramen : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 1; /* [3] */
|
||||
__IO uint32_t flashen : 1; /* [4] */
|
||||
__IO uint32_t reserved2 : 1; /* [5] */
|
||||
__IO uint32_t crcen : 1; /* [6] */
|
||||
__IO uint32_t reserved3 : 3; /* [9:7] */
|
||||
__IO uint32_t sdio1en : 1; /* [10] */
|
||||
__IO uint32_t reserved5 : 21;/* [31:11] */
|
||||
} ahben_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm apb2en register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t apb2en;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iomuxen : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 1; /* [1] */
|
||||
__IO uint32_t gpioaen : 1; /* [2] */
|
||||
__IO uint32_t gpioben : 1; /* [3] */
|
||||
__IO uint32_t gpiocen : 1; /* [4] */
|
||||
__IO uint32_t gpioden : 1; /* [5] */
|
||||
__IO uint32_t reserved2 : 1; /* [6] */
|
||||
__IO uint32_t gpiofen : 1; /* [7] */
|
||||
__IO uint32_t reserved3 : 1; /* [8] */
|
||||
__IO uint32_t adc1en : 1; /* [9] */
|
||||
__IO uint32_t adc2en : 1; /* [10] */
|
||||
__IO uint32_t tmr1en : 1; /* [11] */
|
||||
__IO uint32_t spi1en : 1; /* [12] */
|
||||
__IO uint32_t tmr8en : 1; /* [13] */
|
||||
__IO uint32_t usart1en : 1; /* [14] */
|
||||
__IO uint32_t reserved4 : 4; /* [18:15] */
|
||||
__IO uint32_t tmr9en : 1; /* [19] */
|
||||
__IO uint32_t tmr10en : 1; /* [20] */
|
||||
__IO uint32_t tmr11en : 1; /* [21] */
|
||||
__IO uint32_t accen : 1; /* [22] */
|
||||
__IO uint32_t reserved5 : 9; /* [31:23] */
|
||||
} apb2en_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm apb1en register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t apb1en;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmr2en : 1; /* [0] */
|
||||
__IO uint32_t tmr3en : 1; /* [1] */
|
||||
__IO uint32_t tmr4en : 1; /* [2] */
|
||||
__IO uint32_t tmr5en : 1; /* [3] */
|
||||
__IO uint32_t reserved1 : 7; /* [10:4] */
|
||||
__IO uint32_t wwdten : 1; /* [11] */
|
||||
__IO uint32_t reserved2 : 2; /* [13:12] */
|
||||
__IO uint32_t spi2en : 1; /* [14] */
|
||||
__IO uint32_t reserved3 : 2; /* [16:15] */
|
||||
__IO uint32_t usart2en : 1; /* [17] */
|
||||
__IO uint32_t usart3en : 1; /* [18] */
|
||||
__IO uint32_t uart4en : 1; /* [19] */
|
||||
__IO uint32_t uart5en : 1; /* [20] */
|
||||
__IO uint32_t i2c1en : 1; /* [21] */
|
||||
__IO uint32_t i2c2en : 1; /* [22] */
|
||||
__IO uint32_t usben : 1; /* [23] */
|
||||
__IO uint32_t reserved4 : 1; /* [24] */
|
||||
__IO uint32_t can1en : 1; /* [25] */
|
||||
__IO uint32_t reserved5 : 1; /* [26] */
|
||||
__IO uint32_t bpren : 1; /* [27] */
|
||||
__IO uint32_t pwcen : 1; /* [28] */
|
||||
__IO uint32_t reserved6 : 2; /* [30:29] */
|
||||
__IO uint32_t can2en : 1; /* [31] */
|
||||
} apb1en_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm bpdc register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t bpdc;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t lexten : 1; /* [0] */
|
||||
__IO uint32_t lextstbl : 1; /* [1] */
|
||||
__IO uint32_t lextbyps : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 5; /* [7:3] */
|
||||
__IO uint32_t rtcsel : 2; /* [9:8] */
|
||||
__IO uint32_t reserved2 : 5; /* [14:10] */
|
||||
__IO uint32_t rtcen : 1; /* [15] */
|
||||
__IO uint32_t bpdrst : 1; /* [16] */
|
||||
__IO uint32_t reserved3 : 15;/* [31:17] */
|
||||
} bpdc_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm ctrlsts register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrlsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t licken : 1; /* [0] */
|
||||
__IO uint32_t lickstbl : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 22;/* [23:2] */
|
||||
__IO uint32_t rstfc : 1; /* [24] */
|
||||
__IO uint32_t reserved2 : 1; /* [25] */
|
||||
__IO uint32_t nrstf : 1; /* [26] */
|
||||
__IO uint32_t porrstf : 1; /* [27] */
|
||||
__IO uint32_t swrstf : 1; /* [28] */
|
||||
__IO uint32_t wdtrstf : 1; /* [29] */
|
||||
__IO uint32_t wwdtrstf : 1; /* [30] */
|
||||
__IO uint32_t lprstf : 1; /* [31] */
|
||||
} ctrlsts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm reserved1 register, offset:0x28~0x2C
|
||||
*/
|
||||
__IO uint32_t reserved1[2];
|
||||
|
||||
/**
|
||||
* @brief crm misc1 register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t misc1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t hickcal_key : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 8; /* [15:8] */
|
||||
__IO uint32_t clkout_sel : 1; /* [16] */
|
||||
__IO uint32_t reserved2 : 7; /* [23:17] */
|
||||
__IO uint32_t usbbufs : 1; /* [24] */
|
||||
__IO uint32_t hickdiv : 1; /* [25] */
|
||||
__IO uint32_t reserved3 : 2; /* [27:26] */
|
||||
__IO uint32_t clkoutdiv : 4; /* [31:28] */
|
||||
} misc1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm reserved2 register, offset:0x4C~0x34
|
||||
*/
|
||||
__IO uint32_t reserved2[7];
|
||||
|
||||
/**
|
||||
* @brief crm misc2 register, offset:0x50
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t misc2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 16;/* [15:0] */
|
||||
__IO uint32_t clk_to_tmr : 1; /* [16] */
|
||||
__IO uint32_t reserved2 : 15;/* [31:17] */
|
||||
} misc2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm misc3 register, offset:0x54
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t misc3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 4; /* [3:0] */
|
||||
__IO uint32_t auto_step_en : 2; /* [5:4] */
|
||||
__IO uint32_t reserved2 : 2; /* [7:6] */
|
||||
__IO uint32_t hick_to_usb : 1; /* [8] */
|
||||
__IO uint32_t hick_to_sclk : 1; /* [9] */
|
||||
__IO uint32_t reserved3 : 22;/* [31:10] */
|
||||
} misc3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm reserved3 register, offset:0x58
|
||||
*/
|
||||
__IO uint32_t reserved3;
|
||||
|
||||
/**
|
||||
* @brief crm intmap register, offset:0x5C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t intmap;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t usbintmap : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 31;/* [31:1] */
|
||||
} intmap_bit;
|
||||
};
|
||||
|
||||
} crm_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define CRM ((crm_type *) CRM_BASE)
|
||||
|
||||
/** @defgroup CRM_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void crm_reset(void);
|
||||
void crm_lext_bypass(confirm_state new_state);
|
||||
void crm_hext_bypass(confirm_state new_state);
|
||||
flag_status crm_flag_get(uint32_t flag);
|
||||
flag_status crm_interrupt_flag_get(uint32_t flag);
|
||||
error_status crm_hext_stable_wait(void);
|
||||
void crm_hick_clock_trimming_set(uint8_t trim_value);
|
||||
void crm_hick_clock_calibration_set(uint8_t cali_value);
|
||||
void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state);
|
||||
void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state);
|
||||
void crm_periph_sleep_mode_clock_enable(crm_periph_clock_sleepmd_type value, confirm_state new_state);
|
||||
void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state);
|
||||
void crm_flag_clear(uint32_t flag);
|
||||
void crm_rtc_clock_select(crm_rtc_clock_type value);
|
||||
void crm_rtc_clock_enable(confirm_state new_state);
|
||||
void crm_ahb_div_set(crm_ahb_div_type value);
|
||||
void crm_apb1_div_set(crm_apb1_div_type value);
|
||||
void crm_apb2_div_set(crm_apb2_div_type value);
|
||||
void crm_adc_clock_div_set(crm_adc_div_type div_value);
|
||||
void crm_usb_clock_div_set(crm_usb_div_type div_value);
|
||||
void crm_clock_failure_detection_enable(confirm_state new_state);
|
||||
void crm_battery_powered_domain_reset(confirm_state new_state);
|
||||
void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mult_value, crm_pll_output_range_type pll_range);
|
||||
void crm_sysclk_switch(crm_sclk_type value);
|
||||
crm_sclk_type crm_sysclk_switch_status_get(void);
|
||||
void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct);
|
||||
void crm_clock_out_set(crm_clkout_select_type clkout);
|
||||
void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state);
|
||||
void crm_auto_step_mode_enable(confirm_state new_state);
|
||||
void crm_usb_interrupt_remapping_set(crm_usb_int_map_type int_remap);
|
||||
void crm_hick_divider_select(crm_hick_div_6_type value);
|
||||
void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value);
|
||||
void crm_usb_clock_source_select(crm_usb_clock_source_type value);
|
||||
void crm_clkout_to_tmr10_enable(confirm_state new_state);
|
||||
void crm_clkout_div_set(crm_clkout_div_type clkout_div);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
159
libraries/drivers/inc/at32f413_debug.h
Normal file
159
libraries/drivers/inc/at32f413_debug.h
Normal file
@@ -0,0 +1,159 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_debug.h
|
||||
* @brief at32f413 debug header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F413_DEBUG_H
|
||||
#define __AT32F413_DEBUG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f413.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DEBUG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DEBUG_mode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DEBUG_SLEEP 0x00000001 /*!< debug sleep mode */
|
||||
#define DEBUG_DEEPSLEEP 0x00000002 /*!< debug deepsleep mode */
|
||||
#define DEBUG_STANDBY 0x00000004 /*!< debug standby mode */
|
||||
#define DEBUG_WDT_PAUSE 0x00000100 /*!< debug watchdog timer pause */
|
||||
#define DEBUG_WWDT_PAUSE 0x00000200 /*!< debug window watchdog timer pause */
|
||||
#define DEBUG_TMR1_PAUSE 0x00000400 /*!< debug timer1 pause */
|
||||
#define DEBUG_TMR2_PAUSE 0x00000800 /*!< debug timer2 pause */
|
||||
#define DEBUG_TMR3_PAUSE 0x00001000 /*!< debug timer3 pause */
|
||||
#define DEBUG_TMR4_PAUSE 0x00002000 /*!< debug timer4 pause */
|
||||
#define DEBUG_CAN1_PAUSE 0x00004000 /*!< debug can1 pause */
|
||||
#define DEBUG_I2C1_SMBUS_TIMEOUT 0x00008000 /*!< debug i2c1 smbus timeout */
|
||||
#define DEBUG_I2C2_SMBUS_TIMEOUT 0x00010000 /*!< debug i2c2 smbus timeout */
|
||||
#define DEBUG_TMR8_PAUSE 0x00020000 /*!< debug timer8 pause */
|
||||
#define DEBUG_TMR5_PAUSE 0x00040000 /*!< debug timer5 pause */
|
||||
#define DEBUG_CAN2_PAUSE 0x00200000 /*!< debug can2 pause */
|
||||
#define DEBUG_TMR9_PAUSE 0x10000000 /*!< debug timer9 pause */
|
||||
#define DEBUG_TMR10_PAUSE 0x20000000 /*!< debug timer10 pause */
|
||||
#define DEBUG_TMR11_PAUSE 0x40000000 /*!< debug timer11 pause */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DEBUG_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief type define debug register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief debug idcode register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pid;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pid : 32;/* [31:0] */
|
||||
} idcode_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief debug ctrl register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t sleep_debug : 1;/* [0] */
|
||||
__IO uint32_t deepsleep_debug : 1;/* [1] */
|
||||
__IO uint32_t standby_debug : 1;/* [2] */
|
||||
__IO uint32_t reserved1 : 2;/* [4:3] */
|
||||
__IO uint32_t trace_ioen : 1;/* [5] */
|
||||
__IO uint32_t trace_mode : 2;/* [7:6] */
|
||||
__IO uint32_t wdt_pause : 1;/* [8] */
|
||||
__IO uint32_t wwdt_pause : 1;/* [9] */
|
||||
__IO uint32_t tmr1_pause : 1;/* [10] */
|
||||
__IO uint32_t tmr2_pause : 1;/* [11] */
|
||||
__IO uint32_t tmr3_pause : 1;/* [12] */
|
||||
__IO uint32_t tmr4_pause : 1;/* [13] */
|
||||
__IO uint32_t can1_pause : 1;/* [14] */
|
||||
__IO uint32_t i2c1_smbus_timeout : 1;/* [15] */
|
||||
__IO uint32_t i2c2_smbus_timeout : 1;/* [16] */
|
||||
__IO uint32_t tmr8_pause : 1;/* [17] */
|
||||
__IO uint32_t tmr5_pause : 1;/* [18] */
|
||||
__IO uint32_t reserved2 : 2;/* [20:19] */
|
||||
__IO uint32_t can2_pause : 1;/* [21] */
|
||||
__IO uint32_t reserved3 : 6;/* [27:22] */
|
||||
__IO uint32_t tmr9_pause : 1;/* [28] */
|
||||
__IO uint32_t tmr10_pause : 1;/* [29] */
|
||||
__IO uint32_t tmr11_pause : 1;/* [30] */
|
||||
__IO uint32_t reserved4 : 1;/* [31] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
} debug_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define DEBUGMCU ((debug_type *) DEBUG_BASE)
|
||||
|
||||
/** @defgroup DEBUG_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t debug_device_id_get(void);
|
||||
void debug_periph_mode_set(uint32_t periph_debug_mode, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
69
libraries/drivers/inc/at32f413_def.h
Normal file
69
libraries/drivers/inc/at32f413_def.h
Normal file
@@ -0,0 +1,69 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_def.h
|
||||
* @brief at32f413 macros header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F413_DEF_H
|
||||
#define __AT32F413_DEF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* gnu compiler */
|
||||
#if defined (__GNUC__)
|
||||
#ifndef ALIGNED_HEAD
|
||||
#define ALIGNED_HEAD
|
||||
#endif
|
||||
#ifndef ALIGNED_TAIL
|
||||
#define ALIGNED_TAIL __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* arm compiler */
|
||||
#if defined (__CC_ARM)
|
||||
#ifndef ALIGNED_HEAD
|
||||
#define ALIGNED_HEAD __align(4)
|
||||
#endif
|
||||
#ifndef ALIGNED_TAIL
|
||||
#define ALIGNED_TAIL
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* iar compiler */
|
||||
#if defined (__ICCARM__)
|
||||
#ifndef ALIGNED_HEAD
|
||||
#define ALIGNED_HEAD
|
||||
#endif
|
||||
#ifndef ALIGNED_TAIL
|
||||
#define ALIGNED_TAIL
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
228
libraries/drivers/inc/at32f413_exint.h
Normal file
228
libraries/drivers/inc/at32f413_exint.h
Normal file
@@ -0,0 +1,228 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_exint.h
|
||||
* @brief at32f413 exint header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F413_EXINT_H
|
||||
#define __AT32F413_EXINT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f413.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXINT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXINT_lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXINT_LINE_NONE ((uint32_t)0x000000)
|
||||
#define EXINT_LINE_0 ((uint32_t)0x000001) /*!< external interrupt line 0 */
|
||||
#define EXINT_LINE_1 ((uint32_t)0x000002) /*!< external interrupt line 1 */
|
||||
#define EXINT_LINE_2 ((uint32_t)0x000004) /*!< external interrupt line 2 */
|
||||
#define EXINT_LINE_3 ((uint32_t)0x000008) /*!< external interrupt line 3 */
|
||||
#define EXINT_LINE_4 ((uint32_t)0x000010) /*!< external interrupt line 4 */
|
||||
#define EXINT_LINE_5 ((uint32_t)0x000020) /*!< external interrupt line 5 */
|
||||
#define EXINT_LINE_6 ((uint32_t)0x000040) /*!< external interrupt line 6 */
|
||||
#define EXINT_LINE_7 ((uint32_t)0x000080) /*!< external interrupt line 7 */
|
||||
#define EXINT_LINE_8 ((uint32_t)0x000100) /*!< external interrupt line 8 */
|
||||
#define EXINT_LINE_9 ((uint32_t)0x000200) /*!< external interrupt line 9 */
|
||||
#define EXINT_LINE_10 ((uint32_t)0x000400) /*!< external interrupt line 10 */
|
||||
#define EXINT_LINE_11 ((uint32_t)0x000800) /*!< external interrupt line 11 */
|
||||
#define EXINT_LINE_12 ((uint32_t)0x001000) /*!< external interrupt line 12 */
|
||||
#define EXINT_LINE_13 ((uint32_t)0x002000) /*!< external interrupt line 13 */
|
||||
#define EXINT_LINE_14 ((uint32_t)0x004000) /*!< external interrupt line 14 */
|
||||
#define EXINT_LINE_15 ((uint32_t)0x008000) /*!< external interrupt line 15 */
|
||||
#define EXINT_LINE_16 ((uint32_t)0x010000) /*!< external interrupt line 16 connected to the pvm output */
|
||||
#define EXINT_LINE_17 ((uint32_t)0x020000) /*!< external interrupt line 17 connected to the rtc alarm event */
|
||||
#define EXINT_LINE_18 ((uint32_t)0x040000) /*!< external interrupt line 18 connected to the usb fs wakeup from suspend event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXINT_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief exint line mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXINT_LINE_INTERRUPUT = 0x00, /*!< external interrupt line interrupt mode */
|
||||
EXINT_LINE_EVENT = 0x01 /*!< external interrupt line event mode */
|
||||
} exint_line_mode_type;
|
||||
|
||||
/**
|
||||
* @brief exint polarity configuration type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXINT_TRIGGER_RISING_EDGE = 0x00, /*!< external interrupt line rising trigger mode */
|
||||
EXINT_TRIGGER_FALLING_EDGE = 0x01, /*!< external interrupt line falling trigger mode */
|
||||
EXINT_TRIGGER_BOTH_EDGE = 0x02 /*!< external interrupt line both rising and falling trigger mode */
|
||||
} exint_polarity_config_type;
|
||||
|
||||
/**
|
||||
* @brief exint init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
exint_line_mode_type line_mode; /*!< choose mode event or interrupt mode */
|
||||
uint32_t line_select; /*!< select the exint line, availiable for single line or multiple lines */
|
||||
exint_polarity_config_type line_polarity; /*!< select the tregger polarity, with rising edge, falling edge or both edge */
|
||||
confirm_state line_enable; /*!< enable or disable exint */
|
||||
} exint_init_type;
|
||||
|
||||
/**
|
||||
* @brief type define exint register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief exint inten register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t inten;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t intenx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9;/* [31:23] */
|
||||
} inten_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint evten register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t evten;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t evtenx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9;/* [31:23] */
|
||||
} evten_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint polcfg1 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t polcfg1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rpx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9;/* [31:23] */
|
||||
} polcfg1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint polcfg2 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t polcfg2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fpx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9;/* [31:23] */
|
||||
} polcfg2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint swtrg register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t swtrg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t swtx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9;/* [31:23] */
|
||||
} swtrg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint intsts register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t intsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t linex : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9;/* [31:23] */
|
||||
} intsts_bit;
|
||||
};
|
||||
} exint_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define EXINT ((exint_type *) EXINT_BASE)
|
||||
|
||||
/** @defgroup EXINT_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void exint_reset(void);
|
||||
void exint_default_para_init(exint_init_type *exint_struct);
|
||||
void exint_init(exint_init_type *exint_struct);
|
||||
void exint_flag_clear(uint32_t exint_line);
|
||||
flag_status exint_flag_get(uint32_t exint_line);
|
||||
flag_status exint_interrupt_flag_get(uint32_t exint_line);
|
||||
void exint_software_interrupt_event_generate(uint32_t exint_line);
|
||||
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state);
|
||||
void exint_event_enable(uint32_t exint_line, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
623
libraries/drivers/inc/at32f413_flash.h
Normal file
623
libraries/drivers/inc/at32f413_flash.h
Normal file
@@ -0,0 +1,623 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_flash.h
|
||||
* @brief at32f413 flash header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F413_FLASH_H
|
||||
#define __AT32F413_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f413.h"
|
||||
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_unlock_keys
|
||||
* @brief flash unlock keys
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_UNLOCK_KEY1 ((uint32_t)0x45670123) /*!< flash operation unlock order key1 */
|
||||
#define FLASH_UNLOCK_KEY2 ((uint32_t)0xCDEF89AB) /*!< flash operation unlock order key2 */
|
||||
#define FAP_RELIEVE_KEY ((uint16_t)0x00A5) /*!< flash fap relieve key val */
|
||||
#define SLIB_UNLOCK_KEY ((uint32_t)0xA35F6D24) /*!< flash slib operation unlock order key */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_spim_address
|
||||
* @brief flash spim address
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_SPIM_START_ADDR ((uint32_t)0x08400000) /*!< flash start address of spim */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_flags
|
||||
* @brief flash flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_OBF_FLAG ((uint32_t)0x00000001) /*!< flash bank1 operate busy flag */
|
||||
#define FLASH_ODF_FLAG ((uint32_t)0x00000020) /*!< flash bank1 operate done flag */
|
||||
#define FLASH_PRGMERR_FLAG ((uint32_t)0x00000004) /*!< flash bank1 program error flag */
|
||||
#define FLASH_EPPERR_FLAG ((uint32_t)0x00000010) /*!< flash bank1 erase/program protection error flag */
|
||||
#define FLASH_SPIM_OBF_FLAG ((uint32_t)0x20000001) /*!< flash spim operate busy flag */
|
||||
#define FLASH_SPIM_ODF_FLAG ((uint32_t)0x20000020) /*!< flash spim operate done flag */
|
||||
#define FLASH_SPIM_PRGMERR_FLAG ((uint32_t)0x20000004) /*!< flash spim program error flag */
|
||||
#define FLASH_SPIM_EPPERR_FLAG ((uint32_t)0x20000010) /*!< flash spim erase/program protection error flag */
|
||||
#define FLASH_USDERR_FLAG ((uint32_t)0x40000001) /*!< flash user system data error flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_interrupts
|
||||
* @brief flash interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_ERR_INT ((uint32_t)0x00000001) /*!< flash bank1 error interrupt */
|
||||
#define FLASH_ODF_INT ((uint32_t)0x00000002) /*!< flash bank1 operate done interrupt */
|
||||
#define FLASH_SPIM_ERR_INT ((uint32_t)0x00000010) /*!< flash spim error interrupt */
|
||||
#define FLASH_SPIM_ODF_INT ((uint32_t)0x00000020) /*!< flash spim operate done interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_slib_mask
|
||||
* @brief flash slib mask
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_SLIB_START_SECTOR ((uint32_t)0x000007FF) /*!< flash slib start sector */
|
||||
#define FLASH_SLIB_DATA_START_SECTOR ((uint32_t)0x003FF800) /*!< flash slib d-bus area start sector */
|
||||
#define FLASH_SLIB_END_SECTOR ((uint32_t)0xFFC00000) /*!< flash slib end sector */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_user_system_data
|
||||
* @brief flash user system data
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USD_WDT_ATO_DISABLE ((uint16_t)0x0001) /*!< wdt auto start disabled */
|
||||
#define USD_WDT_ATO_ENABLE ((uint16_t)0x0000) /*!< wdt auto start enabled */
|
||||
|
||||
#define USD_DEPSLP_NO_RST ((uint16_t)0x0002) /*!< no reset generated when entering in deepsleep */
|
||||
#define USD_DEPSLP_RST ((uint16_t)0x0000) /*!< reset generated when entering in deepsleep */
|
||||
|
||||
#define USD_STDBY_NO_RST ((uint16_t)0x0004) /*!< no reset generated when entering in standby */
|
||||
#define USD_STDBY_RST ((uint16_t)0x0000) /*!< reset generated when entering in standby */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_timeout_definition
|
||||
* @brief flash timeout definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ERASE_TIMEOUT ((uint32_t)0x40000000) /*!< internal flash erase operation timeout */
|
||||
#define PROGRAMMING_TIMEOUT ((uint32_t)0x00100000) /*!< internal flash program operation timeout */
|
||||
#define SPIM_ERASE_TIMEOUT ((uint32_t)0xFFFFFFFF) /*!< spim erase operation timeout */
|
||||
#define SPIM_PROGRAMMING_TIMEOUT ((uint32_t)0x00100000) /*!< spim program operation timeout */
|
||||
#define OPERATION_TIMEOUT ((uint32_t)0x10000000) /*!< flash common operation timeout */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief flash status type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_OPERATE_BUSY = 0x00, /*!< flash status is operate busy */
|
||||
FLASH_PROGRAM_ERROR = 0x01, /*!< flash status is program error */
|
||||
FLASH_EPP_ERROR = 0x02, /*!< flash status is epp error */
|
||||
FLASH_OPERATE_DONE = 0x03, /*!< flash status is operate done */
|
||||
FLASH_OPERATE_TIMEOUT = 0x04 /*!< flash status is operate timeout */
|
||||
} flash_status_type;
|
||||
|
||||
/**
|
||||
* @brief flash spim model type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_SPIM_MODEL1 = 0x01, /*!< spim model 1 */
|
||||
FLASH_SPIM_MODEL2 = 0x02 /*!< spim model 2 */
|
||||
} flash_spim_model_type;
|
||||
|
||||
/**
|
||||
* @brief type define flash register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief flash psr register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t psr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 32; /* [31:0] */
|
||||
} psr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash unlock register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t unlock;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ukval : 32;/* [31:0] */
|
||||
} unlock_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash usd unlock register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t usd_unlock;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t usd_ukval : 32;/* [31:0] */
|
||||
} usd_unlock_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash sts register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t obf : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 1; /* [1] */
|
||||
__IO uint32_t prgmerr : 1; /* [2] */
|
||||
__IO uint32_t reserved2 : 1; /* [3] */
|
||||
__IO uint32_t epperr : 1; /* [4] */
|
||||
__IO uint32_t odf : 1; /* [5] */
|
||||
__IO uint32_t reserved3 : 26;/* [31:6] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash ctrl register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fprgm : 1; /* [0] */
|
||||
__IO uint32_t secers : 1; /* [1] */
|
||||
__IO uint32_t bankers : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 1; /* [3] */
|
||||
__IO uint32_t usdprgm : 1; /* [4] */
|
||||
__IO uint32_t usders : 1; /* [5] */
|
||||
__IO uint32_t erstr : 1; /* [6] */
|
||||
__IO uint32_t oplk : 1; /* [7] */
|
||||
__IO uint32_t reserved2 : 1; /* [8] */
|
||||
__IO uint32_t usdulks : 1; /* [9] */
|
||||
__IO uint32_t errie : 1; /* [10] */
|
||||
__IO uint32_t reserved3 : 1; /* [11] */
|
||||
__IO uint32_t odfie : 1; /* [12] */
|
||||
__IO uint32_t reserved4 : 19;/* [31:13] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash addr register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t addr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fa : 32;/* [31:0] */
|
||||
} addr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved1 register, offset:0x18
|
||||
*/
|
||||
__IO uint32_t reserved1;
|
||||
|
||||
/**
|
||||
* @brief flash usd register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t usd;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t usderr : 1; /* [0] */
|
||||
__IO uint32_t fap : 1; /* [1] */
|
||||
__IO uint32_t wdt_ato_en : 1; /* [2] */
|
||||
__IO uint32_t depslp_rst : 1; /* [3] */
|
||||
__IO uint32_t stdby_rst : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 5; /* [9:5] */
|
||||
__IO uint32_t user_d0 : 8; /* [17:10] */
|
||||
__IO uint32_t user_d1 : 8; /* [25:18] */
|
||||
__IO uint32_t reserved2 : 6; /* [31:26] */
|
||||
} usd_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash epps register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t epps;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t epps : 32;/* [31:0] */
|
||||
} epps_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved2 register, offset:0x80~0x24
|
||||
*/
|
||||
__IO uint32_t reserved2[24];
|
||||
|
||||
/**
|
||||
* @brief flash unlock3 register, offset:0x84
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t unlock3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ukval : 32;/* [31:0] */
|
||||
} unlock3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash select register, offset:0x88
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t select;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t select : 32;/* [31:0] */
|
||||
} select_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash sts3 register, offset:0x8C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t obf : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 1; /* [1] */
|
||||
__IO uint32_t prgmerr : 1; /* [2] */
|
||||
__IO uint32_t reserved2 : 1; /* [3] */
|
||||
__IO uint32_t epperr : 1; /* [4] */
|
||||
__IO uint32_t odf : 1; /* [5] */
|
||||
__IO uint32_t reserved3 : 26;/* [31:6] */
|
||||
} sts3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash ctrl3 register, offset:0x90
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fprgm : 1; /* [0] */
|
||||
__IO uint32_t secers : 1; /* [1] */
|
||||
__IO uint32_t chpers : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 3; /* [5:3] */
|
||||
__IO uint32_t erstr : 1; /* [6] */
|
||||
__IO uint32_t oplk : 1; /* [7] */
|
||||
__IO uint32_t reserved2 : 2; /* [9:8] */
|
||||
__IO uint32_t errie : 1; /* [10] */
|
||||
__IO uint32_t reserved3 : 1; /* [11] */
|
||||
__IO uint32_t odfie : 1; /* [12] */
|
||||
__IO uint32_t reserved4 : 19;/* [31:13] */
|
||||
} ctrl3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash addr3 register, offset:0x94
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t addr3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fa : 32;/* [31:0] */
|
||||
} addr3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash da register, offset:0x98
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t da;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fda : 32;/* [31:0] */
|
||||
} da_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved5 register, offset:0xC8~0x9C
|
||||
*/
|
||||
__IO uint32_t reserved5[12];
|
||||
|
||||
/**
|
||||
* @brief flash slib_sts0 register, offset:0xCC
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_sts0;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 3; /* [2:0] */
|
||||
__IO uint32_t slib_enf : 1; /* [3] */
|
||||
__IO uint32_t reserved2 : 28;/* [31:4] */
|
||||
} slib_sts0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_sts1 register, offset:0xD0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_sts1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_ss : 11;/* [10:0] */
|
||||
__IO uint32_t slib_dat_ss : 11;/* [21:11] */
|
||||
__IO uint32_t slib_es : 10;/* [31:22] */
|
||||
} slib_sts1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_pwd_clr register, offset:0xD4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_pwd_clr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_pclr_val : 32;/* [31:0] */
|
||||
} slib_pwd_clr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_misc_sts register, offset:0xD8
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_misc_sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_pwd_err : 1; /* [0] */
|
||||
__IO uint32_t slib_pwd_ok : 1; /* [1] */
|
||||
__IO uint32_t slib_ulkf : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 13;/* [15:3] */
|
||||
__IO uint32_t slib_rcnt : 9; /* [24:16] */
|
||||
__IO uint32_t reserved2 : 7; /* [31:25] */
|
||||
} slib_misc_sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_set_pwd register, offset:0xDC
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_set_pwd;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_pset_val : 32;/* [31:0] */
|
||||
} slib_set_pwd_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_set_range register, offset:0xE0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_set_range;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_ss_set : 11;/* [10:0] */
|
||||
__IO uint32_t slib_dss_set : 11;/* [21:11] */
|
||||
__IO uint32_t slib_es_set : 10;/* [31:22] */
|
||||
} slib_set_range_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved6 register, offset:0xEC~0xE4
|
||||
*/
|
||||
__IO uint32_t reserved6[3];
|
||||
|
||||
/**
|
||||
* @brief flash slib_unlock register, offset:0xF0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_unlock;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_ukval : 32;/* [31:0] */
|
||||
} slib_unlock_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash crc_ctrl register, offset:0xF4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t crc_ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t crc_ss : 12;/* [11:0] */
|
||||
__IO uint32_t crc_sn : 12;/* [23:12] */
|
||||
__IO uint32_t reserved1 : 7; /* [30:24] */
|
||||
__IO uint32_t crc_strt : 1; /* [31] */
|
||||
} crc_ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash crc_chkr register, offset:0xF8
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t crc_chkr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t crc_chkr : 32;/* [31:0] */
|
||||
} crc_chkr_bit;
|
||||
};
|
||||
|
||||
} flash_type;
|
||||
|
||||
/**
|
||||
* @brief user system data
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint16_t fap;
|
||||
__IO uint16_t ssb;
|
||||
__IO uint16_t data0;
|
||||
__IO uint16_t data1;
|
||||
__IO uint16_t epp0;
|
||||
__IO uint16_t epp1;
|
||||
__IO uint16_t epp2;
|
||||
__IO uint16_t epp3;
|
||||
__IO uint16_t eopb0;
|
||||
__IO uint16_t reserved;
|
||||
__IO uint16_t data2;
|
||||
__IO uint16_t data3;
|
||||
__IO uint16_t data4;
|
||||
__IO uint16_t data5;
|
||||
__IO uint16_t data6;
|
||||
__IO uint16_t data7;
|
||||
__IO uint16_t ext_flash_key[8];
|
||||
} usd_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define FLASH ((flash_type *) FLASH_REG_BASE)
|
||||
#define USD ((usd_type *) USD_BASE)
|
||||
|
||||
/** @defgroup FLASH_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
flag_status flash_flag_get(uint32_t flash_flag);
|
||||
void flash_flag_clear(uint32_t flash_flag);
|
||||
flash_status_type flash_operation_status_get(void);
|
||||
flash_status_type flash_spim_operation_status_get(void);
|
||||
flash_status_type flash_operation_wait_for(uint32_t time_out);
|
||||
flash_status_type flash_spim_operation_wait_for(uint32_t time_out);
|
||||
void flash_unlock(void);
|
||||
void flash_spim_unlock(void);
|
||||
void flash_lock(void);
|
||||
void flash_spim_lock(void);
|
||||
flash_status_type flash_sector_erase(uint32_t sector_address);
|
||||
flash_status_type flash_internal_all_erase(void);
|
||||
flash_status_type flash_spim_all_erase(void);
|
||||
flash_status_type flash_user_system_data_erase(void);
|
||||
flash_status_type flash_word_program(uint32_t address, uint32_t data);
|
||||
flash_status_type flash_halfword_program(uint32_t address, uint16_t data);
|
||||
flash_status_type flash_byte_program(uint32_t address, uint8_t data);
|
||||
flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data);
|
||||
flash_status_type flash_epp_set(uint32_t *sector_bits);
|
||||
void flash_epp_status_get(uint32_t *sector_bits);
|
||||
flash_status_type flash_fap_enable(confirm_state new_state);
|
||||
flag_status flash_fap_status_get(void);
|
||||
flash_status_type flash_ssb_set(uint8_t usd_ssb);
|
||||
uint8_t flash_ssb_status_get(void);
|
||||
void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
|
||||
void flash_spim_model_select(flash_spim_model_type mode);
|
||||
void flash_spim_encryption_range_set(uint32_t decode_address);
|
||||
void flash_spim_dummy_read(void);
|
||||
flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt);
|
||||
flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t data_start_sector, uint16_t end_sector);
|
||||
error_status flash_slib_disable(uint32_t pwd);
|
||||
uint32_t flash_slib_remaining_count_get(void);
|
||||
flag_status flash_slib_state_get(void);
|
||||
uint16_t flash_slib_start_sector_get(void);
|
||||
uint16_t flash_slib_datastart_sector_get(void);
|
||||
uint16_t flash_slib_end_sector_get(void);
|
||||
uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
791
libraries/drivers/inc/at32f413_gpio.h
Normal file
791
libraries/drivers/inc/at32f413_gpio.h
Normal file
@@ -0,0 +1,791 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_gpio.h
|
||||
* @brief at32f413 gpio header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F413_GPIO_H
|
||||
#define __AT32F413_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f413.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_number_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_PINS_0 0x0001 /*!< gpio pins number 0 */
|
||||
#define GPIO_PINS_1 0x0002 /*!< gpio pins number 1 */
|
||||
#define GPIO_PINS_2 0x0004 /*!< gpio pins number 2 */
|
||||
#define GPIO_PINS_3 0x0008 /*!< gpio pins number 3 */
|
||||
#define GPIO_PINS_4 0x0010 /*!< gpio pins number 4 */
|
||||
#define GPIO_PINS_5 0x0020 /*!< gpio pins number 5 */
|
||||
#define GPIO_PINS_6 0x0040 /*!< gpio pins number 6 */
|
||||
#define GPIO_PINS_7 0x0080 /*!< gpio pins number 7 */
|
||||
#define GPIO_PINS_8 0x0100 /*!< gpio pins number 8 */
|
||||
#define GPIO_PINS_9 0x0200 /*!< gpio pins number 9 */
|
||||
#define GPIO_PINS_10 0x0400 /*!< gpio pins number 10 */
|
||||
#define GPIO_PINS_11 0x0800 /*!< gpio pins number 11 */
|
||||
#define GPIO_PINS_12 0x1000 /*!< gpio pins number 12 */
|
||||
#define GPIO_PINS_13 0x2000 /*!< gpio pins number 13 */
|
||||
#define GPIO_PINS_14 0x4000 /*!< gpio pins number 14 */
|
||||
#define GPIO_PINS_15 0x8000 /*!< gpio pins number 15 */
|
||||
#define GPIO_PINS_ALL 0xFFFF /*!< gpio all pins */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IOMUX_MAKE_VALUE(reg_offset, bit_addr ,bit_num, bit_val) \
|
||||
(uint32_t)(((reg_offset) << 24) | ((bit_addr) << 16) | ((bit_num) << 8) | (bit_val))
|
||||
|
||||
/** @defgroup IOMUX_map_definition
|
||||
* @brief iomux map definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI1_MUX_01 SPI1_GMUX_0001 /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb0) */
|
||||
#define I2C1_MUX I2C1_GMUX_0001 /*!< i2c1_scl(pb8), i2c1_sda(pb9) */
|
||||
#define USART1_MUX USART1_GMUX_0001 /*!< usart1_tx(pb6), usart1_rx(pb7) */
|
||||
#define USART3_MUX_01 USART3_GMUX_0001 /*!< usart3_tx(pc10), usart3_rx(pc11), usart3_ck(pc12), usart3_cts(pb13), usart3_rts(pb14) */
|
||||
#define TMR1_MUX_01 TMR1_GMUX_0001 /*!< tmr1_ext(pa12), tmr1_ch1(pa8), tmr1_ch2(pa9), tmr1_ch3(pa10), tmr1_ch4(pa11), tmr1_brkin(pa6), tmr1_ch1c(pa7), tmr1_ch2c(pb0), tmr1_ch3c(pb1) */
|
||||
#define TMR2_MUX_01 TMR2_GMUX_001 /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pa2), tmr2_ch4(pa3) */
|
||||
#define TMR2_MUX_10 TMR2_GMUX_010 /*!< tmr2_ch1_ext(pa0), tmr2_ch2(pa1), tmr2_ch3(pb10), tmr2_ch4(pb11) */
|
||||
#define TMR2_MUX_11 TMR2_GMUX_011 /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pb10), tmr2_ch4(pb11) */
|
||||
#define TMR3_MUX_10 TMR3_GMUX_0010 /*!< tmr3_ch1(pb4), tmr3_ch2(pb5), tmr3_ch3(pb0), tmr3_ch4(pb1) */
|
||||
#define TMR3_MUX_11 TMR3_GMUX_0011 /*!< tmr3_ch1(pc6), tmr3_ch2(pc7), tmr3_ch3(pc8), tmr3_ch4(pc9) */
|
||||
#define CAN_MUX_10 CAN1_GMUX_0010 /*!< can_rx(pb8), can_tx(pb9) */
|
||||
#define PD01_MUX PD01_GMUX /*!< pd0/pd1 mapping on osc_in/osc_out */
|
||||
#define TMR5CH4_MUX TMR5CH4_GMUX /*!< lick connected to tmr5_ch4 input capture for calibration */
|
||||
#define ADC1_ETP_MUX ADC1_ETP_GMUX /*!< adc1 external trigger preempted conversion muxing */
|
||||
#define ADC1_ETO_MUX ADC1_ETO_GMUX /*!< adc1 external trigger ordinary conversion muxing */
|
||||
#define ADC2_ETP_MUX ADC2_ETP_GMUX /*!< adc2 external trigger preempted conversion muxing */
|
||||
#define ADC2_ETO_MUX ADC2_ETO_GMUX /*!< adc2 external trigger ordinary conversion muxing */
|
||||
#define SWJTAG_CONF_001 SWJTAG_GMUX_001 /*!< full swj enabled (jtag-dp + sw-dp) but without jtrst */
|
||||
#define SWJTAG_CONF_010 SWJTAG_GMUX_010 /*!< jtag-dp disabled and sw-dp enabled */
|
||||
#define SWJTAG_CONF_100 SWJTAG_GMUX_100 /*!< full swj disabled (jtag-dp + sw-dp) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IOMUX_map2_definition
|
||||
* @brief iomux map2 definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXT_SPIM_EN_MUX EXT_SPIM_GMUX_1000 /*!< enable external spi-flash interface */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IOMUX_map3_definition
|
||||
* @brief iomux map3 definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TMR9_GMUX IOMUX_MAKE_VALUE(0x20, 0, 4, 0x02) /*!< tmr9_ch1(pb14), tmr9_ch2(pb15) */
|
||||
#define TMR10_GMUX IOMUX_MAKE_VALUE(0x20, 4, 4, 0x02) /*!< tmr10_ch1(pa6) */
|
||||
#define TMR11_GMUX IOMUX_MAKE_VALUE(0x20, 8, 4, 0x02) /*!< tmr11_ch1(pa7) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IOMUX_map4_definition
|
||||
* @brief iomux map4 definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TMR1_GMUX_0001 IOMUX_MAKE_VALUE(0x24, 0, 4, 0x01) /*!< tmr1_ext(pa12), tmr1_ch1(pa8), tmr1_ch2(pa9), tmr1_ch3(pa10), tmr1_ch4(pa11), tmr1_brkin(pa6), tmr1_ch1c(pa7), tmr1_ch2c(pb0), tmr1_ch3c(pb1) */
|
||||
#define TMR2_GMUX_001 IOMUX_MAKE_VALUE(0x24, 4, 3, 0x01) /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pa2), tmr2_ch4(pa3) */
|
||||
#define TMR2_GMUX_010 IOMUX_MAKE_VALUE(0x24, 4, 3, 0x02) /*!< tmr2_ch1_ext(pa0), tmr2_ch2(pa1), tmr2_ch3(pb10), tmr2_ch4(pb11) */
|
||||
#define TMR2_GMUX_011 IOMUX_MAKE_VALUE(0x24, 4, 3, 0x03) /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pb10), tmr2_ch4(pb11) */
|
||||
#define TMR2ITR1_GMUX IOMUX_MAKE_VALUE(0x24, 7, 1, 0x01) /*!< usbdev sof as input to tmr2_int.1 */
|
||||
#define TMR3_GMUX_0010 IOMUX_MAKE_VALUE(0x24, 8, 4, 0x02) /*!< tmr3_ch1(pb4), tmr3_ch2(pb5), tmr3_ch3(pb0), tmr3_ch4(pb1) */
|
||||
#define TMR3_GMUX_0011 IOMUX_MAKE_VALUE(0x24, 8, 4, 0x03) /*!< tmr3_ch1(pc6), tmr3_ch2(pc7), tmr3_ch3(pc8), tmr3_ch4(pc9) */
|
||||
#define TMR5_GMUX_001 IOMUX_MAKE_VALUE(0x24, 16, 3, 0x01) /*!< tmr5_ch1(pf4), tmr5_ch2(pf5) */
|
||||
#define TMR5CH4_GMUX IOMUX_MAKE_VALUE(0x24, 19, 1, 0x01) /*!< lick connected to tmr5_ch4 input capture for calibration */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IOMUX_map5_definition
|
||||
* @brief iomux map5 definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C1_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 4, 4, 0x01) /*!< i2c1_scl(pb8), i2c1_sda(pb9) */
|
||||
#define I2C1_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 4, 4, 0x03) /*!< i2c1_scl(pf6), i2c1_sda(pf7) */
|
||||
#define I2C2_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 8, 4, 0x01) /*!< i2c2_scl(pf6), i2c2_sda(pf7) */
|
||||
#define I2C2_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 8, 4, 0x01) /*!< i2c2_scl(pa8), i2c2_sda(pc9) */
|
||||
#define I2C2_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 8, 4, 0x01) /*!< i2c2_scl(pa8), i2c2_sda(pb4) */
|
||||
#define SPI1_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 16, 4, 0x01) /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb6) */
|
||||
#define SPI2_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 20, 4, 0x01) /*!< spi2_cs/i2s2_ws(pa15), spi2_sck/i2s2_ck(pb3), spi2_miso(pb4), spi2_mosi/i2s2_sd(pb5), i2s2_mck(pc7) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IOMUX_map6_definition
|
||||
* @brief iomux map6 definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN1_GMUX_0010 IOMUX_MAKE_VALUE(0x2C, 0, 4, 0x02) /*!< can_rx(pb8), can_tx(pb9) */
|
||||
#define CAN2_GMUX_0001 IOMUX_MAKE_VALUE(0x2C, 4, 4, 0x01) /*!< can2_rx(pb5), can2_tx(pb6) */
|
||||
#define SDIO1_GMUX_0100 IOMUX_MAKE_VALUE(0x2C, 8, 4, 0x04) /*!< sdio1_ck(pc4), sdio1_cmd(pc5), sdio1_d0(pc0), sdio1_d1(pc1), sdio1_d2(pc2), sdio1_d3(pc3), sdio1_d4(pa4), sdio1_d5(pa5), sdio1_d6(pa6), sdio1_d7(pa7) */
|
||||
#define SDIO1_GMUX_0101 IOMUX_MAKE_VALUE(0x2C, 8, 4, 0x05) /*!< sdio1_ck(pc4), sdio1_cmd(pc5), sdio1_d0(pa4), sdio1_d1(pa5), sdio1_d2(pa6), sdio1_d3(pa7) */
|
||||
#define SDIO1_GMUX_0110 IOMUX_MAKE_VALUE(0x2C, 8, 4, 0x06) /*!< sdio1_ck(pa2), sdio1_cmd(pa3), sdio1_d0(pc0), sdio1_d1(pc1), sdio1_d2(pc2), sdio1_d3(pc3), sdio1_d4(pa4), sdio1_d5(pa5), sdio1_d6(pa6), sdio1_d7(pa7) */
|
||||
#define SDIO1_GMUX_0111 IOMUX_MAKE_VALUE(0x2C, 8, 4, 0x07) /*!< sdio1_ck(pa2), sdio1_cmd(pa3), sdio1_d0(pa4), sdio1_d1(pa5), sdio1_d2(pa6), sdio1_d3(pa7) */
|
||||
#define USART1_GMUX_0001 IOMUX_MAKE_VALUE(0x2C, 16, 4, 0x01) /*!< usart1_tx(pb6), usart1_rx(pb7) */
|
||||
#define USART3_GMUX_0001 IOMUX_MAKE_VALUE(0x2C, 24, 4, 0x01) /*!< usart3_tx(pc10), usart3_rx(pc11), usart3_ck(pc12), usart3_cts(pb13), usart3_rts(pb14) */
|
||||
#define UART4_GMUX_0001 IOMUX_MAKE_VALUE(0x2C, 28, 4, 0x01) /*!< uart4_tx(pf4), uart4_rx(pf5) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IOMUX_map7_definition
|
||||
* @brief iomux map7 definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXT_SPIM_GMUX_1000 IOMUX_MAKE_VALUE(0x30, 0, 4, 0x08) /*!< spim_sck(pb1), spim_cs(pa8), spim_io0(pa11), spim_io1(pa12), spim_io2(pb7), spim_sio3(pb6) */
|
||||
#define EXT_SPIM_GMUX_1001 IOMUX_MAKE_VALUE(0x30, 0, 4, 0x09) /*!< spim_sck(pb1), spim_cs(pa8), spim_io0(pb10), spim_io1(pb11), spim_io2(pb7), spim_sio3(pb6) */
|
||||
#define ADC1_ETP_GMUX IOMUX_MAKE_VALUE(0x30, 4, 1, 0x01) /*!< adc1 external trigger preempted conversion muxing */
|
||||
#define ADC1_ETO_GMUX IOMUX_MAKE_VALUE(0x30, 5, 1, 0x01) /*!< adc1 external trigger ordinary conversion muxing */
|
||||
#define ADC2_ETP_GMUX IOMUX_MAKE_VALUE(0x30, 8, 1, 0x01) /*!< adc2 external trigger preempted conversion muxing */
|
||||
#define ADC2_ETO_GMUX IOMUX_MAKE_VALUE(0x30, 9, 1, 0x01) /*!< adc2 external trigger ordinary conversion muxing */
|
||||
#define SWJTAG_GMUX_001 IOMUX_MAKE_VALUE(0x30, 16, 3, 0x01) /*!< full swj enabled (jtag-dp + sw-dp) but without jtrst */
|
||||
#define SWJTAG_GMUX_010 IOMUX_MAKE_VALUE(0x30, 16, 3, 0x02) /*!< jtag-dp disabled and sw-dp enabled */
|
||||
#define SWJTAG_GMUX_100 IOMUX_MAKE_VALUE(0x30, 16, 3, 0x04) /*!< full swj disabled (jtag-dp + sw-dp) */
|
||||
#define PD01_GMUX IOMUX_MAKE_VALUE(0x30, 20, 1, 0x01) /*!< pd0/pd1 mapping on osc_in/osc_out */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief gpio mode select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_MODE_INPUT = 0x00, /*!< gpio input mode */
|
||||
GPIO_MODE_OUTPUT = 0x10, /*!< gpio output mode */
|
||||
GPIO_MODE_MUX = 0x08, /*!< gpio mux function mode */
|
||||
GPIO_MODE_ANALOG = 0x03 /*!< gpio analog in/out mode */
|
||||
} gpio_mode_type;
|
||||
|
||||
/**
|
||||
* @brief gpio output drive strength select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_DRIVE_STRENGTH_STRONGER = 0x01, /*!< stronger sourcing/sinking strength */
|
||||
GPIO_DRIVE_STRENGTH_MODERATE = 0x02, /*!< moderate sourcing/sinking strength */
|
||||
GPIO_DRIVE_STRENGTH_MAXIMUM = 0x03 /*!< maximum sourcing/sinking strength */
|
||||
} gpio_drive_type;
|
||||
|
||||
/**
|
||||
* @brief gpio output type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_OUTPUT_PUSH_PULL = 0x00, /*!< output push-pull */
|
||||
GPIO_OUTPUT_OPEN_DRAIN = 0x04 /*!< output open-drain */
|
||||
} gpio_output_type;
|
||||
|
||||
/**
|
||||
* @brief gpio pull type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PULL_NONE = 0x0004, /*!< floating for input, no pull for output */
|
||||
GPIO_PULL_UP = 0x0018, /*!< pull-up */
|
||||
GPIO_PULL_DOWN = 0x0028 /*!< pull-down */
|
||||
} gpio_pull_type;
|
||||
|
||||
/**
|
||||
* @brief gpio pins source type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PINS_SOURCE0 = 0x00, /*!< gpio pins source number 0 */
|
||||
GPIO_PINS_SOURCE1 = 0x01, /*!< gpio pins source number 1 */
|
||||
GPIO_PINS_SOURCE2 = 0x02, /*!< gpio pins source number 2 */
|
||||
GPIO_PINS_SOURCE3 = 0x03, /*!< gpio pins source number 3 */
|
||||
GPIO_PINS_SOURCE4 = 0x04, /*!< gpio pins source number 4 */
|
||||
GPIO_PINS_SOURCE5 = 0x05, /*!< gpio pins source number 5 */
|
||||
GPIO_PINS_SOURCE6 = 0x06, /*!< gpio pins source number 6 */
|
||||
GPIO_PINS_SOURCE7 = 0x07, /*!< gpio pins source number 7 */
|
||||
GPIO_PINS_SOURCE8 = 0x08, /*!< gpio pins source number 8 */
|
||||
GPIO_PINS_SOURCE9 = 0x09, /*!< gpio pins source number 9 */
|
||||
GPIO_PINS_SOURCE10 = 0x0A, /*!< gpio pins source number 10 */
|
||||
GPIO_PINS_SOURCE11 = 0x0B, /*!< gpio pins source number 11 */
|
||||
GPIO_PINS_SOURCE12 = 0x0C, /*!< gpio pins source number 12 */
|
||||
GPIO_PINS_SOURCE13 = 0x0D, /*!< gpio pins source number 13 */
|
||||
GPIO_PINS_SOURCE14 = 0x0E, /*!< gpio pins source number 14 */
|
||||
GPIO_PINS_SOURCE15 = 0x0F /*!< gpio pins source number 15 */
|
||||
} gpio_pins_source_type;
|
||||
|
||||
/**
|
||||
* @brief gpio port source type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PORT_SOURCE_GPIOA = 0x00, /*!< gpio port source gpioa */
|
||||
GPIO_PORT_SOURCE_GPIOB = 0x01, /*!< gpio port source gpiob */
|
||||
GPIO_PORT_SOURCE_GPIOC = 0x02, /*!< gpio port source gpioc */
|
||||
GPIO_PORT_SOURCE_GPIOD = 0x03, /*!< gpio port source gpiod */
|
||||
GPIO_PORT_SOURCE_GPIOF = 0x05, /*!< gpio port source gpiof */
|
||||
} gpio_port_source_type;
|
||||
|
||||
/**
|
||||
* @brief gpio init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t gpio_pins; /*!< pins number selection */
|
||||
gpio_output_type gpio_out_type; /*!< output type selection */
|
||||
gpio_pull_type gpio_pull; /*!< pull type selection */
|
||||
gpio_mode_type gpio_mode; /*!< mode selection */
|
||||
gpio_drive_type gpio_drive_strength; /*!< drive strength selection */
|
||||
} gpio_init_type;
|
||||
|
||||
/**
|
||||
* @brief type define gpio register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief gpio cfglr register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfglr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iomc0 : 2; /* [1:0] */
|
||||
__IO uint32_t iofc0 : 2; /* [3:2] */
|
||||
__IO uint32_t iomc1 : 2; /* [5:4] */
|
||||
__IO uint32_t iofc1 : 2; /* [7:6] */
|
||||
__IO uint32_t iomc2 : 2; /* [9:8] */
|
||||
__IO uint32_t iofc2 : 2; /* [11:10] */
|
||||
__IO uint32_t iomc3 : 2; /* [13:12] */
|
||||
__IO uint32_t iofc3 : 2; /* [15:14] */
|
||||
__IO uint32_t iomc4 : 2; /* [17:16] */
|
||||
__IO uint32_t iofc4 : 2; /* [19:18] */
|
||||
__IO uint32_t iomc5 : 2; /* [21:20] */
|
||||
__IO uint32_t iofc5 : 2; /* [23:22] */
|
||||
__IO uint32_t iomc6 : 2; /* [25:24] */
|
||||
__IO uint32_t iofc6 : 2; /* [27:26] */
|
||||
__IO uint32_t iomc7 : 2; /* [29:28] */
|
||||
__IO uint32_t iofc7 : 2; /* [31:30] */
|
||||
} cfglr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio cfghr register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfghr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iomc8 : 2; /* [1:0] */
|
||||
__IO uint32_t iofc8 : 2; /* [3:2] */
|
||||
__IO uint32_t iomc9 : 2; /* [5:4] */
|
||||
__IO uint32_t iofc9 : 2; /* [7:6] */
|
||||
__IO uint32_t iomc10 : 2; /* [9:8] */
|
||||
__IO uint32_t iofc10 : 2; /* [11:10] */
|
||||
__IO uint32_t iomc11 : 2; /* [13:12] */
|
||||
__IO uint32_t iofc11 : 2; /* [15:14] */
|
||||
__IO uint32_t iomc12 : 2; /* [17:16] */
|
||||
__IO uint32_t iofc12 : 2; /* [19:18] */
|
||||
__IO uint32_t iomc13 : 2; /* [21:20] */
|
||||
__IO uint32_t iofc13 : 2; /* [23:22] */
|
||||
__IO uint32_t iomc14 : 2; /* [25:24] */
|
||||
__IO uint32_t iofc14 : 2; /* [27:26] */
|
||||
__IO uint32_t iomc15 : 2; /* [29:28] */
|
||||
__IO uint32_t iofc15 : 2; /* [31:30] */
|
||||
} cfghr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio idt register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t idt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t idt0 : 1; /* [0] */
|
||||
__IO uint32_t idt1 : 1; /* [1] */
|
||||
__IO uint32_t idt2 : 1; /* [2] */
|
||||
__IO uint32_t idt3 : 1; /* [3] */
|
||||
__IO uint32_t idt4 : 1; /* [4] */
|
||||
__IO uint32_t idt5 : 1; /* [5] */
|
||||
__IO uint32_t idt6 : 1; /* [6] */
|
||||
__IO uint32_t idt7 : 1; /* [7] */
|
||||
__IO uint32_t idt8 : 1; /* [8] */
|
||||
__IO uint32_t idt9 : 1; /* [9] */
|
||||
__IO uint32_t idt10 : 1; /* [10] */
|
||||
__IO uint32_t idt11 : 1; /* [11] */
|
||||
__IO uint32_t idt12 : 1; /* [12] */
|
||||
__IO uint32_t idt13 : 1; /* [13] */
|
||||
__IO uint32_t idt14 : 1; /* [14] */
|
||||
__IO uint32_t idt15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} idt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio odt register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t odt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t odt0 : 1; /* [0] */
|
||||
__IO uint32_t odt1 : 1; /* [1] */
|
||||
__IO uint32_t odt2 : 1; /* [2] */
|
||||
__IO uint32_t odt3 : 1; /* [3] */
|
||||
__IO uint32_t odt4 : 1; /* [4] */
|
||||
__IO uint32_t odt5 : 1; /* [5] */
|
||||
__IO uint32_t odt6 : 1; /* [6] */
|
||||
__IO uint32_t odt7 : 1; /* [7] */
|
||||
__IO uint32_t odt8 : 1; /* [8] */
|
||||
__IO uint32_t odt9 : 1; /* [9] */
|
||||
__IO uint32_t odt10 : 1; /* [10] */
|
||||
__IO uint32_t odt11 : 1; /* [11] */
|
||||
__IO uint32_t odt12 : 1; /* [12] */
|
||||
__IO uint32_t odt13 : 1; /* [13] */
|
||||
__IO uint32_t odt14 : 1; /* [14] */
|
||||
__IO uint32_t odt15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} odt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio scr register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t scr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iosb0 : 1; /* [0] */
|
||||
__IO uint32_t iosb1 : 1; /* [1] */
|
||||
__IO uint32_t iosb2 : 1; /* [2] */
|
||||
__IO uint32_t iosb3 : 1; /* [3] */
|
||||
__IO uint32_t iosb4 : 1; /* [4] */
|
||||
__IO uint32_t iosb5 : 1; /* [5] */
|
||||
__IO uint32_t iosb6 : 1; /* [6] */
|
||||
__IO uint32_t iosb7 : 1; /* [7] */
|
||||
__IO uint32_t iosb8 : 1; /* [8] */
|
||||
__IO uint32_t iosb9 : 1; /* [9] */
|
||||
__IO uint32_t iosb10 : 1; /* [10] */
|
||||
__IO uint32_t iosb11 : 1; /* [11] */
|
||||
__IO uint32_t iosb12 : 1; /* [12] */
|
||||
__IO uint32_t iosb13 : 1; /* [13] */
|
||||
__IO uint32_t iosb14 : 1; /* [14] */
|
||||
__IO uint32_t iosb15 : 1; /* [15] */
|
||||
__IO uint32_t iocb0 : 1; /* [16] */
|
||||
__IO uint32_t iocb1 : 1; /* [17] */
|
||||
__IO uint32_t iocb2 : 1; /* [18] */
|
||||
__IO uint32_t iocb3 : 1; /* [19] */
|
||||
__IO uint32_t iocb4 : 1; /* [20] */
|
||||
__IO uint32_t iocb5 : 1; /* [21] */
|
||||
__IO uint32_t iocb6 : 1; /* [22] */
|
||||
__IO uint32_t iocb7 : 1; /* [23] */
|
||||
__IO uint32_t iocb8 : 1; /* [24] */
|
||||
__IO uint32_t iocb9 : 1; /* [25] */
|
||||
__IO uint32_t iocb10 : 1; /* [26] */
|
||||
__IO uint32_t iocb11 : 1; /* [27] */
|
||||
__IO uint32_t iocb12 : 1; /* [28] */
|
||||
__IO uint32_t iocb13 : 1; /* [29] */
|
||||
__IO uint32_t iocb14 : 1; /* [30] */
|
||||
__IO uint32_t iocb15 : 1; /* [31] */
|
||||
} scr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio clr register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iocb0 : 1; /* [0] */
|
||||
__IO uint32_t iocb1 : 1; /* [1] */
|
||||
__IO uint32_t iocb2 : 1; /* [2] */
|
||||
__IO uint32_t iocb3 : 1; /* [3] */
|
||||
__IO uint32_t iocb4 : 1; /* [4] */
|
||||
__IO uint32_t iocb5 : 1; /* [5] */
|
||||
__IO uint32_t iocb6 : 1; /* [6] */
|
||||
__IO uint32_t iocb7 : 1; /* [7] */
|
||||
__IO uint32_t iocb8 : 1; /* [8] */
|
||||
__IO uint32_t iocb9 : 1; /* [9] */
|
||||
__IO uint32_t iocb10 : 1; /* [10] */
|
||||
__IO uint32_t iocb11 : 1; /* [11] */
|
||||
__IO uint32_t iocb12 : 1; /* [12] */
|
||||
__IO uint32_t iocb13 : 1; /* [13] */
|
||||
__IO uint32_t iocb14 : 1; /* [14] */
|
||||
__IO uint32_t iocb15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} clr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio wpr register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t wpr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t wpen0 : 1; /* [0] */
|
||||
__IO uint32_t wpen1 : 1; /* [1] */
|
||||
__IO uint32_t wpen2 : 1; /* [2] */
|
||||
__IO uint32_t wpen3 : 1; /* [3] */
|
||||
__IO uint32_t wpen4 : 1; /* [4] */
|
||||
__IO uint32_t wpen5 : 1; /* [5] */
|
||||
__IO uint32_t wpen6 : 1; /* [6] */
|
||||
__IO uint32_t wpen7 : 1; /* [7] */
|
||||
__IO uint32_t wpen8 : 1; /* [8] */
|
||||
__IO uint32_t wpen9 : 1; /* [9] */
|
||||
__IO uint32_t wpen10 : 1; /* [10] */
|
||||
__IO uint32_t wpen11 : 1; /* [11] */
|
||||
__IO uint32_t wpen12 : 1; /* [12] */
|
||||
__IO uint32_t wpen13 : 1; /* [13] */
|
||||
__IO uint32_t wpen14 : 1; /* [14] */
|
||||
__IO uint32_t wpen15 : 1; /* [15] */
|
||||
__IO uint32_t wpseq : 1; /* [16] */
|
||||
__IO uint32_t reserved1 : 15;/* [31:17] */
|
||||
} wpr_bit;
|
||||
};
|
||||
|
||||
} gpio_type;
|
||||
|
||||
/**
|
||||
* @brief type define iomux register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief mux event control register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t evtout;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t selpin : 4; /* [3:0] */
|
||||
__IO uint32_t selport : 3; /* [6:4] */
|
||||
__IO uint32_t evoen : 1; /* [7] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} evtout_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux remap register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t spi1_mux_l : 1; /* [0] */
|
||||
__IO uint32_t i2c1_mux : 1; /* [1] */
|
||||
__IO uint32_t usart1_mux : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 1; /* [3] */
|
||||
__IO uint32_t usart3_mux : 2; /* [5:4] */
|
||||
__IO uint32_t tmr1_mux : 2; /* [7:6] */
|
||||
__IO uint32_t tmr2_mux : 2; /* [9:8] */
|
||||
__IO uint32_t tmr3_mux : 2; /* [11:10] */
|
||||
__IO uint32_t reserved2 : 1; /* [12] */
|
||||
__IO uint32_t can_mux : 2; /* [14:13] */
|
||||
__IO uint32_t pd01_mux : 1; /* [15] */
|
||||
__IO uint32_t tmr5ch4_mux : 1; /* [16] */
|
||||
__IO uint32_t adc1_extrgpre_mux : 1; /* [17] */
|
||||
__IO uint32_t adc1_extrgord_mux : 1; /* [18] */
|
||||
__IO uint32_t adc2_extrgpre_mux : 1; /* [19] */
|
||||
__IO uint32_t adc2_extrgord_mux : 1; /* [20] */
|
||||
__IO uint32_t reserved3 : 3; /* [23:21] */
|
||||
__IO uint32_t swjtag_conf : 3; /* [26:24] */
|
||||
__IO uint32_t reserved4 : 4; /* [30:27] */
|
||||
__IO uint32_t spi1_mux_h : 1; /* [31] */
|
||||
} remap_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief mux external interrupt configuration register 1, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint0 : 4; /* [3:0] */
|
||||
__IO uint32_t exint1 : 4; /* [7:4] */
|
||||
__IO uint32_t exint2 : 4; /* [11:8] */
|
||||
__IO uint32_t exint3 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief mux external interrupt configuration register 2, offset:0x0c
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint4 : 4; /* [3:0] */
|
||||
__IO uint32_t exint5 : 4; /* [7:4] */
|
||||
__IO uint32_t exint6 : 4; /* [11:8] */
|
||||
__IO uint32_t exint7 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief mux external interrupt configuration register 3, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint8 : 4; /* [3:0] */
|
||||
__IO uint32_t exint9 : 4; /* [7:4] */
|
||||
__IO uint32_t exint10 : 4; /* [11:8] */
|
||||
__IO uint32_t exint11 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief mux external interrupt configuration register 4, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint12 : 4; /* [3:0] */
|
||||
__IO uint32_t exint13 : 4; /* [7:4] */
|
||||
__IO uint32_t exint14 : 4; /* [11:8] */
|
||||
__IO uint32_t exint15 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux reserved1 register, offset:0x18
|
||||
*/
|
||||
__IO uint32_t reserved1;
|
||||
|
||||
/**
|
||||
* @brief iomux remap register 2, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 21;/* [20:0] */
|
||||
__IO uint32_t ext_spim_en_mux : 1; /* [21] */
|
||||
__IO uint32_t reserved2 : 10;/* [31:22] */
|
||||
} remap2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux remap register 3, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmr9_gmux : 4; /* [3:0] */
|
||||
__IO uint32_t tmr10_gmux : 4; /* [7:4] */
|
||||
__IO uint32_t tmr11_gmux : 4; /* [11:8] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} remap3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux remap register 4, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmr1_gmux : 4; /* [3:0] */
|
||||
__IO uint32_t tmr2_gmux : 3; /* [6:4] */
|
||||
__IO uint32_t tmr2itr1_gmux : 1; /* [7] */
|
||||
__IO uint32_t tmr3_gmux : 4; /* [11:8] */
|
||||
__IO uint32_t reserved1 : 4; /* [15:12] */
|
||||
__IO uint32_t tmr5_gmux : 3; /* [18:16] */
|
||||
__IO uint32_t tmr5ch4_gmux : 1; /* [19] */
|
||||
__IO uint32_t reserved2 : 12;/* [31:20] */
|
||||
} remap4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux remap register 5, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap5;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 4; /* [3:0] */
|
||||
__IO uint32_t i2c1_gmux : 4; /* [7:4] */
|
||||
__IO uint32_t i2c2_gmux : 4; /* [11:8] */
|
||||
__IO uint32_t reserved2 : 4; /* [15:12] */
|
||||
__IO uint32_t spi1_gmux : 4; /* [19:16] */
|
||||
__IO uint32_t spi2_gmux : 4; /* [23:20] */
|
||||
__IO uint32_t reserved3 : 8; /* [31:24] */
|
||||
} remap5_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux remap register 6, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap6;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t can1_gmux : 4; /* [3:0] */
|
||||
__IO uint32_t can2_gmux : 4; /* [7:4] */
|
||||
__IO uint32_t sdio1_gmux : 4; /* [11:8] */
|
||||
__IO uint32_t reserved1 : 4; /* [15:12] */
|
||||
__IO uint32_t usart1_gmux : 4; /* [19:16] */
|
||||
__IO uint32_t reserved2 : 4; /* [23:20] */
|
||||
__IO uint32_t usart3_gmux : 4; /* [27:24] */
|
||||
__IO uint32_t uart4_gmux : 4; /* [31:28] */
|
||||
} remap6_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux remap register 7, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap7;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ext_spim_gmux : 3; /* [2:0] */
|
||||
__IO uint32_t ext_spim_gen : 1; /* [3] */
|
||||
__IO uint32_t adc1_etp_gmux : 1; /* [4] */
|
||||
__IO uint32_t adc1_eto_gmux : 1; /* [5] */
|
||||
__IO uint32_t reserved1 : 2; /* [7:6] */
|
||||
__IO uint32_t adc2_etp_gmux : 1; /* [8] */
|
||||
__IO uint32_t adc2_eto_gmux : 1; /* [9] */
|
||||
__IO uint32_t reserved2 : 6; /* [15:10] */
|
||||
__IO uint32_t swjtag_gmux : 3; /* [18:16] */
|
||||
__IO uint32_t reserved3 : 1; /* [19] */
|
||||
__IO uint32_t pd01_gmux : 1; /* [20] */
|
||||
__IO uint32_t reserved4 : 11;/* [31:21] */
|
||||
|
||||
} remap7_bit;
|
||||
};
|
||||
|
||||
} iomux_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define GPIOA ((gpio_type *) GPIOA_BASE)
|
||||
#define GPIOB ((gpio_type *) GPIOB_BASE)
|
||||
#define GPIOC ((gpio_type *) GPIOC_BASE)
|
||||
#define GPIOD ((gpio_type *) GPIOD_BASE)
|
||||
#define GPIOF ((gpio_type *) GPIOF_BASE)
|
||||
#define IOMUX ((iomux_type *) IOMUX_BASE)
|
||||
|
||||
/** @defgroup GPIO_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void gpio_reset(gpio_type *gpio_x);
|
||||
void gpio_iomux_reset(void);
|
||||
void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
|
||||
void gpio_default_para_init(gpio_init_type *gpio_init_struct);
|
||||
flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
|
||||
uint16_t gpio_input_data_read(gpio_type *gpio_x);
|
||||
flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
|
||||
uint16_t gpio_output_data_read(gpio_type *gpio_x);
|
||||
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
|
||||
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value);
|
||||
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source);
|
||||
void gpio_event_output_enable(confirm_state new_state);
|
||||
void gpio_pin_remap_config(uint32_t gpio_remap, confirm_state new_state);
|
||||
void gpio_exint_line_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
123
libraries/drivers/inc/at32f413_misc.h
Normal file
123
libraries/drivers/inc/at32f413_misc.h
Normal file
@@ -0,0 +1,123 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_misc.h
|
||||
* @brief at32f413 misc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F413_MISC_H
|
||||
#define __AT32F413_MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f413.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_vector_table_base_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< nvic vector table based ram address */
|
||||
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< nvic vector table based flash address */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief nvic interrupt priority group
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
|
||||
} nvic_priority_group_type;
|
||||
|
||||
/**
|
||||
* @brief nvic low power mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */
|
||||
NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
|
||||
NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */
|
||||
} nvic_lowpower_mode_type;
|
||||
|
||||
/**
|
||||
* @brief systick clock source
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8 = ((uint32_t)0x00000000), /*!< systick clock source from core clock div8 */
|
||||
SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV = ((uint32_t)0x00000004) /*!< systick clock source from core clock */
|
||||
} systick_clock_source_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void nvic_system_reset(void);
|
||||
void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority);
|
||||
void nvic_irq_disable(IRQn_Type irqn);
|
||||
void nvic_priority_group_config(nvic_priority_group_type priority_group);
|
||||
void nvic_vector_table_set(uint32_t base, uint32_t offset);
|
||||
void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
|
||||
void systick_clock_source_config(systick_clock_source_type source);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
179
libraries/drivers/inc/at32f413_pwc.h
Normal file
179
libraries/drivers/inc/at32f413_pwc.h
Normal file
@@ -0,0 +1,179 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_pwc.h
|
||||
* @brief at32f413 pwc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F413_PWC_H
|
||||
#define __AT32F413_PWC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f413.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWC_flags_definition
|
||||
* @brief pwc flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWC_WAKEUP_FLAG ((uint32_t)0x00000001) /*!< wakeup flag */
|
||||
#define PWC_STANDBY_FLAG ((uint32_t)0x00000002) /*!< standby flag */
|
||||
#define PWC_PVM_OUTPUT_FLAG ((uint32_t)0x00000004) /*!< pvm output flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief pwc wakeup pin num definition
|
||||
*/
|
||||
#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */
|
||||
|
||||
/** @defgroup PWC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief pwc pvm voltage type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_PVM_VOLTAGE_2V3 = 0x01, /*!< power voltage monitoring boundary 2.3v */
|
||||
PWC_PVM_VOLTAGE_2V4 = 0x02, /*!< power voltage monitoring boundary 2.4v */
|
||||
PWC_PVM_VOLTAGE_2V5 = 0x03, /*!< power voltage monitoring boundary 2.5v */
|
||||
PWC_PVM_VOLTAGE_2V6 = 0x04, /*!< power voltage monitoring boundary 2.6v */
|
||||
PWC_PVM_VOLTAGE_2V7 = 0x05, /*!< power voltage monitoring boundary 2.7v */
|
||||
PWC_PVM_VOLTAGE_2V8 = 0x06, /*!< power voltage monitoring boundary 2.8v */
|
||||
PWC_PVM_VOLTAGE_2V9 = 0x07 /*!< power voltage monitoring boundary 2.9v */
|
||||
} pwc_pvm_voltage_type;
|
||||
|
||||
/**
|
||||
* @brief pwc sleep enter type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter sleep mode */
|
||||
PWC_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter sleep mode */
|
||||
} pwc_sleep_enter_type;
|
||||
|
||||
/**
|
||||
* @brief pwc deep sleep enter type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_DEEP_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter deepsleep mode */
|
||||
PWC_DEEP_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter deepsleep mode */
|
||||
} pwc_deep_sleep_enter_type;
|
||||
|
||||
/**
|
||||
* @brief type define pwc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief pwc ctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 1; /* [0] */
|
||||
__IO uint32_t lpsel : 1; /* [1] */
|
||||
__IO uint32_t clswef : 1; /* [2] */
|
||||
__IO uint32_t clsef : 1; /* [3] */
|
||||
__IO uint32_t pvmen : 1; /* [4] */
|
||||
__IO uint32_t pvmsel : 3; /* [7:5] */
|
||||
__IO uint32_t bpwen : 1; /* [8] */
|
||||
__IO uint32_t reserved2 : 23;/* [31:9] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief pwc ctrlsts register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrlsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t swef : 1; /* [0] */
|
||||
__IO uint32_t sef : 1; /* [1] */
|
||||
__IO uint32_t pvmof : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 5; /* [7:3] */
|
||||
__IO uint32_t swpen : 1; /* [8] */
|
||||
__IO uint32_t reserved2 : 23;/* [31:9] */
|
||||
} ctrlsts_bit;
|
||||
};
|
||||
|
||||
} pwc_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define PWC ((pwc_type *) PWC_BASE)
|
||||
|
||||
/** @defgroup PWC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void pwc_reset(void);
|
||||
void pwc_battery_powered_domain_access(confirm_state new_state);
|
||||
void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
|
||||
void pwc_power_voltage_monitor_enable(confirm_state new_state);
|
||||
void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
|
||||
void pwc_flag_clear(uint32_t pwc_flag);
|
||||
flag_status pwc_flag_get(uint32_t pwc_flag);
|
||||
void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);
|
||||
void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter);
|
||||
void pwc_standby_mode_enter(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
940
libraries/drivers/inc/at32f413_tmr.h
Normal file
940
libraries/drivers/inc/at32f413_tmr.h
Normal file
@@ -0,0 +1,940 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_tmr.h
|
||||
* @brief at32f413 tmr header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F413_TMR_H
|
||||
#define __AT32F413_TMR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f413.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TMR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TMR_flags_definition
|
||||
* @brief tmr flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TMR_OVF_FLAG ((uint32_t)0x000001) /*!< tmr flag overflow */
|
||||
#define TMR_C1_FLAG ((uint32_t)0x000002) /*!< tmr flag channel 1 */
|
||||
#define TMR_C2_FLAG ((uint32_t)0x000004) /*!< tmr flag channel 2 */
|
||||
#define TMR_C3_FLAG ((uint32_t)0x000008) /*!< tmr flag channel 3 */
|
||||
#define TMR_C4_FLAG ((uint32_t)0x000010) /*!< tmr flag channel 4 */
|
||||
#define TMR_HALL_FLAG ((uint32_t)0x000020) /*!< tmr flag hall */
|
||||
#define TMR_TRIGGER_FLAG ((uint32_t)0x000040) /*!< tmr flag trigger */
|
||||
#define TMR_BRK_FLAG ((uint32_t)0x000080) /*!< tmr flag brake */
|
||||
#define TMR_C1_RECAPTURE_FLAG ((uint32_t)0x000200) /*!< tmr flag channel 1 recapture */
|
||||
#define TMR_C2_RECAPTURE_FLAG ((uint32_t)0x000400) /*!< tmr flag channel 2 recapture */
|
||||
#define TMR_C3_RECAPTURE_FLAG ((uint32_t)0x000800) /*!< tmr flag channel 3 recapture */
|
||||
#define TMR_C4_RECAPTURE_FLAG ((uint32_t)0x001000) /*!< tmr flag channel 4 recapture */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TMR_interrupt_select_type_definition
|
||||
* @brief tmr interrupt select type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TMR_OVF_INT ((uint32_t)0x000001) /*!< tmr interrupt overflow */
|
||||
#define TMR_C1_INT ((uint32_t)0x000002) /*!< tmr interrupt channel 1 */
|
||||
#define TMR_C2_INT ((uint32_t)0x000004) /*!< tmr interrupt channel 2 */
|
||||
#define TMR_C3_INT ((uint32_t)0x000008) /*!< tmr interrupt channel 3 */
|
||||
#define TMR_C4_INT ((uint32_t)0x000010) /*!< tmr interrupt channel 4 */
|
||||
#define TMR_HALL_INT ((uint32_t)0x000020) /*!< tmr interrupt hall */
|
||||
#define TMR_TRIGGER_INT ((uint32_t)0x000040) /*!< tmr interrupt trigger */
|
||||
#define TMR_BRK_INT ((uint32_t)0x000080) /*!< tmr interrupt brake */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TMR_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief tmr clock division type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_CLOCK_DIV1 = 0x00, /*!< tmr clock division 1 */
|
||||
TMR_CLOCK_DIV2 = 0x01, /*!< tmr clock division 2 */
|
||||
TMR_CLOCK_DIV4 = 0x02 /*!< tmr clock division 4 */
|
||||
} tmr_clock_division_type;
|
||||
|
||||
/**
|
||||
* @brief tmr counter mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_COUNT_UP = 0x00, /*!< tmr counter mode up */
|
||||
TMR_COUNT_DOWN = 0x01, /*!< tmr counter mode down */
|
||||
TMR_COUNT_TWO_WAY_1 = 0x02, /*!< tmr counter mode two way 1 */
|
||||
TMR_COUNT_TWO_WAY_2 = 0x04, /*!< tmr counter mode two way 2 */
|
||||
TMR_COUNT_TWO_WAY_3 = 0x06 /*!< tmr counter mode two way 3 */
|
||||
} tmr_count_mode_type;
|
||||
|
||||
/**
|
||||
* @brief tmr primary mode select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_PRIMARY_SEL_RESET = 0x00, /*!< tmr primary mode select reset */
|
||||
TMR_PRIMARY_SEL_ENABLE = 0x01, /*!< tmr primary mode select enable */
|
||||
TMR_PRIMARY_SEL_OVERFLOW = 0x02, /*!< tmr primary mode select overflow */
|
||||
TMR_PRIMARY_SEL_COMPARE = 0x03, /*!< tmr primary mode select compare */
|
||||
TMR_PRIMARY_SEL_C1ORAW = 0x04, /*!< tmr primary mode select c1oraw */
|
||||
TMR_PRIMARY_SEL_C2ORAW = 0x05, /*!< tmr primary mode select c2oraw */
|
||||
TMR_PRIMARY_SEL_C3ORAW = 0x06, /*!< tmr primary mode select c3oraw */
|
||||
TMR_PRIMARY_SEL_C4ORAW = 0x07 /*!< tmr primary mode select c4oraw */
|
||||
} tmr_primary_select_type;
|
||||
|
||||
/**
|
||||
* @brief tmr subordinate mode input select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_SUB_INPUT_SEL_IS0 = 0x00, /*!< subordinate mode input select is0 */
|
||||
TMR_SUB_INPUT_SEL_IS1 = 0x01, /*!< subordinate mode input select is1 */
|
||||
TMR_SUB_INPUT_SEL_IS2 = 0x02, /*!< subordinate mode input select is2 */
|
||||
TMR_SUB_INPUT_SEL_IS3 = 0x03, /*!< subordinate mode input select is3 */
|
||||
TMR_SUB_INPUT_SEL_C1INC = 0x04, /*!< subordinate mode input select c1inc */
|
||||
TMR_SUB_INPUT_SEL_C1DF1 = 0x05, /*!< subordinate mode input select c1df1 */
|
||||
TMR_SUB_INPUT_SEL_C2DF2 = 0x06, /*!< subordinate mode input select c2df2 */
|
||||
TMR_SUB_INPUT_SEL_EXTIN = 0x07 /*!< subordinate mode input select extin */
|
||||
} sub_tmr_input_sel_type;
|
||||
|
||||
/**
|
||||
* @brief tmr subordinate mode select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_SUB_MODE_DIABLE = 0x00, /*!< subordinate mode disable */
|
||||
TMR_SUB_ENCODER_MODE_A = 0x01, /*!< subordinate mode select encoder mode a */
|
||||
TMR_SUB_ENCODER_MODE_B = 0x02, /*!< subordinate mode select encoder mode b */
|
||||
TMR_SUB_ENCODER_MODE_C = 0x03, /*!< subordinate mode select encoder mode c */
|
||||
TMR_SUB_RESET_MODE = 0x04, /*!< subordinate mode select reset */
|
||||
TMR_SUB_HANG_MODE = 0x05, /*!< subordinate mode select hang */
|
||||
TMR_SUB_TRIGGER_MODE = 0x06, /*!< subordinate mode select trigger */
|
||||
TMR_SUB_EXTERNAL_CLOCK_MODE_A = 0x07 /*!< subordinate mode external clock mode a */
|
||||
} tmr_sub_mode_select_type;
|
||||
|
||||
/**
|
||||
* @brief tmr encoder mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_ENCODER_MODE_A = TMR_SUB_ENCODER_MODE_A, /*!< tmr encoder mode a */
|
||||
TMR_ENCODER_MODE_B = TMR_SUB_ENCODER_MODE_B, /*!< tmr encoder mode b */
|
||||
TMR_ENCODER_MODE_C = TMR_SUB_ENCODER_MODE_C /*!< tmr encoder mode c */
|
||||
} tmr_encoder_mode_type;
|
||||
|
||||
/**
|
||||
* @brief tmr output control mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_OUTPUT_CONTROL_OFF = 0x00, /*!< tmr output control mode off */
|
||||
TMR_OUTPUT_CONTROL_HIGH = 0x01, /*!< tmr output control mode high */
|
||||
TMR_OUTPUT_CONTROL_LOW = 0x02, /*!< tmr output control mode low */
|
||||
TMR_OUTPUT_CONTROL_SWITCH = 0x03, /*!< tmr output control mode switch */
|
||||
TMR_OUTPUT_CONTROL_FORCE_LOW = 0x04, /*!< tmr output control mode force low */
|
||||
TMR_OUTPUT_CONTROL_FORCE_HIGH = 0x05, /*!< tmr output control mode force high */
|
||||
TMR_OUTPUT_CONTROL_PWM_MODE_A = 0x06, /*!< tmr output control mode pwm a */
|
||||
TMR_OUTPUT_CONTROL_PWM_MODE_B = 0x07 /*!< tmr output control mode pwm b */
|
||||
} tmr_output_control_mode_type;
|
||||
|
||||
/**
|
||||
* @brief tmr force output type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_FORCE_OUTPUT_HIGH = TMR_OUTPUT_CONTROL_FORCE_HIGH, /*!< tmr force output high */
|
||||
TMR_FORCE_OUTPUT_LOW = TMR_OUTPUT_CONTROL_FORCE_LOW /*!< tmr force output low */
|
||||
} tmr_force_output_type;
|
||||
|
||||
/**
|
||||
* @brief tmr output channel polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_OUTPUT_ACTIVE_HIGH = 0x00, /*!< tmr output channel polarity high */
|
||||
TMR_OUTPUT_ACTIVE_LOW = 0x01 /*!< tmr output channel polarity low */
|
||||
} tmr_output_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief tmr input channel polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_INPUT_RISING_EDGE = 0x00, /*!< tmr input channel polarity rising */
|
||||
TMR_INPUT_FALLING_EDGE = 0x01, /*!< tmr input channel polarity falling */
|
||||
TMR_INPUT_BOTH_EDGE = 0x03 /*!< tmr input channel polarity both edge */
|
||||
} tmr_input_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief tmr channel select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_SELECT_CHANNEL_1 = 0x00, /*!< tmr channel select channel 1 */
|
||||
TMR_SELECT_CHANNEL_1C = 0x01, /*!< tmr channel select channel 1 complementary */
|
||||
TMR_SELECT_CHANNEL_2 = 0x02, /*!< tmr channel select channel 2 */
|
||||
TMR_SELECT_CHANNEL_2C = 0x03, /*!< tmr channel select channel 2 complementary */
|
||||
TMR_SELECT_CHANNEL_3 = 0x04, /*!< tmr channel select channel 3 */
|
||||
TMR_SELECT_CHANNEL_3C = 0x05, /*!< tmr channel select channel 3 complementary */
|
||||
TMR_SELECT_CHANNEL_4 = 0x06 /*!< tmr channel select channel 4 */
|
||||
} tmr_channel_select_type;
|
||||
|
||||
/**
|
||||
* @brief tmr channel1 input connected type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_CHANEL1_CONNECTED_C1IRAW = 0x00, /*!< channel1 pins is only connected to C1IRAW input */
|
||||
TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR = 0x01 /*!< channel1/2/3 pins are connected to C1IRAW input after xored */
|
||||
} tmr_channel1_input_connected_type;
|
||||
|
||||
/**
|
||||
* @brief tmr input channel mapped type channel direction
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */
|
||||
TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */
|
||||
TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */
|
||||
} tmr_input_direction_mapped_type;
|
||||
|
||||
/**
|
||||
* @brief tmr input divider type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_CHANNEL_INPUT_DIV_1 = 0x00, /*!< tmr channel input divider 1 */
|
||||
TMR_CHANNEL_INPUT_DIV_2 = 0x01, /*!< tmr channel input divider 2 */
|
||||
TMR_CHANNEL_INPUT_DIV_4 = 0x02, /*!< tmr channel input divider 4 */
|
||||
TMR_CHANNEL_INPUT_DIV_8 = 0x03 /*!< tmr channel input divider 8 */
|
||||
} tmr_channel_input_divider_type;
|
||||
|
||||
/**
|
||||
* @brief tmr dma request source select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_DMA_REQUEST_BY_CHANNEL = 0x00, /*!< tmr dma request source select channel */
|
||||
TMR_DMA_REQUEST_BY_OVERFLOW = 0x01 /*!< tmr dma request source select overflow */
|
||||
} tmr_dma_request_source_type;
|
||||
|
||||
/**
|
||||
* @brief tmr dma request type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_OVERFLOW_DMA_REQUEST = 0x00000100, /*!< tmr dma request select overflow */
|
||||
TMR_C1_DMA_REQUEST = 0x00000200, /*!< tmr dma request select channel 1 */
|
||||
TMR_C2_DMA_REQUEST = 0x00000400, /*!< tmr dma request select channel 2 */
|
||||
TMR_C3_DMA_REQUEST = 0x00000800, /*!< tmr dma request select channel 3 */
|
||||
TMR_C4_DMA_REQUEST = 0x00001000, /*!< tmr dma request select channel 4 */
|
||||
TMR_HALL_DMA_REQUEST = 0x00002000, /*!< tmr dma request select hall */
|
||||
TMR_TRIGGER_DMA_REQUEST = 0x00004000 /*!< tmr dma request select trigger */
|
||||
} tmr_dma_request_type;
|
||||
|
||||
/**
|
||||
* @brief tmr event triggered by software type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_OVERFLOW_SWTRIG = 0x00000001, /*!< tmr event triggered by software of overflow */
|
||||
TMR_C1_SWTRIG = 0x00000002, /*!< tmr event triggered by software of channel 1 */
|
||||
TMR_C2_SWTRIG = 0x00000004, /*!< tmr event triggered by software of channel 2 */
|
||||
TMR_C3_SWTRIG = 0x00000008, /*!< tmr event triggered by software of channel 3 */
|
||||
TMR_C4_SWTRIG = 0x00000010, /*!< tmr event triggered by software of channel 4 */
|
||||
TMR_HALL_SWTRIG = 0x00000020, /*!< tmr event triggered by software of hall */
|
||||
TMR_TRIGGER_SWTRIG = 0x00000040, /*!< tmr event triggered by software of trigger */
|
||||
TMR_BRK_SWTRIG = 0x00000080 /*!< tmr event triggered by software of brake */
|
||||
}tmr_event_trigger_type;
|
||||
|
||||
/**
|
||||
* @brief tmr polarity active type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_POLARITY_ACTIVE_HIGH = 0x00, /*!< tmr polarity active high */
|
||||
TMR_POLARITY_ACTIVE_LOW = 0x01, /*!< tmr polarity active low */
|
||||
TMR_POLARITY_ACTIVE_BOTH = 0x02 /*!< tmr polarity active both high ande low */
|
||||
}tmr_polarity_active_type;
|
||||
|
||||
/**
|
||||
* @brief tmr external signal divider type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_ES_FREQUENCY_DIV_1 = 0x00, /*!< tmr external signal frequency divider 1 */
|
||||
TMR_ES_FREQUENCY_DIV_2 = 0x01, /*!< tmr external signal frequency divider 2 */
|
||||
TMR_ES_FREQUENCY_DIV_4 = 0x02, /*!< tmr external signal frequency divider 4 */
|
||||
TMR_ES_FREQUENCY_DIV_8 = 0x03 /*!< tmr external signal frequency divider 8 */
|
||||
}tmr_external_signal_divider_type;
|
||||
|
||||
/**
|
||||
* @brief tmr external signal polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_ES_POLARITY_NON_INVERTED = 0x00, /*!< tmr external signal polarity non-inerted */
|
||||
TMR_ES_POLARITY_INVERTED = 0x01 /*!< tmr external signal polarity inerted */
|
||||
}tmr_external_signal_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief tmr dma transfer length type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_DMA_TRANSFER_1BYTE = 0x00, /*!< tmr dma transfer length 1 byte */
|
||||
TMR_DMA_TRANSFER_2BYTES = 0x01, /*!< tmr dma transfer length 2 bytes */
|
||||
TMR_DMA_TRANSFER_3BYTES = 0x02, /*!< tmr dma transfer length 3 bytes */
|
||||
TMR_DMA_TRANSFER_4BYTES = 0x03, /*!< tmr dma transfer length 4 bytes */
|
||||
TMR_DMA_TRANSFER_5BYTES = 0x04, /*!< tmr dma transfer length 5 bytes */
|
||||
TMR_DMA_TRANSFER_6BYTES = 0x05, /*!< tmr dma transfer length 6 bytes */
|
||||
TMR_DMA_TRANSFER_7BYTES = 0x06, /*!< tmr dma transfer length 7 bytes */
|
||||
TMR_DMA_TRANSFER_8BYTES = 0x07, /*!< tmr dma transfer length 8 bytes */
|
||||
TMR_DMA_TRANSFER_9BYTES = 0x08, /*!< tmr dma transfer length 9 bytes */
|
||||
TMR_DMA_TRANSFER_10BYTES = 0x09, /*!< tmr dma transfer length 10 bytes */
|
||||
TMR_DMA_TRANSFER_11BYTES = 0x0A, /*!< tmr dma transfer length 11 bytes */
|
||||
TMR_DMA_TRANSFER_12BYTES = 0x0B, /*!< tmr dma transfer length 12 bytes */
|
||||
TMR_DMA_TRANSFER_13BYTES = 0x0C, /*!< tmr dma transfer length 13 bytes */
|
||||
TMR_DMA_TRANSFER_14BYTES = 0x0D, /*!< tmr dma transfer length 14 bytes */
|
||||
TMR_DMA_TRANSFER_15BYTES = 0x0E, /*!< tmr dma transfer length 15 bytes */
|
||||
TMR_DMA_TRANSFER_16BYTES = 0x0F, /*!< tmr dma transfer length 16 bytes */
|
||||
TMR_DMA_TRANSFER_17BYTES = 0x10, /*!< tmr dma transfer length 17 bytes */
|
||||
TMR_DMA_TRANSFER_18BYTES = 0x11 /*!< tmr dma transfer length 18 bytes */
|
||||
}tmr_dma_transfer_length_type;
|
||||
|
||||
/**
|
||||
* @brief tmr dma base address type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_CTRL1_ADDRESS = 0x0000, /*!< tmr dma base address ctrl1 */
|
||||
TMR_CTRL2_ADDRESS = 0x0001, /*!< tmr dma base address ctrl2 */
|
||||
TMR_STCTRL_ADDRESS = 0x0002, /*!< tmr dma base address stctrl */
|
||||
TMR_IDEN_ADDRESS = 0x0003, /*!< tmr dma base address iden */
|
||||
TMR_ISTS_ADDRESS = 0x0004, /*!< tmr dma base address ists */
|
||||
TMR_SWEVT_ADDRESS = 0x0005, /*!< tmr dma base address swevt */
|
||||
TMR_CM1_ADDRESS = 0x0006, /*!< tmr dma base address cm1 */
|
||||
TMR_CM2_ADDRESS = 0x0007, /*!< tmr dma base address cm2 */
|
||||
TMR_CCTRL_ADDRESS = 0x0008, /*!< tmr dma base address cctrl */
|
||||
TMR_CVAL_ADDRESS = 0x0009, /*!< tmr dma base address cval */
|
||||
TMR_DIV_ADDRESS = 0x000A, /*!< tmr dma base address div */
|
||||
TMR_PR_ADDRESS = 0x000B, /*!< tmr dma base address pr */
|
||||
TMR_RPR_ADDRESS = 0x000C, /*!< tmr dma base address rpr */
|
||||
TMR_C1DT_ADDRESS = 0x000D, /*!< tmr dma base address c1dt */
|
||||
TMR_C2DT_ADDRESS = 0x000E, /*!< tmr dma base address c2dt */
|
||||
TMR_C3DT_ADDRESS = 0x000F, /*!< tmr dma base address c3dt */
|
||||
TMR_C4DT_ADDRESS = 0x0010, /*!< tmr dma base address c4dt */
|
||||
TMR_BRK_ADDRESS = 0x0011, /*!< tmr dma base address brake */
|
||||
TMR_DMACTRL_ADDRESS = 0x0012 /*!< tmr dma base address dmactrl */
|
||||
}tmr_dma_address_type;
|
||||
|
||||
/**
|
||||
* @brief tmr brk polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_BRK_INPUT_ACTIVE_LOW = 0x00, /*!< tmr brk input channel active low */
|
||||
TMR_BRK_INPUT_ACTIVE_HIGH = 0x01 /*!< tmr brk input channel active high */
|
||||
}tmr_brk_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief tmr write protect level type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_WP_OFF = 0x00, /*!< tmr write protect off */
|
||||
TMR_WP_LEVEL_3 = 0x01, /*!< tmr write protect level 3 */
|
||||
TMR_WP_LEVEL_2 = 0x02, /*!< tmr write protect level 2 */
|
||||
TMR_WP_LEVEL_1 = 0x03 /*!< tmr write protect level 1 */
|
||||
}tmr_wp_level_type;
|
||||
|
||||
/**
|
||||
* @brief tmr output config type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
tmr_output_control_mode_type oc_mode; /*!< output channel mode */
|
||||
confirm_state oc_idle_state; /*!< output channel idle state */
|
||||
confirm_state occ_idle_state; /*!< output channel complementary idle state */
|
||||
tmr_output_polarity_type oc_polarity; /*!< output channel polarity */
|
||||
tmr_output_polarity_type occ_polarity; /*!< output channel complementary polarity */
|
||||
confirm_state oc_output_state; /*!< output channel enable */
|
||||
confirm_state occ_output_state; /*!< output channel complementary enable */
|
||||
} tmr_output_config_type;
|
||||
|
||||
/**
|
||||
* @brief tmr input capture config type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
tmr_channel_select_type input_channel_select; /*!< tmr input channel select */
|
||||
tmr_input_polarity_type input_polarity_select; /*!< tmr input polarity select */
|
||||
tmr_input_direction_mapped_type input_mapped_select; /*!< tmr channel mapped direct or indirect */
|
||||
uint8_t input_filter_value; /*!< tmr channel filter value */
|
||||
} tmr_input_config_type;
|
||||
|
||||
/**
|
||||
* @brief tmr brkdt config type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t deadtime; /*!< dead-time generator setup */
|
||||
tmr_brk_polarity_type brk_polarity; /*!< tmr brake polarity */
|
||||
tmr_wp_level_type wp_level; /*!< write protect configuration */
|
||||
confirm_state auto_output_enable; /*!< automatic output enable */
|
||||
confirm_state fcsoen_state; /*!< frozen channel status when output enable */
|
||||
confirm_state fcsodis_state; /*!< frozen channel status when output disable */
|
||||
confirm_state brk_enable; /*!< tmr brk enale */
|
||||
} tmr_brkdt_config_type;
|
||||
|
||||
/**
|
||||
* @brief type define tmr register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief tmr ctrl1 register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmren : 1; /* [0] */
|
||||
__IO uint32_t ovfen : 1; /* [1] */
|
||||
__IO uint32_t ovfs : 1; /* [2] */
|
||||
__IO uint32_t ocmen : 1; /* [3] */
|
||||
__IO uint32_t cnt_dir : 3; /* [6:4] */
|
||||
__IO uint32_t prben : 1; /* [7] */
|
||||
__IO uint32_t clkdiv : 2; /* [9:8] */
|
||||
__IO uint32_t pmen : 1; /* [10] */
|
||||
__IO uint32_t reserved1 : 21;/* [31:11] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr ctrl2 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cbctrl : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 1; /* [1] */
|
||||
__IO uint32_t ccfs : 1; /* [2] */
|
||||
__IO uint32_t drs : 1; /* [3] */
|
||||
__IO uint32_t ptos : 3; /* [6:4] */
|
||||
__IO uint32_t c1insel : 1; /* [7] */
|
||||
__IO uint32_t c1ios : 1; /* [8] */
|
||||
__IO uint32_t c1cios : 1; /* [9] */
|
||||
__IO uint32_t c2ios : 1; /* [10] */
|
||||
__IO uint32_t c2cios : 1; /* [11] */
|
||||
__IO uint32_t c3ios : 1; /* [12] */
|
||||
__IO uint32_t c3cios : 1; /* [13] */
|
||||
__IO uint32_t c4ios : 1; /* [14] */
|
||||
__IO uint32_t reserved2 : 17;/* [31:15] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr smc register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t stctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t smsel : 3; /* [2:0] */
|
||||
__IO uint32_t reserved1 : 1; /* [3] */
|
||||
__IO uint32_t stis : 3; /* [6:4] */
|
||||
__IO uint32_t sts : 1; /* [7] */
|
||||
__IO uint32_t esf : 4; /* [11:8] */
|
||||
__IO uint32_t esdiv : 2; /* [13:12] */
|
||||
__IO uint32_t ecmben : 1; /* [14] */
|
||||
__IO uint32_t esp : 1; /* [15] */
|
||||
__IO uint32_t reserved2 : 16;/* [31:16] */
|
||||
} stctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr die register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t iden;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ovfien : 1; /* [0] */
|
||||
__IO uint32_t c1ien : 1; /* [1] */
|
||||
__IO uint32_t c2ien : 1; /* [2] */
|
||||
__IO uint32_t c3ien : 1; /* [3] */
|
||||
__IO uint32_t c4ien : 1; /* [4] */
|
||||
__IO uint32_t hallien : 1; /* [5] */
|
||||
__IO uint32_t tien : 1; /* [6] */
|
||||
__IO uint32_t brkie : 1; /* [7] */
|
||||
__IO uint32_t ovfden : 1; /* [8] */
|
||||
__IO uint32_t c1den : 1; /* [9] */
|
||||
__IO uint32_t c2den : 1; /* [10] */
|
||||
__IO uint32_t c3den : 1; /* [11] */
|
||||
__IO uint32_t c4den : 1; /* [12] */
|
||||
__IO uint32_t hallde : 1; /* [13] */
|
||||
__IO uint32_t tden : 1; /* [14] */
|
||||
__IO uint32_t reserved1 : 17;/* [31:15] */
|
||||
} iden_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr ists register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ists;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ovfif : 1; /* [0] */
|
||||
__IO uint32_t c1if : 1; /* [1] */
|
||||
__IO uint32_t c2if : 1; /* [2] */
|
||||
__IO uint32_t c3if : 1; /* [3] */
|
||||
__IO uint32_t c4if : 1; /* [4] */
|
||||
__IO uint32_t hallif : 1; /* [5] */
|
||||
__IO uint32_t trgif : 1; /* [6] */
|
||||
__IO uint32_t brkif : 1; /* [7] */
|
||||
__IO uint32_t reserved1 : 1; /* [8] */
|
||||
__IO uint32_t c1rf : 1; /* [9] */
|
||||
__IO uint32_t c2rf : 1; /* [10] */
|
||||
__IO uint32_t c3rf : 1; /* [11] */
|
||||
__IO uint32_t c4rf : 1; /* [12] */
|
||||
__IO uint32_t reserved2 : 19;/* [31:13] */
|
||||
} ists_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr eveg register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t swevt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ovfswtr : 1; /* [0] */
|
||||
__IO uint32_t c1swtr : 1; /* [1] */
|
||||
__IO uint32_t c2swtr : 1; /* [2] */
|
||||
__IO uint32_t c3swtr : 1; /* [3] */
|
||||
__IO uint32_t c4swtr : 1; /* [4] */
|
||||
__IO uint32_t hallswtr : 1; /* [5] */
|
||||
__IO uint32_t trgswtr : 1; /* [6] */
|
||||
__IO uint32_t brkswtr : 1; /* [7] */
|
||||
__IO uint32_t reserved : 24;/* [31:8] */
|
||||
} swevt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr ccm1 register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cm1;
|
||||
|
||||
/**
|
||||
* @brief channel mode
|
||||
*/
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c1c : 2; /* [1:0] */
|
||||
__IO uint32_t c1oien : 1; /* [2] */
|
||||
__IO uint32_t c1oben : 1; /* [3] */
|
||||
__IO uint32_t c1octrl : 3; /* [6:4] */
|
||||
__IO uint32_t c1osen : 1; /* [7] */
|
||||
__IO uint32_t c2c : 2; /* [9:8] */
|
||||
__IO uint32_t c2oien : 1; /* [10] */
|
||||
__IO uint32_t c2oben : 1; /* [11] */
|
||||
__IO uint32_t c2octrl : 3; /* [14:12] */
|
||||
__IO uint32_t c2osen : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} cm1_output_bit;
|
||||
|
||||
/**
|
||||
* @brief input capture mode
|
||||
*/
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c1c : 2; /* [1:0] */
|
||||
__IO uint32_t c1idiv : 2; /* [3:2] */
|
||||
__IO uint32_t c1df : 4; /* [7:4] */
|
||||
__IO uint32_t c2c : 2; /* [9:8] */
|
||||
__IO uint32_t c2idiv : 2; /* [11:10] */
|
||||
__IO uint32_t c2df : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} cm1_input_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr ccm2 register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cm2;
|
||||
|
||||
/**
|
||||
* @brief channel mode
|
||||
*/
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c3c : 2; /* [1:0] */
|
||||
__IO uint32_t c3oien : 1; /* [2] */
|
||||
__IO uint32_t c3oben : 1; /* [3] */
|
||||
__IO uint32_t c3octrl : 3; /* [6:4] */
|
||||
__IO uint32_t c3osen : 1; /* [7] */
|
||||
__IO uint32_t c4c : 2; /* [9:8] */
|
||||
__IO uint32_t c4oien : 1; /* [10] */
|
||||
__IO uint32_t c4oben : 1; /* [11] */
|
||||
__IO uint32_t c4octrl : 3; /* [14:12] */
|
||||
__IO uint32_t c4osen : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} cm2_output_bit;
|
||||
|
||||
/**
|
||||
* @brief input capture mode
|
||||
*/
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c3c : 2; /* [1:0] */
|
||||
__IO uint32_t c3idiv : 2; /* [3:2] */
|
||||
__IO uint32_t c3df : 4; /* [7:4] */
|
||||
__IO uint32_t c4c : 2; /* [9:8] */
|
||||
__IO uint32_t c4idiv : 2; /* [11:10] */
|
||||
__IO uint32_t c4df : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} cm2_input_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr cce register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
uint32_t cctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c1en : 1; /* [0] */
|
||||
__IO uint32_t c1p : 1; /* [1] */
|
||||
__IO uint32_t c1cen : 1; /* [2] */
|
||||
__IO uint32_t c1cp : 1; /* [3] */
|
||||
__IO uint32_t c2en : 1; /* [4] */
|
||||
__IO uint32_t c2p : 1; /* [5] */
|
||||
__IO uint32_t c2cen : 1; /* [6] */
|
||||
__IO uint32_t c2cp : 1; /* [7] */
|
||||
__IO uint32_t c3en : 1; /* [8] */
|
||||
__IO uint32_t c3p : 1; /* [9] */
|
||||
__IO uint32_t c3cen : 1; /* [10] */
|
||||
__IO uint32_t c3cp : 1; /* [11] */
|
||||
__IO uint32_t c4en : 1; /* [12] */
|
||||
__IO uint32_t c4p : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 18;/* [31:14] */
|
||||
} cctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr cnt register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cval;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cval : 32;/* [31:0] */
|
||||
} cval_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr div, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t div;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t div : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} div_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr pr register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pr : 32;/* [31:0] */
|
||||
} pr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr rpr register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rpr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rpr : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} rpr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr c1dt register, offset:0x34
|
||||
*/
|
||||
union
|
||||
{
|
||||
uint32_t c1dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c1dt : 32;/* [31:0] */
|
||||
} c1dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr c2dt register, offset:0x38
|
||||
*/
|
||||
union
|
||||
{
|
||||
uint32_t c2dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c2dt : 32;/* [31:0] */
|
||||
} c2dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr c3dt register, offset:0x3C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t c3dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c3dt : 32;/* [31:0] */
|
||||
} c3dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr c4dt register, offset:0x40
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t c4dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c4dt : 32;/* [31:0] */
|
||||
} c4dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr brk register, offset:0x44
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t brk;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dtc : 8; /* [7:0] */
|
||||
__IO uint32_t wpc : 2; /* [9:8] */
|
||||
__IO uint32_t fcsodis : 1; /* [10] */
|
||||
__IO uint32_t fcsoen : 1; /* [11] */
|
||||
__IO uint32_t brken : 1; /* [12] */
|
||||
__IO uint32_t brkv : 1; /* [13] */
|
||||
__IO uint32_t aoen : 1; /* [14] */
|
||||
__IO uint32_t oen : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} brk_bit;
|
||||
};
|
||||
/**
|
||||
* @brief tmr dmactrl register, offset:0x48
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dmactrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t addr : 5; /* [4:0] */
|
||||
__IO uint32_t reserved1 : 3; /* [7:5] */
|
||||
__IO uint32_t dtb : 5; /* [12:8] */
|
||||
__IO uint32_t reserved2 : 19;/* [31:13] */
|
||||
} dmactrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr dmadt register, offset:0x4C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dmadt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dmadt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} dmadt_bit;
|
||||
};
|
||||
|
||||
} tmr_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define TMR1 ((tmr_type *) TMR1_BASE)
|
||||
#define TMR2 ((tmr_type *) TMR2_BASE)
|
||||
#define TMR3 ((tmr_type *) TMR3_BASE)
|
||||
#define TMR4 ((tmr_type *) TMR4_BASE)
|
||||
#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \
|
||||
defined (AT32F413Kx)
|
||||
#define TMR5 ((tmr_type *) TMR5_BASE)
|
||||
#if defined (AT32F413CCU7) || defined (AT32F413CCT7) || defined (AT32F413RCT7)
|
||||
#define TMR8 ((tmr_type *) TMR8_BASE)
|
||||
#endif
|
||||
#define TMR9 ((tmr_type *) TMR9_BASE)
|
||||
#define TMR10 ((tmr_type *) TMR10_BASE)
|
||||
#define TMR11 ((tmr_type *) TMR11_BASE)
|
||||
#endif
|
||||
|
||||
/** @defgroup TMR_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void tmr_reset(tmr_type *tmr_x);
|
||||
void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct);
|
||||
void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct);
|
||||
void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct);
|
||||
void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div);
|
||||
void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div);
|
||||
void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir);
|
||||
void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value);
|
||||
void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value);
|
||||
uint32_t tmr_counter_value_get(tmr_type *tmr_x);
|
||||
void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value);
|
||||
uint32_t tmr_div_value_get(tmr_type *tmr_x);
|
||||
void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
tmr_output_config_type *tmr_output_struct);
|
||||
void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
tmr_output_control_mode_type oc_mode);
|
||||
void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value);
|
||||
uint32_t tmr_period_value_get(tmr_type *tmr_x);
|
||||
void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
uint32_t tmr_channel_value);
|
||||
uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel);
|
||||
void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
confirm_state new_state);
|
||||
void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
confirm_state new_state);
|
||||
void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
confirm_state new_state);
|
||||
void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
|
||||
tmr_channel_input_divider_type divider_factor);
|
||||
void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state);
|
||||
void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
uint16_t filter_value);
|
||||
void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
|
||||
tmr_channel_input_divider_type divider_factor);
|
||||
void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect);
|
||||
void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
tmr_channel_input_divider_type divider_factor);
|
||||
void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode);
|
||||
void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode);
|
||||
void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select);
|
||||
void tmr_hall_select(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select);
|
||||
void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state);
|
||||
void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state);
|
||||
flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
|
||||
flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
|
||||
void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag);
|
||||
void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event);
|
||||
void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_internal_clock_set(tmr_type *tmr_x);
|
||||
|
||||
void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
tmr_polarity_active_type oc_polarity);
|
||||
void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
|
||||
tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
|
||||
void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
|
||||
tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
|
||||
void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
|
||||
tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
|
||||
void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type \
|
||||
ic1_polarity, tmr_input_polarity_type ic2_polarity);
|
||||
void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
tmr_force_output_type force_output);
|
||||
void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
|
||||
tmr_dma_address_type dma_base_address);
|
||||
void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
378
libraries/drivers/inc/at32f413_usart.h
Normal file
378
libraries/drivers/inc/at32f413_usart.h
Normal file
@@ -0,0 +1,378 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_usart.h
|
||||
* @brief at32f413 usart header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F413_USART_H
|
||||
#define __AT32F413_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f413.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USART_flags_definition
|
||||
* @brief usart flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_PERR_FLAG ((uint32_t)0x00000001) /*!< usart parity error flag */
|
||||
#define USART_FERR_FLAG ((uint32_t)0x00000002) /*!< usart framing error flag */
|
||||
#define USART_NERR_FLAG ((uint32_t)0x00000004) /*!< usart noise error flag */
|
||||
#define USART_ROERR_FLAG ((uint32_t)0x00000008) /*!< usart receiver overflow error flag */
|
||||
#define USART_IDLEF_FLAG ((uint32_t)0x00000010) /*!< usart idle flag */
|
||||
#define USART_RDBF_FLAG ((uint32_t)0x00000020) /*!< usart receive data buffer full flag */
|
||||
#define USART_TDC_FLAG ((uint32_t)0x00000040) /*!< usart transmit data complete flag */
|
||||
#define USART_TDBE_FLAG ((uint32_t)0x00000080) /*!< usart transmit data buffer empty flag */
|
||||
#define USART_BFF_FLAG ((uint32_t)0x00000100) /*!< usart break frame flag */
|
||||
#define USART_CTSCF_FLAG ((uint32_t)0x00000200) /*!< usart cts change flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_interrupts_definition
|
||||
* @brief usart interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IDLE_INT MAKE_VALUE(0x0C,0x04) /*!< usart idle interrupt */
|
||||
#define USART_RDBF_INT MAKE_VALUE(0x0C,0x05) /*!< usart receive data buffer full interrupt */
|
||||
#define USART_TDC_INT MAKE_VALUE(0x0C,0x06) /*!< usart transmit data complete interrupt */
|
||||
#define USART_TDBE_INT MAKE_VALUE(0x0C,0x07) /*!< usart transmit data buffer empty interrupt */
|
||||
#define USART_PERR_INT MAKE_VALUE(0x0C,0x08) /*!< usart parity error interrupt */
|
||||
#define USART_BF_INT MAKE_VALUE(0x10,0x06) /*!< usart break frame interrupt */
|
||||
#define USART_ERR_INT MAKE_VALUE(0x14,0x00) /*!< usart error interrupt */
|
||||
#define USART_CTSCF_INT MAKE_VALUE(0x14,0x0A) /*!< usart cts change interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief usart parity selection type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_PARITY_NONE = 0x00, /*!< usart no parity */
|
||||
USART_PARITY_EVEN = 0x01, /*!< usart even parity */
|
||||
USART_PARITY_ODD = 0x02 /*!< usart odd parity */
|
||||
} usart_parity_selection_type;
|
||||
|
||||
/**
|
||||
* @brief usart wakeup mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_WAKEUP_BY_IDLE_FRAME = 0x00, /*!< usart wakeup by idle frame */
|
||||
USART_WAKEUP_BY_MATCHING_ID = 0x01 /*!< usart wakeup by matching id */
|
||||
} usart_wakeup_mode_type;
|
||||
|
||||
/**
|
||||
* @brief usart data bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_DATA_8BITS = 0x00, /*!< usart data size is 8 bits */
|
||||
USART_DATA_9BITS = 0x01 /*!< usart data size is 9 bits */
|
||||
} usart_data_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart break frame bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_BREAK_10BITS = 0x00, /*!< usart lin mode berak frame detection 10 bits */
|
||||
USART_BREAK_11BITS = 0x01 /*!< usart lin mode berak frame detection 11 bits */
|
||||
} usart_break_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart phase of the clock type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CLOCK_PHASE_1EDGE = 0x00, /*!< usart data capture is done on the clock leading edge */
|
||||
USART_CLOCK_PHASE_2EDGE = 0x01 /*!< usart data capture is done on the clock trailing edge */
|
||||
} usart_clock_phase_type;
|
||||
|
||||
/**
|
||||
* @brief usart polarity of the clock type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CLOCK_POLARITY_LOW = 0x00, /*!< usart clock stay low level outside transmission window */
|
||||
USART_CLOCK_POLARITY_HIGH = 0x01 /*!< usart clock stay high level outside transmission window */
|
||||
} usart_clock_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief usart last bit clock pulse type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CLOCK_LAST_BIT_NONE = 0x00, /*!< usart clock pulse of the last data bit is not outputted */
|
||||
USART_CLOCK_LAST_BIT_OUTPUT = 0x01 /*!< usart clock pulse of the last data bit is outputted */
|
||||
} usart_lbcp_type;
|
||||
|
||||
/**
|
||||
* @brief usart stop bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_STOP_1_BIT = 0x00, /*!< usart stop bits num is 1 */
|
||||
USART_STOP_0_5_BIT = 0x01, /*!< usart stop bits num is 0.5 */
|
||||
USART_STOP_2_BIT = 0x02, /*!< usart stop bits num is 2 */
|
||||
USART_STOP_1_5_BIT = 0x03 /*!< usart stop bits num is 1.5 */
|
||||
} usart_stop_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart hardware flow control type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_HARDWARE_FLOW_NONE = 0x00, /*!< usart without hardware flow */
|
||||
USART_HARDWARE_FLOW_RTS = 0x01, /*!< usart hardware flow only rts */
|
||||
USART_HARDWARE_FLOW_CTS = 0x02, /*!< usart hardware flow only cts */
|
||||
USART_HARDWARE_FLOW_RTS_CTS = 0x03 /*!< usart hardware flow both rts and cts */
|
||||
} usart_hardware_flow_control_type;
|
||||
|
||||
/**
|
||||
* @brief type define usart register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief usart sts register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t perr : 1; /* [0] */
|
||||
__IO uint32_t ferr : 1; /* [1] */
|
||||
__IO uint32_t nerr : 1; /* [2] */
|
||||
__IO uint32_t roerr : 1; /* [3] */
|
||||
__IO uint32_t idlef : 1; /* [4] */
|
||||
__IO uint32_t rdbf : 1; /* [5] */
|
||||
__IO uint32_t tdc : 1; /* [6] */
|
||||
__IO uint32_t tdbe : 1; /* [7] */
|
||||
__IO uint32_t bff : 1; /* [8] */
|
||||
__IO uint32_t ctscf : 1; /* [9] */
|
||||
__IO uint32_t reserved1 : 22;/* [31:10] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart dt register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 9; /* [8:0] */
|
||||
__IO uint32_t reserved1 : 23;/* [31:9] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart baudr register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t baudr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t div : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} baudr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart ctrl1 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t sbf : 1; /* [0] */
|
||||
__IO uint32_t rm : 1; /* [1] */
|
||||
__IO uint32_t ren : 1; /* [2] */
|
||||
__IO uint32_t ten : 1; /* [3] */
|
||||
__IO uint32_t idleien : 1; /* [4] */
|
||||
__IO uint32_t rdbfien : 1; /* [5] */
|
||||
__IO uint32_t tdcien : 1; /* [6] */
|
||||
__IO uint32_t tdbeien : 1; /* [7] */
|
||||
__IO uint32_t perrien : 1; /* [8] */
|
||||
__IO uint32_t psel : 1; /* [9] */
|
||||
__IO uint32_t pen : 1; /* [10] */
|
||||
__IO uint32_t wum : 1; /* [11] */
|
||||
__IO uint32_t dbn : 1; /* [12] */
|
||||
__IO uint32_t uen : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 18;/* [31:14] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart ctrl2 register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t id : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 1; /* [4] */
|
||||
__IO uint32_t bfbn : 1; /* [5] */
|
||||
__IO uint32_t bfien : 1; /* [6] */
|
||||
__IO uint32_t reserved2 : 1; /* [7] */
|
||||
__IO uint32_t lbcp : 1; /* [8] */
|
||||
__IO uint32_t clkpha : 1; /* [9] */
|
||||
__IO uint32_t clkpol : 1; /* [10] */
|
||||
__IO uint32_t clken : 1; /* [11] */
|
||||
__IO uint32_t stopbn : 2; /* [13:12] */
|
||||
__IO uint32_t linen : 1; /* [14] */
|
||||
__IO uint32_t reserved3 : 17;/* [31:15] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart ctrl3 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t errien : 1; /* [0] */
|
||||
__IO uint32_t irdaen : 1; /* [1] */
|
||||
__IO uint32_t irdalp : 1; /* [2] */
|
||||
__IO uint32_t slben : 1; /* [3] */
|
||||
__IO uint32_t scnacken : 1; /* [4] */
|
||||
__IO uint32_t scmen : 1; /* [5] */
|
||||
__IO uint32_t dmaren : 1; /* [6] */
|
||||
__IO uint32_t dmaten : 1; /* [7] */
|
||||
__IO uint32_t rtsen : 1; /* [8] */
|
||||
__IO uint32_t ctsen : 1; /* [9] */
|
||||
__IO uint32_t ctscfien : 1; /* [10] */
|
||||
__IO uint32_t reserved1 : 21;/* [31:11] */
|
||||
} ctrl3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart gdiv register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t gdiv;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t isdiv : 8; /* [7:0] */
|
||||
__IO uint32_t scgt : 8; /* [15:8] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} gdiv_bit;
|
||||
};
|
||||
} usart_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define USART1 ((usart_type *) USART1_BASE)
|
||||
#define USART2 ((usart_type *) USART2_BASE)
|
||||
#if defined (AT32F413Rx) || defined (AT32F413Cx) || defined (AT32FEBKC8T7)
|
||||
#define USART3 ((usart_type *) USART3_BASE)
|
||||
#endif
|
||||
#if defined (AT32F413Rx)
|
||||
#define UART4 ((usart_type *) UART4_BASE)
|
||||
#define UART5 ((usart_type *) UART5_BASE)
|
||||
#endif
|
||||
|
||||
/** @defgroup USART_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void usart_reset(usart_type* usart_x);
|
||||
void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit);
|
||||
void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity);
|
||||
void usart_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_receiver_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb);
|
||||
void usart_clock_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state);
|
||||
void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id);
|
||||
void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode);
|
||||
void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit);
|
||||
void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_data_transmit(usart_type* usart_x, uint16_t data);
|
||||
uint16_t usart_data_receive(usart_type* usart_x);
|
||||
void usart_break_send(usart_type* usart_x);
|
||||
void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val);
|
||||
void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val);
|
||||
void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
|
||||
flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
|
||||
flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag);
|
||||
void usart_flag_clear(usart_type* usart_x, uint32_t flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
1246
libraries/drivers/src/at32f413_can.c
Normal file
1246
libraries/drivers/src/at32f413_can.c
Normal file
File diff suppressed because it is too large
Load Diff
881
libraries/drivers/src/at32f413_crm.c
Normal file
881
libraries/drivers/src/at32f413_crm.c
Normal file
@@ -0,0 +1,881 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_crm.c
|
||||
* @brief contains all the functions for the crm firmware library
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#include "at32f413_conf.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRM
|
||||
* @brief CRM driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef CRM_MODULE_ENABLED
|
||||
|
||||
/** @defgroup CRM_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief reset the crm register
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void crm_reset(void)
|
||||
{
|
||||
/* reset the crm clock configuration to the default reset state(for debug purpose) */
|
||||
/* set hicken bit */
|
||||
CRM->ctrl_bit.hicken = TRUE;
|
||||
|
||||
/* wait hick stable */
|
||||
while(CRM->ctrl_bit.hickstbl != SET);
|
||||
|
||||
/* hick used as system clock */
|
||||
CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
|
||||
|
||||
/* wait sclk switch status */
|
||||
while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
|
||||
|
||||
/* reset hexten, hextbyps, cfden and pllen bits */
|
||||
CRM->ctrl &= ~(0x010D0000U);
|
||||
|
||||
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
|
||||
clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */
|
||||
CRM->cfg = 0;
|
||||
|
||||
/* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
|
||||
CRM->misc1 = 0;
|
||||
|
||||
/* disable all interrupts enable and clear pending bits */
|
||||
CRM->clkint = 0x009F0000;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable crm low speed external crystal bypass
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void crm_lext_bypass(confirm_state new_state)
|
||||
{
|
||||
CRM->bpdc_bit.lextbyps = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable crm high speed external crystal bypass
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void crm_hext_bypass(confirm_state new_state)
|
||||
{
|
||||
CRM->ctrl_bit.hextbyps = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get crm flag status
|
||||
* @param flag
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_HICK_STABLE_FLAG
|
||||
* - CRM_HEXT_STABLE_FLAG
|
||||
* - CRM_PLL_STABLE_FLAG
|
||||
* - CRM_LEXT_STABLE_FLAG
|
||||
* - CRM_LICK_STABLE_FLAG
|
||||
* - CRM_NRST_RESET_FLAG
|
||||
* - CRM_POR_RESET_FLAG
|
||||
* - CRM_SW_RESET_FLAG
|
||||
* - CRM_WDT_RESET_FLAG
|
||||
* - CRM_WWDT_RESET_FLAG
|
||||
* - CRM_LOWPOWER_RESET_FLAG
|
||||
* interrupt flag:
|
||||
* - CRM_LICK_READY_INT_FLAG
|
||||
* - CRM_LEXT_READY_INT_FLAG
|
||||
* - CRM_HICK_READY_INT_FLAG
|
||||
* - CRM_HEXT_READY_INT_FLAG
|
||||
* - CRM_PLL_READY_INT_FLAG
|
||||
* - CRM_CLOCK_FAILURE_INT_FLAG
|
||||
* @retval flag_status (SET or RESET)
|
||||
*/
|
||||
flag_status crm_flag_get(uint32_t flag)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
if((CRM_REG(flag) & CRM_REG_BIT(flag)) != CRM_REG_BIT(flag))
|
||||
{
|
||||
status = RESET;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get crm interrupt flag status
|
||||
* @param flag
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_LICK_READY_INT_FLAG
|
||||
* - CRM_LEXT_READY_INT_FLAG
|
||||
* - CRM_HICK_READY_INT_FLAG
|
||||
* - CRM_HEXT_READY_INT_FLAG
|
||||
* - CRM_PLL_READY_INT_FLAG
|
||||
* - CRM_CLOCK_FAILURE_INT_FLAG
|
||||
* @retval flag_status (SET or RESET)
|
||||
*/
|
||||
flag_status crm_interrupt_flag_get(uint32_t flag)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
switch(flag)
|
||||
{
|
||||
case CRM_LICK_READY_INT_FLAG:
|
||||
if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case CRM_LEXT_READY_INT_FLAG:
|
||||
if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case CRM_HICK_READY_INT_FLAG:
|
||||
if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case CRM_HEXT_READY_INT_FLAG:
|
||||
if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case CRM_PLL_READY_INT_FLAG:
|
||||
if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case CRM_CLOCK_FAILURE_INT_FLAG:
|
||||
if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief wait for hext stable
|
||||
* @param none
|
||||
* @retval error_status (ERROR or SUCCESS)
|
||||
*/
|
||||
error_status crm_hext_stable_wait(void)
|
||||
{
|
||||
uint32_t stable_cnt = 0;
|
||||
error_status status = ERROR;
|
||||
|
||||
while((crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET) && (stable_cnt < HEXT_STARTUP_TIMEOUT))
|
||||
{
|
||||
stable_cnt ++;
|
||||
}
|
||||
|
||||
if(crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = SUCCESS;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set the hick trimming value
|
||||
* @param trim_value (0x00~0x3F)
|
||||
* @retval none
|
||||
*/
|
||||
void crm_hick_clock_trimming_set(uint8_t trim_value)
|
||||
{
|
||||
CRM->ctrl_bit.hicktrim = trim_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set the crm calibration value
|
||||
* @param cali_value (0x00~0xFF)
|
||||
* @retval none
|
||||
*/
|
||||
void crm_hick_clock_calibration_set(uint8_t cali_value)
|
||||
{
|
||||
/* enable write hick calibration */
|
||||
CRM->misc1_bit.hickcal_key = 0x5A;
|
||||
|
||||
/* write hick calibration value */
|
||||
CRM->ctrl_bit.hickcal = cali_value;
|
||||
|
||||
/* disable write hick calibration */
|
||||
CRM->misc1_bit.hickcal_key = 0x0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the peripheral clock
|
||||
* @param value
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_DMA1_PERIPH_CLOCK - CRM_DMA2_PERIPH_CLOCK - CRM_CRC_PERIPH_CLOCK - CRM_SDIO1_PERIPH_CLOCK
|
||||
* - CRM_IOMUX_PERIPH_CLOCK - CRM_GPIOA_PERIPH_CLOCK - CRM_GPIOB_PERIPH_CLOCK - CRM_GPIOC_PERIPH_CLOCK
|
||||
* - CRM_GPIOD_PERIPH_CLOCK - CRM_GPIOF_PERIPH_CLOCK - CRM_ADC1_PERIPH_CLOCK - CRM_ADC2_PERIPH_CLOCK
|
||||
* - CRM_TMR1_PERIPH_CLOCK - CRM_SPI1_PERIPH_CLOCK - CRM_TMR8_PERIPH_CLOCK - CRM_USART1_PERIPH_CLOCK
|
||||
* - CRM_TMR9_PERIPH_CLOCK - CRM_TMR10_PERIPH_CLOCK - CRM_TMR11_PERIPH_CLOCK - CRM_ACC_PERIPH_CLOCK
|
||||
* - CRM_TMR3_PERIPH_CLOCK - CRM_TMR4_PERIPH_CLOCK - CRM_TMR5_PERIPH_CLOCK - CRM_WWDT_PERIPH_CLOCK
|
||||
* - CRM_SPI2_PERIPH_CLOCK - CRM_USART2_PERIPH_CLOCK - CRM_USART3_PERIPH_CLOCK - CRM_UART4_PERIPH_CLOCK
|
||||
* - CRM_UART5_PERIPH_CLOCK - CRM_I2C1_PERIPH_CLOCK - CRM_I2C2_PERIPH_CLOCK - CRM_USB_PERIPH_CLOCK
|
||||
* - CRM_CAN1_PERIPH_CLOCK - CRM_BPR_PERIPH_CLOCK - CRM_PWC_PERIPH_CLOCK - CRM_CAN2_PERIPH_CLOCK
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state)
|
||||
{
|
||||
/* enable periph clock */
|
||||
if(TRUE == new_state)
|
||||
{
|
||||
CRM_REG(value) |= CRM_REG_BIT(value);
|
||||
}
|
||||
/* disable periph clock */
|
||||
else
|
||||
{
|
||||
CRM_REG(value) &= ~(CRM_REG_BIT(value));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the peripheral reset
|
||||
* @param value
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_IOMUX_PERIPH_RESET - CRM_EXINT_PERIPH_RESET - CRM_GPIOA_PERIPH_RESET - CRM_GPIOB_PERIPH_RESET
|
||||
* - CRM_GPIOC_PERIPH_RESET - CRM_GPIOD_PERIPH_RESET - CRM_GPIOF_PERIPH_RESET - CRM_ADC1_PERIPH_RESET
|
||||
* - CRM_ADC2_PERIPH_RESET - CRM_TMR1_PERIPH_RESET - CRM_SPI1_PERIPH_RESET - CRM_TMR8_PERIPH_RESET
|
||||
* - CRM_USART1_PERIPH_RESET - CRM_TMR9_PERIPH_RESET - CRM_TMR10_PERIPH_RESET - CRM_TMR11_PERIPH_RESET
|
||||
* - CRM_ACC_PERIPH_RESET - CRM_TMR2_PERIPH_RESET - CRM_TMR3_PERIPH_RESET - CRM_TMR4_PERIPH_RESET
|
||||
* - CRM_TMR5_PERIPH_RESET - CRM_WWDT_PERIPH_RESET - CRM_SPI2_PERIPH_RESET - CRM_USART2_PERIPH_RESET
|
||||
* - CRM_USART3_PERIPH_RESET - CRM_UART4_PERIPH_RESET - CRM_UART5_PERIPH_RESET - CRM_I2C1_PERIPH_RESET
|
||||
* - CRM_I2C2_PERIPH_RESET - CRM_USB_PERIPH_RESET - CRM_CAN1_PERIPH_RESET - CRM_BPR_PERIPH_RESET
|
||||
* - CRM_PWC_PERIPH_RESET - CRM_CAN2_PERIPH_RESET
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state)
|
||||
{
|
||||
/* enable periph reset */
|
||||
if(new_state == TRUE)
|
||||
{
|
||||
CRM_REG(value) |= (CRM_REG_BIT(value));
|
||||
}
|
||||
/* disable periph reset */
|
||||
else
|
||||
{
|
||||
CRM_REG(value) &= ~(CRM_REG_BIT(value));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the peripheral clock in sleep mode
|
||||
* @param value
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_SRAM_PERIPH_CLOCK_SLEEP_MODE
|
||||
* - CRM_FLASH_PERIPH_CLOCK_SLEEP_MODE
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void crm_periph_sleep_mode_clock_enable(crm_periph_clock_sleepmd_type value, confirm_state new_state)
|
||||
{
|
||||
/* enable periph clock in sleep mode */
|
||||
if(new_state == TRUE)
|
||||
{
|
||||
CRM_REG(value) |= (CRM_REG_BIT(value));
|
||||
}
|
||||
/* disable perph clock in sleep mode */
|
||||
else
|
||||
{
|
||||
CRM_REG(value) &= ~(CRM_REG_BIT(value));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the crm clock source
|
||||
* @param source
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_CLOCK_SOURCE_HICK
|
||||
* - CRM_CLOCK_SOURCE_HEXT
|
||||
* - CRM_CLOCK_SOURCE_PLL
|
||||
* - CRM_CLOCK_SOURCE_LEXT
|
||||
* - CRM_CLOCK_SOURCE_LICK
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state)
|
||||
{
|
||||
switch(source)
|
||||
{
|
||||
case CRM_CLOCK_SOURCE_HICK:
|
||||
CRM->ctrl_bit.hicken = new_state;
|
||||
break;
|
||||
case CRM_CLOCK_SOURCE_HEXT:
|
||||
CRM->ctrl_bit.hexten = new_state;
|
||||
break;
|
||||
case CRM_CLOCK_SOURCE_PLL:
|
||||
CRM->ctrl_bit.pllen = new_state;
|
||||
break;
|
||||
case CRM_CLOCK_SOURCE_LEXT:
|
||||
CRM->bpdc_bit.lexten = new_state;
|
||||
break;
|
||||
case CRM_CLOCK_SOURCE_LICK:
|
||||
CRM->ctrlsts_bit.licken = new_state;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear the crm reset flags
|
||||
* @param flag
|
||||
* this parameter can be one of the following values:
|
||||
* reset flag:
|
||||
* - CRM_NRST_RESET_FLAG
|
||||
* - CRM_POR_RESET_FLAG
|
||||
* - CRM_SW_RESET_FLAG
|
||||
* - CRM_WDT_RESET_FLAG
|
||||
* - CRM_WWDT_RESET_FLAG
|
||||
* - CRM_LOWPOWER_RESET_FLAG
|
||||
* - CRM_ALL_RESET_FLAG
|
||||
* interrupt flag:
|
||||
* - CRM_LICK_READY_INT_FLAG
|
||||
* - CRM_LEXT_READY_INT_FLAG
|
||||
* - CRM_HICK_READY_INT_FLAG
|
||||
* - CRM_HEXT_READY_INT_FLAG
|
||||
* - CRM_PLL_READY_INT_FLAG
|
||||
* - CRM_CLOCK_FAILURE_INT_FLAG
|
||||
* @retval none
|
||||
*/
|
||||
void crm_flag_clear(uint32_t flag)
|
||||
{
|
||||
switch(flag)
|
||||
{
|
||||
case CRM_NRST_RESET_FLAG:
|
||||
case CRM_POR_RESET_FLAG:
|
||||
case CRM_SW_RESET_FLAG:
|
||||
case CRM_WDT_RESET_FLAG:
|
||||
case CRM_WWDT_RESET_FLAG:
|
||||
case CRM_LOWPOWER_RESET_FLAG:
|
||||
case CRM_ALL_RESET_FLAG:
|
||||
CRM->ctrlsts_bit.rstfc = TRUE;
|
||||
while(CRM->ctrlsts_bit.rstfc == TRUE);
|
||||
break;
|
||||
case CRM_LICK_READY_INT_FLAG:
|
||||
CRM->clkint_bit.lickstblfc = TRUE;
|
||||
break;
|
||||
case CRM_LEXT_READY_INT_FLAG:
|
||||
CRM->clkint_bit.lextstblfc = TRUE;
|
||||
break;
|
||||
case CRM_HICK_READY_INT_FLAG:
|
||||
CRM->clkint_bit.hickstblfc = TRUE;
|
||||
break;
|
||||
case CRM_HEXT_READY_INT_FLAG:
|
||||
CRM->clkint_bit.hextstblfc = TRUE;
|
||||
break;
|
||||
case CRM_PLL_READY_INT_FLAG:
|
||||
CRM->clkint_bit.pllstblfc = TRUE;
|
||||
break;
|
||||
case CRM_CLOCK_FAILURE_INT_FLAG:
|
||||
CRM->clkint_bit.cfdfc = TRUE;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief select rtc clock
|
||||
* @param value
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_RTC_CLOCK_LEXT
|
||||
* - CRM_RTC_CLOCK_LICK
|
||||
* - CRM_RTC_CLOCK_HEXT_DIV
|
||||
* @retval none
|
||||
*/
|
||||
void crm_rtc_clock_select(crm_rtc_clock_type value)
|
||||
{
|
||||
CRM->bpdc_bit.rtcsel = value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable rtc
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void crm_rtc_clock_enable(confirm_state new_state)
|
||||
{
|
||||
CRM->bpdc_bit.rtcen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set crm ahb division
|
||||
* @param value
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_AHB_DIV_1
|
||||
* - CRM_AHB_DIV_2
|
||||
* - CRM_AHB_DIV_4
|
||||
* - CRM_AHB_DIV_8
|
||||
* - CRM_AHB_DIV_16
|
||||
* - CRM_AHB_DIV_64
|
||||
* - CRM_AHB_DIV_128
|
||||
* - CRM_AHB_DIV_256
|
||||
* - CRM_AHB_DIV_512
|
||||
* @retval none
|
||||
*/
|
||||
void crm_ahb_div_set(crm_ahb_div_type value)
|
||||
{
|
||||
CRM->cfg_bit.ahbdiv = value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set crm apb1 division
|
||||
* @note the maximum frequency of APB1/APB2 clock is 100 MHz
|
||||
* @param value
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_APB1_DIV_1
|
||||
* - CRM_APB1_DIV_2
|
||||
* - CRM_APB1_DIV_4
|
||||
* - CRM_APB1_DIV_8
|
||||
* - CRM_APB1_DIV_16
|
||||
* @retval none
|
||||
*/
|
||||
void crm_apb1_div_set(crm_apb1_div_type value)
|
||||
{
|
||||
CRM->cfg_bit.apb1div = value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set crm apb2 division
|
||||
* @note the maximum frequency of APB1/APB2 clock is 100 MHz
|
||||
* @param value
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_APB2_DIV_1
|
||||
* - CRM_APB2_DIV_2
|
||||
* - CRM_APB2_DIV_4
|
||||
* - CRM_APB2_DIV_8
|
||||
* - CRM_APB2_DIV_16
|
||||
* @retval none
|
||||
*/
|
||||
void crm_apb2_div_set(crm_apb2_div_type value)
|
||||
{
|
||||
CRM->cfg_bit.apb2div = value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set crm adc division
|
||||
* @param value
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_ADC_DIV_2
|
||||
* - CRM_ADC_DIV_4
|
||||
* - CRM_ADC_DIV_6
|
||||
* - CRM_ADC_DIV_8
|
||||
* - CRM_ADC_DIV_12
|
||||
* - CRM_ADC_DIV_16
|
||||
* @retval none
|
||||
*/
|
||||
void crm_adc_clock_div_set(crm_adc_div_type div_value)
|
||||
{
|
||||
CRM->cfg_bit.adcdiv_l = div_value & 0x03;
|
||||
CRM->cfg_bit.adcdiv_h = (div_value >> 2) & 0x01;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set crm usb division
|
||||
* @param value
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_USB_DIV_1_5
|
||||
* - CRM_USB_DIV_1
|
||||
* - CRM_USB_DIV_2_5
|
||||
* - CRM_USB_DIV_2
|
||||
* - CRM_USB_DIV_3_5
|
||||
* - CRM_USB_DIV_3
|
||||
* - CRM_USB_DIV_4
|
||||
* @retval none
|
||||
*/
|
||||
void crm_usb_clock_div_set(crm_usb_div_type div_value)
|
||||
{
|
||||
CRM->cfg_bit.usbdiv_l = div_value & 0x03;
|
||||
CRM->cfg_bit.usbdiv_h = (div_value >> 2) & 0x01;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable clock failure detection
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void crm_clock_failure_detection_enable(confirm_state new_state)
|
||||
{
|
||||
CRM->ctrl_bit.cfden = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief battery powered domain software reset
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void crm_battery_powered_domain_reset(confirm_state new_state)
|
||||
{
|
||||
CRM->bpdc_bit.bpdrst = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief config crm pll
|
||||
* @param clock_source
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_PLL_SOURCE_HICK
|
||||
* - CRM_PLL_SOURCE_HEXT
|
||||
* - CRM_PLL_SOURCE_HEXT_DIV
|
||||
* @param mult_value (CRM_PLL_MULT_2~64)
|
||||
* @param pll_range
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_PLL_OUTPUT_RANGE_LE72MHZ
|
||||
* - CRM_PLL_OUTPUT_RANGE_GT72MHZ
|
||||
* @retval none
|
||||
*/
|
||||
void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mult_value, crm_pll_output_range_type pll_range)
|
||||
{
|
||||
/* config pll clock source */
|
||||
if(clock_source == CRM_PLL_SOURCE_HICK)
|
||||
{
|
||||
CRM->cfg_bit.pllrcs = FALSE;
|
||||
CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV;
|
||||
}
|
||||
else
|
||||
{
|
||||
CRM->cfg_bit.pllrcs = TRUE;
|
||||
if(CRM_PLL_SOURCE_HEXT == clock_source)
|
||||
{
|
||||
CRM->cfg_bit.pllhextdiv = FALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
CRM->cfg_bit.pllhextdiv = TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
/* config pll multiplication factor */
|
||||
CRM->cfg_bit.pllmult_l = (mult_value & 0x0F);
|
||||
CRM->cfg_bit.pllmult_h = ((mult_value & 0x30) >> 4);
|
||||
|
||||
/* config pll output range */
|
||||
CRM->cfg_bit.pllrange = pll_range;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief select system clock source
|
||||
* @param value
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_SCLK_HICK
|
||||
* - CRM_SCLK_HEXT
|
||||
* - CRM_SCLK_PLL
|
||||
* @retval none
|
||||
*/
|
||||
void crm_sysclk_switch(crm_sclk_type value)
|
||||
{
|
||||
CRM->cfg_bit.sclksel = value;
|
||||
DUMMY_NOP();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief indicate which clock source is used as system clock
|
||||
* @param none
|
||||
* @retval crm_sclk
|
||||
* this return can be one of the following values:
|
||||
* - CRM_SCLK_HICK
|
||||
* - CRM_SCLK_HEXT
|
||||
* - CRM_SCLK_PLL
|
||||
*/
|
||||
crm_sclk_type crm_sysclk_switch_status_get(void)
|
||||
{
|
||||
return (crm_sclk_type)CRM->cfg_bit.sclksts;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get crm clocks freqency
|
||||
* @param clocks
|
||||
* - pointer to the crm_clocks_freq structure
|
||||
* @retval none
|
||||
*/
|
||||
void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct)
|
||||
{
|
||||
uint32_t pll_mult = 0, pll_mult_h = 0, pll_clock_source = 0, temp = 0, div_value = 0;
|
||||
crm_sclk_type sclk_source;
|
||||
|
||||
static const uint8_t sclk_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
static const uint8_t ahb_apb1_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
|
||||
static const uint8_t ahb_apb2_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
|
||||
static const uint8_t adc_div_table[8] = {2, 4, 6, 8, 2, 12, 8, 16};
|
||||
|
||||
/* get sclk source */
|
||||
sclk_source = crm_sysclk_switch_status_get();
|
||||
|
||||
switch(sclk_source)
|
||||
{
|
||||
case CRM_SCLK_HICK:
|
||||
if(((CRM->misc3_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
|
||||
clocks_struct->sclk_freq = HICK_VALUE * 6;
|
||||
else
|
||||
clocks_struct->sclk_freq = HICK_VALUE;
|
||||
break;
|
||||
case CRM_SCLK_HEXT:
|
||||
clocks_struct->sclk_freq = HEXT_VALUE;
|
||||
break;
|
||||
case CRM_SCLK_PLL:
|
||||
pll_clock_source = CRM->cfg_bit.pllrcs;
|
||||
/* get multiplication factor */
|
||||
pll_mult = CRM->cfg_bit.pllmult_l;
|
||||
pll_mult_h = CRM->cfg_bit.pllmult_h;
|
||||
|
||||
/* process high bits */
|
||||
if((pll_mult_h != 0U) || (pll_mult == 15U))
|
||||
{
|
||||
pll_mult += ((16U * pll_mult_h) + 1U);
|
||||
}
|
||||
else
|
||||
{
|
||||
pll_mult += 2U;
|
||||
}
|
||||
|
||||
if (pll_clock_source == 0x00)
|
||||
{
|
||||
/* hick divided by 2 selected as pll clock entry */
|
||||
clocks_struct->sclk_freq = (HICK_VALUE >> 1) * pll_mult;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* hext selected as pll clock entry */
|
||||
if (CRM->cfg_bit.pllhextdiv != RESET)
|
||||
{
|
||||
/* hext clock divided by 2 */
|
||||
clocks_struct->sclk_freq = (HEXT_VALUE / 2) * pll_mult;
|
||||
}
|
||||
else
|
||||
{
|
||||
clocks_struct->sclk_freq = HEXT_VALUE * pll_mult;
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
clocks_struct->sclk_freq = HICK_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
/* compute sclk, ahbclk, abp1clk apb2clk and adcclk frequencies */
|
||||
/* get ahb division */
|
||||
temp = CRM->cfg_bit.ahbdiv;
|
||||
div_value = sclk_ahb_div_table[temp];
|
||||
/* ahbclk frequency */
|
||||
clocks_struct->ahb_freq = clocks_struct->sclk_freq >> div_value;
|
||||
|
||||
/* get apb1 division */
|
||||
temp = CRM->cfg_bit.apb1div;
|
||||
div_value = ahb_apb1_div_table[temp];
|
||||
/* apb1clk frequency */
|
||||
clocks_struct->apb1_freq = clocks_struct->ahb_freq >> div_value;
|
||||
|
||||
/* get apb2 division */
|
||||
temp = CRM->cfg_bit.apb2div;
|
||||
div_value = ahb_apb2_div_table[temp];
|
||||
/* apb2clk frequency */
|
||||
clocks_struct->apb2_freq = clocks_struct->ahb_freq >> div_value;
|
||||
|
||||
/* get adc division */
|
||||
temp = CRM->cfg_bit.adcdiv_h;
|
||||
temp = ((temp << 2) | (CRM->cfg_bit.adcdiv_l));
|
||||
div_value = adc_div_table[temp];
|
||||
/* adcclk clock frequency */
|
||||
clocks_struct->adc_freq = clocks_struct->apb2_freq / div_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set crm clkout
|
||||
* @param clkout
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_CLKOUT_NOCLK
|
||||
* - CRM_CLKOUT_LICK
|
||||
* - CRM_CLKOUT_LEXT
|
||||
* - CRM_CLKOUT_SCLK
|
||||
* - CRM_CLKOUT_HICK
|
||||
* - CRM_CLKOUT_HEXT
|
||||
* - CRM_CLKOUT_PLL_DIV_2
|
||||
* - CRM_CLKOUT_PLL_DIV_4
|
||||
* - CRM_CLKOUT_USB
|
||||
* - CRM_CLKOUT_ADC
|
||||
* @retval none
|
||||
*/
|
||||
void crm_clock_out_set(crm_clkout_select_type clkout)
|
||||
{
|
||||
CRM->cfg_bit.clkout_sel = clkout & 0x7;
|
||||
CRM->misc1_bit.clkout_sel = (clkout >> 3) & 0x1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief config crm interrupt
|
||||
* @param int
|
||||
* this parameter can be any combination of the following values:
|
||||
* - CRM_LICK_STABLE_INT
|
||||
* - CRM_LEXT_STABLE_INT
|
||||
* - CRM_HICK_STABLE_INT
|
||||
* - CRM_HEXT_STABLE_INT
|
||||
* - CRM_PLL_STABLE_INT
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state)
|
||||
{
|
||||
if(new_state == TRUE)
|
||||
CRM->clkint |= crm_int;
|
||||
else
|
||||
CRM->clkint &= ~crm_int;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief auto step clock switch enable
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void crm_auto_step_mode_enable(confirm_state new_state)
|
||||
{
|
||||
if(new_state == TRUE)
|
||||
CRM->misc3_bit.auto_step_en = CRM_AUTO_STEP_MODE_ENABLE;
|
||||
else
|
||||
CRM->misc3_bit.auto_step_en = CRM_AUTO_STEP_MODE_DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usbdev interrupt remapping control
|
||||
* @param int_remap
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_USB_INT19_INT20
|
||||
* - CRM_USB_INT73_INT74
|
||||
* @retval none
|
||||
*/
|
||||
void crm_usb_interrupt_remapping_set(crm_usb_int_map_type int_remap)
|
||||
{
|
||||
CRM->intmap_bit.usbintmap = int_remap;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief config hick divider select
|
||||
* @param value
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_HICK48_DIV6
|
||||
* - CRM_HICK48_NODIV
|
||||
* @retval none
|
||||
*/
|
||||
void crm_hick_divider_select(crm_hick_div_6_type value)
|
||||
{
|
||||
CRM->misc1_bit.hickdiv = value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief hick as system clock frequency select
|
||||
* @param value
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_HICK_SCLK_8MHZ
|
||||
* - CRM_HICK_SCLK_48MHZ
|
||||
* @retval none
|
||||
*/
|
||||
void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value)
|
||||
{
|
||||
crm_hick_divider_select(CRM_HICK48_NODIV);
|
||||
CRM->misc3_bit.hick_to_sclk = value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb 48 mhz clock source select
|
||||
* @param value
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_USB_CLOCK_SOURCE_PLL
|
||||
* - CRM_USB_CLOCK_SOURCE_HICK
|
||||
* @retval none
|
||||
*/
|
||||
void crm_usb_clock_source_select(crm_usb_clock_source_type value)
|
||||
{
|
||||
if(value == CRM_USB_CLOCK_SOURCE_HICK)
|
||||
{
|
||||
crm_hick_sclk_frequency_select(CRM_HICK_SCLK_48MHZ);
|
||||
}
|
||||
CRM->misc3_bit.hick_to_usb = value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable clkout direct to tmr10 channel 1
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void crm_clkout_to_tmr10_enable(confirm_state new_state)
|
||||
{
|
||||
CRM->misc2_bit.clk_to_tmr = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set crm clkout division
|
||||
* @param clkout_div
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_CLKOUT_DIV_1
|
||||
* - CRM_CLKOUT_DIV_2
|
||||
* - CRM_CLKOUT_DIV_4
|
||||
* - CRM_CLKOUT_DIV_8
|
||||
* - CRM_CLKOUT_DIV_16
|
||||
* - CRM_CLKOUT_DIV_64
|
||||
* - CRM_CLKOUT_DIV_128
|
||||
* - CRM_CLKOUT_DIV_256
|
||||
* - CRM_CLKOUT_DIV_512
|
||||
* @retval none
|
||||
*/
|
||||
void crm_clkout_div_set(crm_clkout_div_type clkout_div)
|
||||
{
|
||||
CRM->misc1_bit.clkoutdiv = clkout_div;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
102
libraries/drivers/src/at32f413_debug.c
Normal file
102
libraries/drivers/src/at32f413_debug.c
Normal file
@@ -0,0 +1,102 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_debug.c
|
||||
* @brief contains all the functions for the debug firmware library
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#include "at32f413_conf.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DEBUG
|
||||
* @brief DEBUG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef DEBUG_MODULE_ENABLED
|
||||
|
||||
/** @defgroup DEBUG_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief get debug device id
|
||||
* @param none
|
||||
* @retval the debug device id
|
||||
*/
|
||||
uint32_t debug_device_id_get(void)
|
||||
{
|
||||
return DEBUGMCU->pid;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set periph debug mode
|
||||
* @param periph_debug_mode
|
||||
* this parameter can be any combination of the following values:
|
||||
* - DEBUG_SLEEP
|
||||
* - DEBUG_DEEPSLEEP
|
||||
* - DEBUG_STANDBY
|
||||
* - DEBUG_WDT_PAUSE
|
||||
* - DEBUG_WWDT_PAUSE
|
||||
* - DEBUG_TMR1_PAUSE
|
||||
* - DEBUG_TMR2_PAUSE
|
||||
* - DEBUG_TMR3_PAUSE
|
||||
* - DEBUG_TMR4_PAUSE
|
||||
* - DEBUG_CAN1_PAUSE
|
||||
* - DEBUG_I2C1_SMBUS_TIMEOUT
|
||||
* - DEBUG_I2C2_SMBUS_TIMEOUT
|
||||
* - DEBUG_TMR8_PAUSE
|
||||
* - DEBUG_TMR5_PAUSE
|
||||
* - DEBUG_CAN2_PAUSE
|
||||
* - DEBUG_TMR9_PAUSE
|
||||
* - DEBUG_TMR10_PAUSE
|
||||
* - DEBUG_TMR11_PAUSE
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void debug_periph_mode_set(uint32_t periph_debug_mode, confirm_state new_state)
|
||||
{
|
||||
|
||||
if(new_state != FALSE)
|
||||
{
|
||||
DEBUGMCU->ctrl |= periph_debug_mode;
|
||||
}
|
||||
else
|
||||
{
|
||||
DEBUGMCU->ctrl &= ~periph_debug_mode;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
263
libraries/drivers/src/at32f413_exint.c
Normal file
263
libraries/drivers/src/at32f413_exint.c
Normal file
@@ -0,0 +1,263 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_exint.c
|
||||
* @brief contains all the functions for the exint firmware library
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#include "at32f413_conf.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXINT
|
||||
* @brief EXINT driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef EXINT_MODULE_ENABLED
|
||||
|
||||
/** @defgroup EXINT_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief exint reset
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void exint_reset(void)
|
||||
{
|
||||
EXINT->inten = 0x00000000;
|
||||
EXINT->polcfg1 = 0x00000000;
|
||||
EXINT->polcfg2 = 0x00000000;
|
||||
EXINT->evten = 0x00000000;
|
||||
EXINT->intsts = 0x0007FFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief exint default para init
|
||||
* @param exint_struct
|
||||
* - to the structure of exint_init_type
|
||||
* @retval none
|
||||
*/
|
||||
void exint_default_para_init(exint_init_type *exint_struct)
|
||||
{
|
||||
exint_struct->line_enable = FALSE;
|
||||
exint_struct->line_select = EXINT_LINE_NONE;
|
||||
exint_struct->line_polarity = EXINT_TRIGGER_FALLING_EDGE;
|
||||
exint_struct->line_mode = EXINT_LINE_EVENT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief exint init
|
||||
* @param exint_struct
|
||||
* - to the structure of exint_init_type
|
||||
* @retval none
|
||||
*/
|
||||
void exint_init(exint_init_type *exint_struct)
|
||||
{
|
||||
uint32_t line_index = 0;
|
||||
line_index = exint_struct->line_select;
|
||||
|
||||
EXINT->inten &= ~line_index;
|
||||
EXINT->evten &= ~line_index;
|
||||
|
||||
if(exint_struct->line_enable != FALSE)
|
||||
{
|
||||
if(exint_struct->line_mode == EXINT_LINE_INTERRUPUT)
|
||||
{
|
||||
EXINT->inten |= line_index;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXINT->evten |= line_index;
|
||||
}
|
||||
|
||||
EXINT->polcfg1 &= ~line_index;
|
||||
EXINT->polcfg2 &= ~line_index;
|
||||
if(exint_struct->line_polarity == EXINT_TRIGGER_RISING_EDGE)
|
||||
{
|
||||
EXINT->polcfg1 |= line_index;
|
||||
}
|
||||
else if(exint_struct->line_polarity == EXINT_TRIGGER_FALLING_EDGE)
|
||||
{
|
||||
EXINT->polcfg2 |= line_index;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXINT->polcfg1 |= line_index;
|
||||
EXINT->polcfg2 |= line_index;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear exint flag
|
||||
* @param exint_line
|
||||
* this parameter can be any combination of the following values:
|
||||
* - EXINT_LINE_0
|
||||
* - EXINT_LINE_1
|
||||
* ...
|
||||
* - EXINT_LINE_17
|
||||
* - EXINT_LINE_18
|
||||
* @retval none
|
||||
*/
|
||||
void exint_flag_clear(uint32_t exint_line)
|
||||
{
|
||||
EXINT->intsts = exint_line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get exint flag
|
||||
* @param exint_line
|
||||
* this parameter can be one of the following values:
|
||||
* - EXINT_LINE_0
|
||||
* - EXINT_LINE_1
|
||||
* ...
|
||||
* - EXINT_LINE_17
|
||||
* - EXINT_LINE_18
|
||||
* @retval the new state of exint flag(SET or RESET).
|
||||
*/
|
||||
flag_status exint_flag_get(uint32_t exint_line)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
uint32_t exint_flag =0;
|
||||
exint_flag = EXINT->intsts & exint_line;
|
||||
if((exint_flag != (uint16_t)RESET))
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = RESET;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get exint interrupt flag
|
||||
* @param exint_line
|
||||
* this parameter can be one of the following values:
|
||||
* - EXINT_LINE_0
|
||||
* - EXINT_LINE_1
|
||||
* ...
|
||||
* - EXINT_LINE_17
|
||||
* - EXINT_LINE_18
|
||||
* @retval the new state of exint flag(SET or RESET).
|
||||
*/
|
||||
flag_status exint_interrupt_flag_get(uint32_t exint_line)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
uint32_t exint_flag = 0;
|
||||
exint_flag = EXINT->intsts & exint_line;
|
||||
exint_flag = exint_flag & EXINT->inten;
|
||||
|
||||
if((exint_flag != (uint16_t)RESET))
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = RESET;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief generate exint software interrupt event
|
||||
* @param exint_line
|
||||
* this parameter can be one of the following values:
|
||||
* - EXINT_LINE_0
|
||||
* - EXINT_LINE_1
|
||||
* ...
|
||||
* - EXINT_LINE_17
|
||||
* - EXINT_LINE_18
|
||||
* @retval none
|
||||
*/
|
||||
void exint_software_interrupt_event_generate(uint32_t exint_line)
|
||||
{
|
||||
EXINT->swtrg |= exint_line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable exint interrupt
|
||||
* @param exint_line
|
||||
* this parameter can be any combination of the following values:
|
||||
* - EXINT_LINE_0
|
||||
* - EXINT_LINE_1
|
||||
* ...
|
||||
* - EXINT_LINE_17
|
||||
* - EXINT_LINE_18
|
||||
* @param new_state: new state of exint interrupt.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state)
|
||||
{
|
||||
if(new_state == TRUE)
|
||||
{
|
||||
EXINT->inten |= exint_line;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXINT->inten &= ~exint_line;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable exint event
|
||||
* @param exint_line
|
||||
* this parameter can be any combination of the following values:
|
||||
* - EXINT_LINE_0
|
||||
* - EXINT_LINE_1
|
||||
* ...
|
||||
* - EXINT_LINE_17
|
||||
* - EXINT_LINE_18
|
||||
* @param new_state: new state of exint event.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void exint_event_enable(uint32_t exint_line, confirm_state new_state)
|
||||
{
|
||||
if(new_state == TRUE)
|
||||
{
|
||||
EXINT->evten |= exint_line;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXINT->evten &= ~exint_line;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
961
libraries/drivers/src/at32f413_flash.c
Normal file
961
libraries/drivers/src/at32f413_flash.c
Normal file
@@ -0,0 +1,961 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_flash.c
|
||||
* @brief contains all the functions for the flash firmware library
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#include "at32f413_conf.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH
|
||||
* @brief FLASH driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef FLASH_MODULE_ENABLED
|
||||
|
||||
/** @defgroup FLASH_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief check whether the specified flash flag is set or not.
|
||||
* @param flash_flag: specifies the flash flag to check.
|
||||
* this parameter can be one of flash flag status:
|
||||
* - FLASH_OBF_FLAG
|
||||
* - FLASH_ODF_FLAG
|
||||
* - FLASH_PRGMERR_FLAG
|
||||
* - FLASH_EPPERR_FLAG
|
||||
* - FLASH_SPIM_OBF_FLAG
|
||||
* - FLASH_SPIM_ODF_FLAG
|
||||
* - FLASH_SPIM_PRGMERR_FLAG
|
||||
* - FLASH_SPIM_EPPERR_FLAG
|
||||
* - FLASH_USDERR_FLAG
|
||||
* @retval the new state of flash_flag (SET or RESET).
|
||||
*/
|
||||
flag_status flash_flag_get(uint32_t flash_flag)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
uint32_t flag_position;
|
||||
flag_position = flash_flag & 0x70000000;
|
||||
flash_flag &= 0x8FFFFFFF;
|
||||
switch(flag_position)
|
||||
{
|
||||
case 0x00000000:
|
||||
if(FLASH->sts & flash_flag)
|
||||
status = SET;
|
||||
break;
|
||||
case 0x20000000:
|
||||
if(FLASH->sts3 & flash_flag)
|
||||
status = SET;
|
||||
break;
|
||||
case 0x40000000:
|
||||
if(FLASH->usd & flash_flag)
|
||||
status = SET;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
/* return the new state of flash_flag (SET or RESET) */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear the flash flag.
|
||||
* @param flash_flag: specifies the flash flags to clear.
|
||||
* this parameter can be any combination of the following values:
|
||||
* - FLASH_ODF_FLAG
|
||||
* - FLASH_PRGMERR_FLAG
|
||||
* - FLASH_EPPERR_FLAG
|
||||
* - FLASH_SPIM_ODF_FLAG
|
||||
* - FLASH_SPIM_PRGMERR_FLAG
|
||||
* - FLASH_SPIM_EPPERR_FLAG
|
||||
* @retval none
|
||||
*/
|
||||
void flash_flag_clear(uint32_t flash_flag)
|
||||
{
|
||||
uint32_t flag_position;
|
||||
flag_position = flash_flag & 0x70000000;
|
||||
flash_flag &= 0x8FFFFFFF;
|
||||
switch(flag_position)
|
||||
{
|
||||
case 0x00000000:
|
||||
FLASH->sts = flash_flag;
|
||||
break;
|
||||
case 0x20000000:
|
||||
FLASH->sts3 = flash_flag;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return the flash operation status.
|
||||
* @param none
|
||||
* @retval status: the returned value can be: FLASH_OPERATE_BUSY,
|
||||
* FLASH_PROGRAM_ERROR, FLASH_EPP_ERROR or FLASH_OPERATE_DONE.
|
||||
*/
|
||||
flash_status_type flash_operation_status_get(void)
|
||||
{
|
||||
flash_status_type flash_status = FLASH_OPERATE_DONE;
|
||||
if(FLASH->sts_bit.obf != RESET)
|
||||
{
|
||||
flash_status = FLASH_OPERATE_BUSY;
|
||||
}
|
||||
else if(FLASH->sts_bit.prgmerr != RESET)
|
||||
{
|
||||
flash_status = FLASH_PROGRAM_ERROR;
|
||||
}
|
||||
else if(FLASH->sts_bit.epperr != RESET)
|
||||
{
|
||||
flash_status = FLASH_EPP_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
flash_status = FLASH_OPERATE_DONE;
|
||||
}
|
||||
/* return the flash status */
|
||||
return flash_status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return the flash spim operation status.
|
||||
* @param none
|
||||
* @retval status: the returned value can be: FLASH_OPERATE_BUSY,
|
||||
* FLASH_PROGRAM_ERROR, FLASH_EPP_ERROR or FLASH_OPERATE_DONE.
|
||||
*/
|
||||
flash_status_type flash_spim_operation_status_get(void)
|
||||
{
|
||||
flash_status_type flash_status = FLASH_OPERATE_DONE;
|
||||
if(FLASH->sts3_bit.obf != RESET)
|
||||
{
|
||||
flash_status = FLASH_OPERATE_BUSY;
|
||||
}
|
||||
else if(FLASH->sts3_bit.prgmerr != RESET)
|
||||
{
|
||||
flash_status = FLASH_PROGRAM_ERROR;
|
||||
}
|
||||
else if(FLASH->sts3_bit.epperr != RESET)
|
||||
{
|
||||
flash_status = FLASH_EPP_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
flash_status = FLASH_OPERATE_DONE;
|
||||
}
|
||||
/* return the flash status */
|
||||
return flash_status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief wait for flash operation complete or timeout.
|
||||
* @param time_out: flash operation timeout
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_operation_wait_for(uint32_t time_out)
|
||||
{
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
/* check for the flash status */
|
||||
status = flash_operation_status_get();
|
||||
|
||||
while((status == FLASH_OPERATE_BUSY) && (time_out != 0x00))
|
||||
{
|
||||
status = flash_operation_status_get();
|
||||
time_out--;
|
||||
}
|
||||
if(time_out == 0x00)
|
||||
{
|
||||
status = FLASH_OPERATE_TIMEOUT;
|
||||
}
|
||||
/* return the status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief wait for flash spim operation complete or timeout.
|
||||
* @param time_out: flash operation timeout
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_spim_operation_wait_for(uint32_t time_out)
|
||||
{
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
/* check for the flash status */
|
||||
status = flash_spim_operation_status_get();
|
||||
|
||||
while((status == FLASH_OPERATE_BUSY) && (time_out != 0x00))
|
||||
{
|
||||
status = flash_spim_operation_status_get();
|
||||
time_out--;
|
||||
}
|
||||
if(time_out == 0x00)
|
||||
{
|
||||
status = FLASH_OPERATE_TIMEOUT;
|
||||
}
|
||||
/* return the operation status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief unlock the flash controller.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void flash_unlock(void)
|
||||
{
|
||||
FLASH->unlock = FLASH_UNLOCK_KEY1;
|
||||
FLASH->unlock = FLASH_UNLOCK_KEY2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief unlock the flash spim controller.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void flash_spim_unlock(void)
|
||||
{
|
||||
FLASH->unlock3 = FLASH_UNLOCK_KEY1;
|
||||
FLASH->unlock3 = FLASH_UNLOCK_KEY2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief lock the flash controller.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void flash_lock(void)
|
||||
{
|
||||
FLASH->ctrl_bit.oplk = TRUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief lock the flash spim controller.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void flash_spim_lock(void)
|
||||
{
|
||||
FLASH->ctrl3_bit.oplk = TRUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief erase a specified flash sector.
|
||||
* @param sector_address: the sector address to be erased.
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_sector_erase(uint32_t sector_address)
|
||||
{
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
/* spim : external flash */
|
||||
if(sector_address >= FLASH_SPIM_START_ADDR)
|
||||
{
|
||||
FLASH->ctrl3_bit.secers = TRUE;
|
||||
FLASH->addr3 = sector_address;
|
||||
FLASH->ctrl3_bit.erstr = TRUE;
|
||||
|
||||
/* wait for operation to be completed */
|
||||
status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT);
|
||||
|
||||
/* disable the secers bit */
|
||||
FLASH->ctrl3_bit.secers = FALSE;
|
||||
|
||||
/* dummy read */
|
||||
flash_spim_dummy_read();
|
||||
}
|
||||
else
|
||||
{
|
||||
FLASH->ctrl_bit.secers = TRUE;
|
||||
FLASH->addr = sector_address;
|
||||
FLASH->ctrl_bit.erstr = TRUE;
|
||||
|
||||
/* wait for operation to be completed */
|
||||
status = flash_operation_wait_for(ERASE_TIMEOUT);
|
||||
|
||||
/* disable the secers bit */
|
||||
FLASH->ctrl_bit.secers = FALSE;
|
||||
}
|
||||
/* return the erase status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief erase flash all internal sectors.
|
||||
* @param none
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_internal_all_erase(void)
|
||||
{
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
|
||||
FLASH->ctrl_bit.bankers = TRUE;
|
||||
FLASH->ctrl_bit.erstr = TRUE;
|
||||
|
||||
/* wait for operation to be completed */
|
||||
status = flash_operation_wait_for(ERASE_TIMEOUT);
|
||||
|
||||
/* disable the bankers bit */
|
||||
FLASH->ctrl_bit.bankers = FALSE;
|
||||
|
||||
/* return the erase status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief erase flash spim sectors.
|
||||
* @param none
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_spim_all_erase(void)
|
||||
{
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
|
||||
FLASH->ctrl3_bit.chpers = TRUE;
|
||||
FLASH->ctrl3_bit.erstr = TRUE;
|
||||
|
||||
/* wait for operation to be completed */
|
||||
status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT);
|
||||
|
||||
/* disable the chpers bit */
|
||||
FLASH->ctrl3_bit.chpers = FALSE;
|
||||
|
||||
/* dummy read */
|
||||
flash_spim_dummy_read();
|
||||
|
||||
/* return the erase status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief erase the flash user system data.
|
||||
* @note this functions erases all user system data except the fap byte.
|
||||
* @param none
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_user_system_data_erase(void)
|
||||
{
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
uint16_t fap_val = FAP_RELIEVE_KEY;
|
||||
/* get the flash access protection status */
|
||||
if(flash_fap_status_get() != RESET)
|
||||
{
|
||||
fap_val = 0x0000;
|
||||
}
|
||||
|
||||
/* unlock the user system data */
|
||||
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
|
||||
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
|
||||
while(FLASH->ctrl_bit.usdulks == RESET);
|
||||
|
||||
/* erase the user system data */
|
||||
FLASH->ctrl_bit.usders = TRUE;
|
||||
FLASH->ctrl_bit.erstr = TRUE;
|
||||
|
||||
/* wait for operation to be completed */
|
||||
status = flash_operation_wait_for(ERASE_TIMEOUT);
|
||||
|
||||
/* disable the usders bit */
|
||||
FLASH->ctrl_bit.usders = FALSE;
|
||||
|
||||
if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY))
|
||||
{
|
||||
/* enable the user system data programming operation */
|
||||
FLASH->ctrl_bit.usdprgm = TRUE;
|
||||
|
||||
/* restore the last flash access protection value */
|
||||
USD->fap = (uint16_t)fap_val;
|
||||
|
||||
/* wait for operation to be completed */
|
||||
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
|
||||
|
||||
/*disable the usdprgm bit */
|
||||
FLASH->ctrl_bit.usdprgm = FALSE;
|
||||
}
|
||||
|
||||
/* return the erase status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief program a word at a specified address.
|
||||
* @param address: specifies the address to be programmed, word alignment is recommended.
|
||||
* @param data: specifies the data to be programmed.
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_word_program(uint32_t address, uint32_t data)
|
||||
{
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
/* spim : external flash */
|
||||
if(address >= FLASH_SPIM_START_ADDR)
|
||||
{
|
||||
FLASH->ctrl3_bit.fprgm = TRUE;
|
||||
*(__IO uint32_t*)address = data;
|
||||
/* wait for operation to be completed */
|
||||
status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT);
|
||||
|
||||
/* disable the fprgm bit */
|
||||
FLASH->ctrl3_bit.fprgm = FALSE;
|
||||
|
||||
/* dummy read */
|
||||
flash_spim_dummy_read();
|
||||
}
|
||||
else
|
||||
{
|
||||
FLASH->ctrl_bit.fprgm = TRUE;
|
||||
*(__IO uint32_t*)address = data;
|
||||
/* wait for operation to be completed */
|
||||
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
|
||||
|
||||
/* disable the fprgm bit */
|
||||
FLASH->ctrl_bit.fprgm = FALSE;
|
||||
}
|
||||
/* return the program status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief program a halfword at a specified address.
|
||||
* @param address: specifies the address to be programmed, halfword alignment is recommended.
|
||||
* @param data: specifies the data to be programmed.
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_halfword_program(uint32_t address, uint16_t data)
|
||||
{
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
/* spim : external flash */
|
||||
if(address >= FLASH_SPIM_START_ADDR)
|
||||
{
|
||||
FLASH->ctrl3_bit.fprgm = TRUE;
|
||||
*(__IO uint16_t*)address = data;
|
||||
/* wait for operation to be completed */
|
||||
status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT);
|
||||
|
||||
/* disable the fprgm bit */
|
||||
FLASH->ctrl3_bit.fprgm = FALSE;
|
||||
|
||||
/* dummy read */
|
||||
flash_spim_dummy_read();
|
||||
}
|
||||
else
|
||||
{
|
||||
FLASH->ctrl_bit.fprgm = TRUE;
|
||||
*(__IO uint16_t*)address = data;
|
||||
/* wait for operation to be completed */
|
||||
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
|
||||
|
||||
/* disable the fprgm bit */
|
||||
FLASH->ctrl_bit.fprgm = FALSE;
|
||||
}
|
||||
/* return the program status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief program a byte at a specified address.
|
||||
* @note this function cannot be used to program spim.
|
||||
* @param address: specifies the address to be programmed.
|
||||
* @param data: specifies the data to be programmed.
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_byte_program(uint32_t address, uint8_t data)
|
||||
{
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
|
||||
FLASH->ctrl_bit.fprgm = TRUE;
|
||||
*(__IO uint8_t*)address = data;
|
||||
/* wait for operation to be completed */
|
||||
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
|
||||
|
||||
/* disable the fprgm bit */
|
||||
FLASH->ctrl_bit.fprgm = FALSE;
|
||||
|
||||
/* return the program status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief program a halfword at a specified user system data address.
|
||||
* @param address: specifies the address to be programmed.
|
||||
* @param data: specifies the data to be programmed.
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data)
|
||||
{
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
|
||||
if(address == USD_BASE)
|
||||
{
|
||||
if(data != 0xA5)
|
||||
return FLASH_OPERATE_DONE;
|
||||
}
|
||||
|
||||
/* unlock the user system data */
|
||||
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
|
||||
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
|
||||
while(FLASH->ctrl_bit.usdulks==RESET);
|
||||
|
||||
/* enable the user system data programming operation */
|
||||
FLASH->ctrl_bit.usdprgm = TRUE;
|
||||
*(__IO uint16_t*)address = data;
|
||||
|
||||
/* wait for operation to be completed */
|
||||
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
|
||||
|
||||
/* disable the usdprgm bit */
|
||||
FLASH->ctrl_bit.usdprgm = FALSE;
|
||||
|
||||
/* return the user system data program status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief config erase/program protection for the desired sectors.
|
||||
* @param sector_bits:
|
||||
* the pointer of the address of the sectors to be erase/program protected.
|
||||
* general every bit is used to protect the 4KB bytes, and the last one bit
|
||||
* is used to protect the rest.
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_epp_set(uint32_t *sector_bits)
|
||||
{
|
||||
uint16_t epp_data[4] = {0xFFFF,0xFFFF,0xFFFF,0xFFFF};
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
sector_bits[0] = (uint32_t)(~sector_bits[0]);
|
||||
epp_data[0] = (uint16_t)((sector_bits[0] >> 0) & 0xFF);
|
||||
epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF);
|
||||
epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF);
|
||||
epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF);
|
||||
|
||||
/* unlock the user system data */
|
||||
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
|
||||
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
|
||||
while(FLASH->ctrl_bit.usdulks==RESET);
|
||||
|
||||
FLASH->ctrl_bit.usdprgm = TRUE;
|
||||
USD->epp0 = epp_data[0];
|
||||
/* wait for operation to be completed */
|
||||
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
|
||||
|
||||
if(status == FLASH_OPERATE_DONE)
|
||||
{
|
||||
USD->epp1 = epp_data[1];
|
||||
/* wait for operation to be completed */
|
||||
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
|
||||
}
|
||||
if(status == FLASH_OPERATE_DONE)
|
||||
{
|
||||
USD->epp2 = epp_data[2];
|
||||
/* wait for operation to be completed */
|
||||
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
|
||||
}
|
||||
if(status == FLASH_OPERATE_DONE)
|
||||
{
|
||||
USD->epp3 = epp_data[3];
|
||||
/* wait for operation to be completed */
|
||||
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
|
||||
}
|
||||
/* disable the usdprgm bit */
|
||||
FLASH->ctrl_bit.usdprgm = FALSE;
|
||||
|
||||
/* return the erase/program protection operation status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return the flash erase/program protection status.
|
||||
* @param sector_bits: pointer to get the epps register.
|
||||
* @retval none
|
||||
*/
|
||||
void flash_epp_status_get(uint32_t *sector_bits)
|
||||
{
|
||||
/* return the flash erase/program protection register value */
|
||||
sector_bits[0] = (uint32_t)(FLASH->epps);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the flash access protection.
|
||||
* @note if the user has already programmed the other user system data before calling
|
||||
* this function, must re-program them since this function erase all user system data.
|
||||
* @param new_state: new state of the flash access protection.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_fap_enable(confirm_state new_state)
|
||||
{
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
|
||||
/* unlock the user system data */
|
||||
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
|
||||
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
|
||||
while(FLASH->ctrl_bit.usdulks==RESET);
|
||||
|
||||
FLASH->ctrl_bit.usders = TRUE;
|
||||
FLASH->ctrl_bit.erstr = TRUE;
|
||||
/* wait for operation to be completed */
|
||||
status = flash_operation_wait_for(ERASE_TIMEOUT);
|
||||
|
||||
/* disable the usders bit */
|
||||
FLASH->ctrl_bit.usders = FALSE;
|
||||
|
||||
if(status == FLASH_OPERATE_DONE)
|
||||
{
|
||||
if(new_state == FALSE)
|
||||
{
|
||||
/* enable the user system data programming operation */
|
||||
FLASH->ctrl_bit.usdprgm = TRUE;
|
||||
USD->fap = FAP_RELIEVE_KEY;
|
||||
|
||||
/* Wait for operation to be completed */
|
||||
status = flash_operation_wait_for(ERASE_TIMEOUT);
|
||||
|
||||
/* disable the usdprgm bit */
|
||||
FLASH->ctrl_bit.usdprgm = FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
/* return the flash access protection operation status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief check the flash access protection status.
|
||||
* @param none
|
||||
* @retval flash access protection status(SET or RESET)
|
||||
*/
|
||||
flag_status flash_fap_status_get(void)
|
||||
{
|
||||
return (flag_status)FLASH->usd_bit.fap;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief program the flash system setting byte in usd: wdt_ato_en / depslp_rst / stdby_rst.
|
||||
* @param usd_ssb: the system setting byte
|
||||
* @note this parameter usd_ssb must contain a combination of all the following 3 types of data
|
||||
* type 1: wdt_ato_en, select the wdt auto start
|
||||
* this data can be one of the following values:
|
||||
* - USD_WDT_ATO_DISABLE: disable wdt auto start
|
||||
* - USD_WDT_ATO_ENABLE: enable wdt auto start
|
||||
* type 2: depslp_rst, reset event when entering deepsleep mode.
|
||||
* this data can be one of the following values:
|
||||
* - USD_DEPSLP_NO_RST: no reset generated when entering in deepsleep
|
||||
* - USD_DEPSLP_RST: reset generated when entering in deepsleep
|
||||
* type 3: stdby_rst, reset event when entering standby mode.
|
||||
* this data can be one of the following values:
|
||||
* - USD_STDBY_NO_RST: no reset generated when entering in standby
|
||||
* - USD_STDBY_RST: reset generated when entering in standby
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_ssb_set(uint8_t usd_ssb)
|
||||
{
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
|
||||
/* unlock the user system data */
|
||||
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
|
||||
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
|
||||
while(FLASH->ctrl_bit.usdulks==RESET);
|
||||
|
||||
/* enable the user system data programming operation */
|
||||
FLASH->ctrl_bit.usdprgm = TRUE;
|
||||
|
||||
USD->ssb = usd_ssb;
|
||||
/* wait for operation to be completed */
|
||||
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
|
||||
|
||||
/* disable the usdprgm bit */
|
||||
FLASH->ctrl_bit.usdprgm = FALSE;
|
||||
|
||||
/* return the user system data program status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return the flash system setting byte status.
|
||||
* @param none
|
||||
* @retval values from flash_usd register: wdt_ato_en(bit0), depslp_rst(bit1) and stdby_rst(bit2).
|
||||
*/
|
||||
uint8_t flash_ssb_status_get(void)
|
||||
{
|
||||
/* return the system setting byte status */
|
||||
return (uint8_t)(FLASH->usd >> 2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the specified flash interrupts.
|
||||
* @param flash_int: specifies the flash interrupt sources to be enabled or disabled.
|
||||
* this parameter can be any combination of the following values:
|
||||
* - FLASH_ERR_INT
|
||||
* - FLASH_ODF_INT
|
||||
* - FLASH_SPIM_ERR_INT
|
||||
* - FLASH_SPIM_ODF_INT
|
||||
* @param new_state: new state of the specified flash interrupts.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state)
|
||||
{
|
||||
if(flash_int & FLASH_ERR_INT)
|
||||
FLASH->ctrl_bit.errie = new_state;
|
||||
if(flash_int & FLASH_ODF_INT)
|
||||
FLASH->ctrl_bit.odfie = new_state;
|
||||
if(flash_int & FLASH_SPIM_ERR_INT)
|
||||
FLASH->ctrl3_bit.errie = new_state;
|
||||
if(flash_int & FLASH_SPIM_ODF_INT)
|
||||
FLASH->ctrl3_bit.odfie = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief select spim supports extended spi flash chip model.
|
||||
* @param mode: the extended spi flash model
|
||||
* @retval none
|
||||
*/
|
||||
void flash_spim_model_select(flash_spim_model_type mode)
|
||||
{
|
||||
FLASH->select = mode;
|
||||
|
||||
/* dummy read */
|
||||
flash_spim_dummy_read();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set the range of encryption in spim flash.
|
||||
* when the address is larger than this value, the writing data will be
|
||||
* directly written to spim without encryption.
|
||||
* @param decode_address: the end address of encrypted data in spim
|
||||
* @retval none
|
||||
*/
|
||||
void flash_spim_encryption_range_set(uint32_t decode_address)
|
||||
{
|
||||
FLASH->da = decode_address;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief operate the flash spim dummy read.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void flash_spim_dummy_read(void)
|
||||
{
|
||||
UNUSED(*(__IO uint32_t*)FLASH_SPIM_START_ADDR);
|
||||
UNUSED(*(__IO uint32_t*)(FLASH_SPIM_START_ADDR + 0x1000));
|
||||
UNUSED(*(__IO uint32_t*)(FLASH_SPIM_START_ADDR + 0x2000));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief mass program for flash spim.
|
||||
* @param address: specifies the start address to be programmed, word or halfword alignment is recommended.
|
||||
* @param buf: specifies the pointer of data to be programmed.
|
||||
* @param cnt: specifies the data counter to be programmed.
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt)
|
||||
{
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
uint32_t index, temp_offset;
|
||||
if(address >= FLASH_SPIM_START_ADDR)
|
||||
{
|
||||
temp_offset = cnt % 4;
|
||||
if((temp_offset != 0) && (temp_offset != 2))
|
||||
return status;
|
||||
|
||||
FLASH->ctrl3_bit.fprgm = TRUE;
|
||||
for(index = 0; index < cnt / 4; index++)
|
||||
{
|
||||
*(__IO uint32_t*)(address + index * 4) = *(uint32_t*)(buf + index * 4);
|
||||
/* wait for operation to be completed */
|
||||
status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT);
|
||||
if(status != FLASH_OPERATE_DONE)
|
||||
return status;
|
||||
}
|
||||
if(temp_offset == 2)
|
||||
{
|
||||
*(__IO uint16_t*)(address + index * 4) = *(uint16_t*)(buf + index * 4);
|
||||
/* wait for operation to be completed */
|
||||
status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT);
|
||||
}
|
||||
/* disable the fprgm bit */
|
||||
FLASH->ctrl3_bit.fprgm = FALSE;
|
||||
|
||||
/* dummy read */
|
||||
flash_spim_dummy_read();
|
||||
}
|
||||
|
||||
/* return the program status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable security library function.
|
||||
* @param pwd: slib password
|
||||
* start_sector: security library start sector
|
||||
* data_start_sector: security library d-bus area start sector
|
||||
* end_sector: security library end sector
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t data_start_sector, uint16_t end_sector)
|
||||
{
|
||||
uint32_t slib_range;
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
|
||||
/*check range param limits*/
|
||||
if((start_sector>=data_start_sector) || ((data_start_sector > end_sector) && \
|
||||
(data_start_sector != 0x7FF)) || (start_sector > end_sector))
|
||||
return FLASH_PROGRAM_ERROR;
|
||||
|
||||
|
||||
/* unlock slib cfg register */
|
||||
FLASH->slib_unlock = SLIB_UNLOCK_KEY;
|
||||
while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);
|
||||
|
||||
slib_range = ((uint32_t)(data_start_sector << 11) & FLASH_SLIB_DATA_START_SECTOR) | \
|
||||
((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \
|
||||
(start_sector & FLASH_SLIB_START_SECTOR);
|
||||
/* configure slib, set pwd and range */
|
||||
FLASH->slib_set_pwd = pwd;
|
||||
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
|
||||
if(status == FLASH_OPERATE_DONE)
|
||||
{
|
||||
FLASH->slib_set_range = slib_range;
|
||||
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief disable slib when slib enabled.
|
||||
* @param pwd: slib password
|
||||
* @retval success or error
|
||||
*/
|
||||
error_status flash_slib_disable(uint32_t pwd)
|
||||
{
|
||||
flash_status_type status = FLASH_OPERATE_DONE;
|
||||
/* write password to disable slib */
|
||||
FLASH->slib_pwd_clr = pwd;
|
||||
|
||||
status = flash_operation_wait_for(ERASE_TIMEOUT);
|
||||
if(status == FLASH_OPERATE_DONE)
|
||||
{
|
||||
if(FLASH->slib_misc_sts_bit.slib_pwd_ok)
|
||||
return SUCCESS;
|
||||
else
|
||||
return ERROR;
|
||||
}
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get remaining count of slib(range: 256~0).
|
||||
* @param none
|
||||
* @retval uint32_t
|
||||
*/
|
||||
uint32_t flash_slib_remaining_count_get(void)
|
||||
{
|
||||
return (uint32_t)FLASH->slib_misc_sts_bit.slib_rcnt;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get the slib state.
|
||||
* @param none
|
||||
* @retval SET or RESET
|
||||
*/
|
||||
flag_status flash_slib_state_get(void)
|
||||
{
|
||||
if(FLASH->slib_sts0_bit.slib_enf)
|
||||
return SET;
|
||||
else
|
||||
return RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get the start sector of slib.
|
||||
* @param none
|
||||
* @retval uint16_t
|
||||
*/
|
||||
uint16_t flash_slib_start_sector_get(void)
|
||||
{
|
||||
return (uint16_t)FLASH->slib_sts1_bit.slib_ss;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get the data start sector of slib.
|
||||
* @param none
|
||||
* @retval uint16_t
|
||||
*/
|
||||
uint16_t flash_slib_datastart_sector_get(void)
|
||||
{
|
||||
return (uint16_t)FLASH->slib_sts1_bit.slib_dat_ss;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get the end sector of slib.
|
||||
* @param none
|
||||
* @retval uint16_t
|
||||
*/
|
||||
uint16_t flash_slib_end_sector_get(void)
|
||||
{
|
||||
return (uint16_t)FLASH->slib_sts1_bit.slib_es;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief flash crc calibration in main block.
|
||||
* @param start_sector: crc calibration start sector number
|
||||
* sector_cnt: crc calibration sector count
|
||||
* @retval uint32: crc calibration result
|
||||
*/
|
||||
uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt)
|
||||
{
|
||||
FLASH->crc_ctrl_bit.crc_ss = start_sector;
|
||||
FLASH->crc_ctrl_bit.crc_sn = sector_cnt;
|
||||
FLASH->crc_ctrl_bit.crc_strt = TRUE;
|
||||
flash_operation_wait_for(OPERATION_TIMEOUT);
|
||||
return FLASH->crc_chkr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
611
libraries/drivers/src/at32f413_gpio.c
Normal file
611
libraries/drivers/src/at32f413_gpio.c
Normal file
@@ -0,0 +1,611 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_gpio.c
|
||||
* @brief contains all the functions for the gpio firmware library
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#include "at32f413_conf.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO
|
||||
* @brief GPIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef GPIO_MODULE_ENABLED
|
||||
|
||||
/** @defgroup GPIO_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief reset the gpio register
|
||||
* @param gpio_x: to select the gpio peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
|
||||
* @retval none
|
||||
*/
|
||||
void gpio_reset(gpio_type *gpio_x)
|
||||
{
|
||||
if(gpio_x == GPIOA)
|
||||
{
|
||||
crm_periph_reset(CRM_GPIOA_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_GPIOA_PERIPH_RESET, FALSE);
|
||||
}
|
||||
else if(gpio_x == GPIOB)
|
||||
{
|
||||
crm_periph_reset(CRM_GPIOB_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_GPIOB_PERIPH_RESET, FALSE);
|
||||
}
|
||||
else if(gpio_x == GPIOC)
|
||||
{
|
||||
crm_periph_reset(CRM_GPIOC_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_GPIOC_PERIPH_RESET, FALSE);
|
||||
}
|
||||
else if(gpio_x == GPIOD)
|
||||
{
|
||||
crm_periph_reset(CRM_GPIOD_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_GPIOD_PERIPH_RESET, FALSE);
|
||||
}
|
||||
else if(gpio_x == GPIOF)
|
||||
{
|
||||
crm_periph_reset(CRM_GPIOF_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_GPIOF_PERIPH_RESET, FALSE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief reset the mux functions (remap, event control
|
||||
and exint configuration) registers to their default values.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void gpio_iomux_reset(void)
|
||||
{
|
||||
crm_periph_reset(CRM_IOMUX_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_IOMUX_PERIPH_RESET, FALSE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief initialize the gpio peripheral.
|
||||
* @param gpio_x: to select the gpio peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
|
||||
* @param gpio_init_struct: pointer to gpio init structure.
|
||||
* @retval none
|
||||
*/
|
||||
void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct)
|
||||
{
|
||||
uint32_t temp;
|
||||
uint16_t pinx_value, pin_index;
|
||||
|
||||
pin_index = (uint16_t)gpio_init_struct->gpio_pins;
|
||||
|
||||
/* pinx_value indecate pin grounp bit[3:0] from modey[1:0] confy[1:0] */
|
||||
|
||||
/* pin input analog config */
|
||||
if(gpio_init_struct->gpio_mode == GPIO_MODE_ANALOG)
|
||||
{
|
||||
pinx_value = 0x00;
|
||||
}
|
||||
/* pin input config */
|
||||
else if(gpio_init_struct->gpio_mode == GPIO_MODE_INPUT)
|
||||
{
|
||||
pinx_value = gpio_init_struct->gpio_pull & 0x0F;
|
||||
|
||||
if(gpio_init_struct->gpio_pull == GPIO_PULL_UP)
|
||||
{
|
||||
gpio_x->scr = pin_index;
|
||||
}
|
||||
else if(gpio_init_struct->gpio_pull == GPIO_PULL_DOWN)
|
||||
{
|
||||
gpio_x->clr = pin_index;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
pinx_value = (gpio_init_struct->gpio_mode & 0x08) | (gpio_init_struct->gpio_out_type & 0x04) | \
|
||||
(gpio_init_struct->gpio_drive_strength & 0x03);
|
||||
}
|
||||
|
||||
/* pin 0~7 config */
|
||||
if(((uint32_t)pin_index & ((uint32_t)0x00FF)) != 0x00)
|
||||
{
|
||||
for(temp = 0; temp < 0x08; temp++)
|
||||
{
|
||||
if((1 << temp) & pin_index)
|
||||
{
|
||||
gpio_x->cfglr &= (uint32_t)~(0x0F << (temp * 4));
|
||||
gpio_x->cfglr |= (uint32_t)(pinx_value << (temp * 4));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* pin 8~15 config */
|
||||
if(pin_index > 0x00ff)
|
||||
{
|
||||
pin_index = pin_index >> 8;
|
||||
|
||||
for(temp = 0; temp < 0x8; temp++)
|
||||
{
|
||||
if((1 << temp) & pin_index)
|
||||
{
|
||||
gpio_x->cfghr &= (uint32_t)~(0xf << (temp * 4));
|
||||
gpio_x->cfghr |= (uint32_t)(pinx_value << (temp * 4));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief fill each gpio_init_type member with its default value.
|
||||
* @param gpio_init_struct : pointer to a gpio_init_type structure which will be initialized.
|
||||
* @retval none
|
||||
*/
|
||||
void gpio_default_para_init(gpio_init_type *gpio_init_struct)
|
||||
{
|
||||
/* reset gpio init structure parameters values */
|
||||
gpio_init_struct->gpio_pins = GPIO_PINS_ALL;
|
||||
gpio_init_struct->gpio_mode = GPIO_MODE_INPUT;
|
||||
gpio_init_struct->gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct->gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct->gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief read the specified input port pin.
|
||||
* @param gpio_x: to select the gpio peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
|
||||
* @param pins: gpio pin number
|
||||
* this parameter can be one of the following values:
|
||||
* - GPIO_PINS_0
|
||||
* - GPIO_PINS_1
|
||||
* - GPIO_PINS_2
|
||||
* - GPIO_PINS_3
|
||||
* - GPIO_PINS_4
|
||||
* - GPIO_PINS_5
|
||||
* - GPIO_PINS_6
|
||||
* - GPIO_PINS_7
|
||||
* - GPIO_PINS_8
|
||||
* - GPIO_PINS_9
|
||||
* - GPIO_PINS_10
|
||||
* - GPIO_PINS_11
|
||||
* - GPIO_PINS_12
|
||||
* - GPIO_PINS_13
|
||||
* - GPIO_PINS_14
|
||||
* - GPIO_PINS_15
|
||||
* @retval flag_status (SET or RESET)
|
||||
*/
|
||||
flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
|
||||
if(pins != (pins & gpio_x->idt))
|
||||
{
|
||||
status = RESET;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief read the specified gpio input data port.
|
||||
* @param gpio_x: to select the gpio peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
|
||||
* @retval gpio input data port value.
|
||||
*/
|
||||
uint16_t gpio_input_data_read(gpio_type *gpio_x)
|
||||
{
|
||||
return ((uint16_t)(gpio_x->idt));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief read the specified output port pin.
|
||||
* @param gpio_x: to select the gpio peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
|
||||
* @param pins: gpio pin number
|
||||
* this parameter can be one of the following values:
|
||||
* - GPIO_PINS_0
|
||||
* - GPIO_PINS_1
|
||||
* - GPIO_PINS_2
|
||||
* - GPIO_PINS_3
|
||||
* - GPIO_PINS_4
|
||||
* - GPIO_PINS_5
|
||||
* - GPIO_PINS_6
|
||||
* - GPIO_PINS_7
|
||||
* - GPIO_PINS_8
|
||||
* - GPIO_PINS_9
|
||||
* - GPIO_PINS_10
|
||||
* - GPIO_PINS_11
|
||||
* - GPIO_PINS_12
|
||||
* - GPIO_PINS_13
|
||||
* - GPIO_PINS_14
|
||||
* - GPIO_PINS_15
|
||||
* @retval flag_status (SET or RESET)
|
||||
*/
|
||||
flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
|
||||
if((gpio_x->odt & pins) != RESET)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = RESET;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief read the specified gpio ouput data port.
|
||||
* @param gpio_x: to select the gpio peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
|
||||
* @retval gpio input data port value.
|
||||
*/
|
||||
uint16_t gpio_output_data_read(gpio_type *gpio_x)
|
||||
{
|
||||
return ((uint16_t)(gpio_x->odt));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set the selected data port bits.
|
||||
* @param gpio_x: to select the gpio peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
|
||||
* @param pins: gpio pin number
|
||||
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
|
||||
* - GPIO_PINS_0
|
||||
* - GPIO_PINS_1
|
||||
* - GPIO_PINS_2
|
||||
* - GPIO_PINS_3
|
||||
* - GPIO_PINS_4
|
||||
* - GPIO_PINS_5
|
||||
* - GPIO_PINS_6
|
||||
* - GPIO_PINS_7
|
||||
* - GPIO_PINS_8
|
||||
* - GPIO_PINS_9
|
||||
* - GPIO_PINS_10
|
||||
* - GPIO_PINS_11
|
||||
* - GPIO_PINS_12
|
||||
* - GPIO_PINS_13
|
||||
* - GPIO_PINS_14
|
||||
* - GPIO_PINS_15
|
||||
* - GPIO_PINS_ALL
|
||||
* @retval none
|
||||
*/
|
||||
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins)
|
||||
{
|
||||
gpio_x->scr = pins;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear the selected data port bits.
|
||||
* @param gpio_x: to select the gpio peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
|
||||
* @param pins: gpio pin number
|
||||
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
|
||||
* - GPIO_PINS_0
|
||||
* - GPIO_PINS_1
|
||||
* - GPIO_PINS_2
|
||||
* - GPIO_PINS_3
|
||||
* - GPIO_PINS_4
|
||||
* - GPIO_PINS_5
|
||||
* - GPIO_PINS_6
|
||||
* - GPIO_PINS_7
|
||||
* - GPIO_PINS_8
|
||||
* - GPIO_PINS_9
|
||||
* - GPIO_PINS_10
|
||||
* - GPIO_PINS_11
|
||||
* - GPIO_PINS_12
|
||||
* - GPIO_PINS_13
|
||||
* - GPIO_PINS_14
|
||||
* - GPIO_PINS_15
|
||||
* - GPIO_PINS_ALL
|
||||
* @retval none
|
||||
*/
|
||||
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins)
|
||||
{
|
||||
gpio_x->clr = pins;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set or clear the selected data port bit.
|
||||
* @param gpio_x: to select the gpio peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
|
||||
* @param pins: gpio pin number
|
||||
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
|
||||
* - GPIO_PINS_0
|
||||
* - GPIO_PINS_1
|
||||
* - GPIO_PINS_2
|
||||
* - GPIO_PINS_3
|
||||
* - GPIO_PINS_4
|
||||
* - GPIO_PINS_5
|
||||
* - GPIO_PINS_6
|
||||
* - GPIO_PINS_7
|
||||
* - GPIO_PINS_8
|
||||
* - GPIO_PINS_9
|
||||
* - GPIO_PINS_10
|
||||
* - GPIO_PINS_11
|
||||
* - GPIO_PINS_12
|
||||
* - GPIO_PINS_13
|
||||
* - GPIO_PINS_14
|
||||
* - GPIO_PINS_15
|
||||
* - GPIO_PINS_ALL
|
||||
* @param bit_state: specifies the value to be written to the selected bit (TRUE or FALSE).
|
||||
* @retval none
|
||||
*/
|
||||
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state)
|
||||
{
|
||||
if(bit_state != FALSE)
|
||||
{
|
||||
gpio_x->scr = pins;
|
||||
}
|
||||
else
|
||||
{
|
||||
gpio_x->clr = pins;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief write data to the specified gpio data port.
|
||||
* @param gpio_x: to select the gpio peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
|
||||
* @param port_value: specifies the value to be written to the port output data register.
|
||||
* @retval none
|
||||
*/
|
||||
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value)
|
||||
{
|
||||
gpio_x->odt = port_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief write protect gpio pins configuration registers.
|
||||
* @param gpio_x: to select the gpio peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* GPIOA, GPIOB, GPIOC, GPIOD, GPIOF.
|
||||
* @param pins: gpio pin number
|
||||
* this parameter can be any combination of the following:
|
||||
* - GPIO_PINS_0
|
||||
* - GPIO_PINS_1
|
||||
* - GPIO_PINS_2
|
||||
* - GPIO_PINS_3
|
||||
* - GPIO_PINS_4
|
||||
* - GPIO_PINS_5
|
||||
* - GPIO_PINS_6
|
||||
* - GPIO_PINS_7
|
||||
* - GPIO_PINS_8
|
||||
* - GPIO_PINS_9
|
||||
* - GPIO_PINS_10
|
||||
* - GPIO_PINS_11
|
||||
* - GPIO_PINS_12
|
||||
* - GPIO_PINS_13
|
||||
* - GPIO_PINS_14
|
||||
* - GPIO_PINS_15
|
||||
* - GPIO_PINS_ALL
|
||||
* @retval none
|
||||
*/
|
||||
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins)
|
||||
{
|
||||
uint32_t temp = 0x00010000;
|
||||
|
||||
temp |= pins;
|
||||
/* set wpen bit */
|
||||
gpio_x->wpr = temp;
|
||||
/* reset wpen bit */
|
||||
gpio_x->wpr = pins;
|
||||
/* set wpen bit */
|
||||
gpio_x->wpr = temp;
|
||||
/* read wpen bit*/
|
||||
temp = gpio_x->wpr;
|
||||
/* read wpen bit*/
|
||||
temp = gpio_x->wpr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief select the gpio pin used as event output.
|
||||
* @param gpio_port_source: select the gpio port to be used as source
|
||||
* for event output.
|
||||
* this parameter can be one of the following values:
|
||||
* - GPIO_PORT_SOURCE_GPIOA
|
||||
* - GPIO_PORT_SOURCE_GPIOB
|
||||
* - GPIO_PORT_SOURCE_GPIOC
|
||||
* - GPIO_PORT_SOURCE_GPIOD
|
||||
* - GPIO_PORT_SOURCE_GPIOF
|
||||
* @param gpio_pin_source: specifies the pin for the event output.
|
||||
* this parameter can be one of the following values:
|
||||
* - GPIO_PINS_SOURCE0
|
||||
* - GPIO_PINS_SOURCE1
|
||||
* - GPIO_PINS_SOURCE2
|
||||
* - GPIO_PINS_SOURCE3
|
||||
* - GPIO_PINS_SOURCE4
|
||||
* - GPIO_PINS_SOURCE5
|
||||
* - GPIO_PINS_SOURCE6
|
||||
* - GPIO_PINS_SOURCE7
|
||||
* - GPIO_PINS_SOURCE8
|
||||
* - GPIO_PINS_SOURCE9
|
||||
* - GPIO_PINS_SOURCE10
|
||||
* - GPIO_PINS_SOURCE11
|
||||
* - GPIO_PINS_SOURCE12
|
||||
* - GPIO_PINS_SOURCE13
|
||||
* - GPIO_PINS_SOURCE14
|
||||
* - GPIO_PINS_SOURCE15
|
||||
* @retval none
|
||||
*/
|
||||
void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source)
|
||||
{
|
||||
uint32_t tmpreg = 0x00;
|
||||
|
||||
tmpreg = IOMUX->evtout;
|
||||
|
||||
/* clear the port[6:4] and pin[3:0] bits */
|
||||
tmpreg &= 0x80;
|
||||
tmpreg |= (uint32_t)gpio_port_source << 0x04;
|
||||
tmpreg |= gpio_pin_source;
|
||||
IOMUX->evtout = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the event output.
|
||||
* @param confirm_state: new state of the event output.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void gpio_event_output_enable(confirm_state new_state)
|
||||
{
|
||||
IOMUX->evtout_bit.evoen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief iomux remap and debug i/o configuration.
|
||||
* @param gpio_remap: select the pin to remap.
|
||||
* this parameter can be one of the following values:
|
||||
* - SPI1_MUX_01 - I2C1_MUX - USART1_MUX - USART3_MUX_01
|
||||
* - TMR1_MUX_01 - TMR2_MUX_01 - TMR2_MUX_10 - TMR2_MUX_11
|
||||
* - TMR3_MUX_10 - TMR3_MUX_11 - CAN_MUX_10 - PD01_MUX
|
||||
* - TMR5CH4_MUX - ADC1_EXTRGPRE_MUX - ADC1_EXTRGORD_MUX - ADC2_EXTRGPRE_MUX
|
||||
* - ADC2_EXTRGORD_MUX - SWJTAG_CONF_001 - SWJTAG_CONF_010 - SWJTAG_CONF_100
|
||||
* - EXT_SPIM_EN_MUX - TMR9_GMUX - TMR10_GMUX - TMR11_GMUX
|
||||
* - TMR1_GMUX_0001 - TMR2_GMUX_001 - TMR2_GMUX_010 - TMR2_GMUX_011
|
||||
* - TMR2ITR1_GMUX - TMR3_GMUX_0010 - TMR3_GMUX_0011 - TMR5_GMUX_001
|
||||
* - TMR5CH4_GMUX - I2C1_GMUX_0001 - I2C1_GMUX_0011 - I2C2_GMUX_0001
|
||||
* - I2C2_GMUX_0010 - I2C2_GMUX_0011 - SPI1_GMUX_0001 - SPI2_GMUX_0001
|
||||
* - CAN1_GMUX_0010 - CAN2_GMUX_0001 - SDIO1_GMUX_0100 - SDIO1_GMUX_0101
|
||||
* - SDIO1_GMUX_0110 - SDIO1_GMUX_0111 - USART1_GMUX_0001 - USART3_GMUX_0001
|
||||
* - UART4_GMUX_0001 - EXT_SPIM_GMUX_1000 - EXT_SPIM_GMUX_1001 - ADC1_ETP_GMUX
|
||||
* - ADC1_ETO_GMUX - ADC2_ETP_GMUX - ADC2_ETO_GMUX - SWJTAG_GMUX_001
|
||||
* - SWJTAG_GMUX_010 - SWJTAG_GMUX_100 - PD01_GMUX
|
||||
* @param new_state: (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void gpio_pin_remap_config(uint32_t gpio_remap, confirm_state new_state)
|
||||
{
|
||||
uint32_t reg_addr, remap_mask;
|
||||
uint8_t bit_offset, bit_num, bit_val;
|
||||
|
||||
/* get register address, bit offset, bit number and remap value */
|
||||
reg_addr = IOMUX_BASE + (gpio_remap >> 24);
|
||||
bit_offset = (gpio_remap >> 16) & 0xFF;
|
||||
bit_num = (gpio_remap >> 8) & 0xFF;
|
||||
bit_val = gpio_remap & 0xFF;
|
||||
|
||||
/* get remap mask value */
|
||||
remap_mask = 0xFFFFFFFF << (32 - bit_num - bit_offset);
|
||||
remap_mask = remap_mask >> (32 - bit_num - bit_offset);
|
||||
remap_mask = remap_mask >> bit_offset;
|
||||
remap_mask = remap_mask << bit_offset;
|
||||
|
||||
/* clear remap value */
|
||||
*(uint32_t*)reg_addr &= ~remap_mask;
|
||||
|
||||
if(new_state != FALSE)
|
||||
{
|
||||
/* set remap value */
|
||||
*(uint32_t*)reg_addr |= (uint32_t)(bit_val << bit_offset);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief select the gpio pin used as exint line.
|
||||
* @param gpio_port_source: select the gpio port to be used as source for exint.
|
||||
* this parameter can be one of the following values:
|
||||
* - GPIO_PORT_SOURCE_GPIOA
|
||||
* - GPIO_PORT_SOURCE_GPIOB
|
||||
* - GPIO_PORT_SOURCE_GPIOC
|
||||
* - GPIO_PORT_SOURCE_GPIOD
|
||||
* - GPIO_PORT_SOURCE_GPIOF
|
||||
* @param gpio_pin_source: specifies the pin for the event output.
|
||||
* this parameter can be one of the following values:
|
||||
* - GPIO_PINS_SOURCE0
|
||||
* - GPIO_PINS_SOURCE1
|
||||
* - GPIO_PINS_SOURCE2
|
||||
* - GPIO_PINS_SOURCE3
|
||||
* - GPIO_PINS_SOURCE4
|
||||
* - GPIO_PINS_SOURCE5
|
||||
* - GPIO_PINS_SOURCE6
|
||||
* - GPIO_PINS_SOURCE7
|
||||
* - GPIO_PINS_SOURCE8
|
||||
* - GPIO_PINS_SOURCE9
|
||||
* - GPIO_PINS_SOURCE10
|
||||
* - GPIO_PINS_SOURCE11
|
||||
* - GPIO_PINS_SOURCE12
|
||||
* - GPIO_PINS_SOURCE13
|
||||
* - GPIO_PINS_SOURCE14
|
||||
* - GPIO_PINS_SOURCE15
|
||||
* @retval none
|
||||
*/
|
||||
void gpio_exint_line_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source)
|
||||
{
|
||||
uint32_t tmp = 0x00;
|
||||
tmp = ((uint32_t)0x0F) << (0x04 * (gpio_pin_source & (uint8_t)0x03));
|
||||
|
||||
switch (gpio_pin_source >> 0x02)
|
||||
{
|
||||
case 0:
|
||||
IOMUX->exintc1 &= ~tmp;
|
||||
IOMUX->exintc1 |= (((uint32_t)gpio_port_source) << (0x04 * (gpio_pin_source & (uint8_t)0x03)));
|
||||
break;
|
||||
case 1:
|
||||
IOMUX->exintc2 &= ~tmp;
|
||||
IOMUX->exintc2 |= (((uint32_t)gpio_port_source) << (0x04 * (gpio_pin_source & (uint8_t)0x03)));
|
||||
break;
|
||||
case 2:
|
||||
IOMUX->exintc3 &= ~tmp;
|
||||
IOMUX->exintc3 |= (((uint32_t)gpio_port_source) << (0x04 * (gpio_pin_source & (uint8_t)0x03)));
|
||||
break;
|
||||
case 3:
|
||||
IOMUX->exintc4 &= ~tmp;
|
||||
IOMUX->exintc4 |= (((uint32_t)gpio_port_source) << (0x04 * (gpio_pin_source & (uint8_t)0x03)));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
171
libraries/drivers/src/at32f413_misc.c
Normal file
171
libraries/drivers/src/at32f413_misc.c
Normal file
@@ -0,0 +1,171 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_misc.c
|
||||
* @brief contains all the functions for the misc firmware library
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f413_conf.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC
|
||||
* @brief MISC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef MISC_MODULE_ENABLED
|
||||
|
||||
/** @defgroup MISC_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
||||
|
||||
/**
|
||||
* @brief system reset
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void nvic_system_reset(void)
|
||||
{
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable nvic irq
|
||||
* @param irqn (IRQn_Type number)
|
||||
* @param preempt_priority: preemptive priority value (starting from 0)
|
||||
* @param sub_priority: subpriority value (starting from 0)
|
||||
* @retval none
|
||||
*/
|
||||
void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority)
|
||||
{
|
||||
uint32_t temp_priority = 0;
|
||||
|
||||
/* encode priority */
|
||||
temp_priority = NVIC_EncodePriority(NVIC_GetPriorityGrouping(), preempt_priority, sub_priority);
|
||||
/* set priority */
|
||||
NVIC_SetPriority(irqn, temp_priority);
|
||||
/* enable irqn */
|
||||
NVIC_EnableIRQ(irqn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief disable nvic irq number
|
||||
* @param irqn (IRQn_Type number)
|
||||
* @retval none
|
||||
*/
|
||||
void nvic_irq_disable(IRQn_Type irqn)
|
||||
{
|
||||
NVIC_DisableIRQ(irqn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief config nvic priority group
|
||||
* @param priority_group
|
||||
* this parameter can be one of the following values:
|
||||
* - NVIC_PRIORITY_GROUP_0
|
||||
* - NVIC_PRIORITY_GROUP_1
|
||||
* - NVIC_PRIORITY_GROUP_2
|
||||
* - NVIC_PRIORITY_GROUP_3
|
||||
* - NVIC_PRIORITY_GROUP_4
|
||||
* @retval none
|
||||
*/
|
||||
void nvic_priority_group_config(nvic_priority_group_type priority_group)
|
||||
{
|
||||
/* set the prigroup[10:8] bits according to nvic_prioritygroup value */
|
||||
NVIC_SetPriorityGrouping(priority_group);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set the vector table location and offset.
|
||||
* @param base
|
||||
* this parameter can be one of the following values:
|
||||
* - NVIC_VECTTAB_RAM
|
||||
* - NVIC_VECTTAB_FLASH
|
||||
* @param offset (vector table base offset field. this value must be a multiple of 0x200)
|
||||
* @retval none
|
||||
*/
|
||||
void nvic_vector_table_set(uint32_t base, uint32_t offset)
|
||||
{
|
||||
SCB->VTOR = base | (offset & (uint32_t)0x1FFFFF80);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief config nvic lowpower mode
|
||||
* @param lp_mode
|
||||
* this parameter can be one of the following values:
|
||||
* - NVIC_LP_SEVONPEND
|
||||
* - NVIC_LP_SLEEPDEEP
|
||||
* - NVIC_LP_SLEEPONEXIT
|
||||
* @param new_state (new state of lp condition. ENABLE or DISABLE)
|
||||
* @retval none
|
||||
*/
|
||||
void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state)
|
||||
{
|
||||
if(new_state != FALSE)
|
||||
{
|
||||
SCB->SCR |= lp_mode;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SCR &= (uint32_t)(~(uint32_t)lp_mode);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief config systick clock source
|
||||
* @param source
|
||||
* this parameter can be one of the following values:
|
||||
* - SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8
|
||||
* - SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV
|
||||
* @retval none
|
||||
*/
|
||||
void systick_clock_source_config(systick_clock_source_type source)
|
||||
{
|
||||
if(source == SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV)
|
||||
{
|
||||
SysTick->CTRL |= SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= ~(uint32_t)SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
234
libraries/drivers/src/at32f413_pwc.c
Normal file
234
libraries/drivers/src/at32f413_pwc.c
Normal file
@@ -0,0 +1,234 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_pwc.c
|
||||
* @brief contains all the functions for the pwc firmware library
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#include "at32f413_conf.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWC
|
||||
* @brief PWC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef PWC_MODULE_ENABLED
|
||||
|
||||
/** @defgroup PWC_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief deinitialize the pwc peripheral registers to their default reset values.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void pwc_reset(void)
|
||||
{
|
||||
crm_periph_reset(CRM_PWC_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_PWC_PERIPH_RESET, FALSE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable access to the battery powered domain.
|
||||
* @param new_state: new state of battery powered domain access.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void pwc_battery_powered_domain_access(confirm_state new_state)
|
||||
{
|
||||
PWC->ctrl_bit.bpwen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief select the voltage threshold detected by the power voltage detector.
|
||||
* @param pvm_voltage: select pwc pvm voltage
|
||||
* this parameter can be one of the following values:
|
||||
* - PWC_PVM_VOLTAGE_2V3
|
||||
* - PWC_PVM_VOLTAGE_2V4
|
||||
* - PWC_PVM_VOLTAGE_2V5
|
||||
* - PWC_PVM_VOLTAGE_2V6
|
||||
* - PWC_PVM_VOLTAGE_2V7
|
||||
* - PWC_PVM_VOLTAGE_2V8
|
||||
* - PWC_PVM_VOLTAGE_2V9
|
||||
* @retval none
|
||||
*/
|
||||
void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage)
|
||||
{
|
||||
PWC->ctrl_bit.pvmsel = pvm_voltage;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable pwc power voltage monitor (pvm)
|
||||
* @param new_state: new state of pvm.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void pwc_power_voltage_monitor_enable(confirm_state new_state)
|
||||
{
|
||||
PWC->ctrl_bit.pvmen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable pwc standby wakeup pin
|
||||
* @param pin_num: choose the wakeup pin.
|
||||
* this parameter can be be any combination of the following values:
|
||||
* - PWC_WAKEUP_PIN_1
|
||||
* @param new_state: new state of the standby wakeup pin.
|
||||
* this parameter can be one of the following values:
|
||||
* - TRUE <wakeup pin is used for wake up cpu from standby mode>
|
||||
* - FALSE <wakeup pin is used for general purpose I/O>
|
||||
* @retval none
|
||||
*/
|
||||
void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state)
|
||||
{
|
||||
if(new_state == TRUE)
|
||||
{
|
||||
PWC->ctrlsts |= pin_num;
|
||||
}
|
||||
else
|
||||
{
|
||||
PWC->ctrlsts &= ~pin_num;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear flag of pwc
|
||||
* @param pwc_flag: select the pwc flag.
|
||||
* this parameter can be any combination of the following values:
|
||||
* - PWC_WAKEUP_FLAG
|
||||
* - PWC_STANDBY_FLAG
|
||||
* - note:"PWC_PVM_OUTPUT_FLAG" cannot be choose!this bit is readonly bit,it means the voltage monitoring output state
|
||||
* @retval none
|
||||
*/
|
||||
void pwc_flag_clear(uint32_t pwc_flag)
|
||||
{
|
||||
if(pwc_flag & PWC_STANDBY_FLAG)
|
||||
PWC->ctrl_bit.clsef = TRUE;
|
||||
if(pwc_flag & PWC_WAKEUP_FLAG)
|
||||
PWC->ctrl_bit.clswef = TRUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get flag of pwc
|
||||
* @param pwc_flag: select the pwc flag.
|
||||
* this parameter can be one of the following values:
|
||||
* - PWC_WAKEUP_FLAG
|
||||
* - PWC_STANDBY_FLAG
|
||||
* - PWC_PVM_OUTPUT_FLAG
|
||||
* @retval state of select flag(SET or RESET).
|
||||
*/
|
||||
flag_status pwc_flag_get(uint32_t pwc_flag)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
if ((PWC->ctrlsts & pwc_flag) == RESET)
|
||||
{
|
||||
status = RESET;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enter pwc sleep mode
|
||||
* @param sleep_mode_enter: choose the instruction to enter sleep mode.
|
||||
* this parameter can be one of the following values:
|
||||
* - PWC_SLEEP_ENTER_WFI
|
||||
* - PWC_SLEEP_ENTER_WFE
|
||||
* @retval none
|
||||
*/
|
||||
void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter)
|
||||
{
|
||||
SCB->SCR &= (uint32_t)~0x4;
|
||||
if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFE)
|
||||
{
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
else if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFI)
|
||||
{
|
||||
__WFI();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enter pwc deep-sleep mode
|
||||
* @param pwc_deep_sleep_enter: choose the instruction to enter deep sleep mode.
|
||||
* this parameter can be one of the following values:
|
||||
* - PWC_DEEP_SLEEP_ENTER_WFI
|
||||
* - PWC_DEEP_SLEEP_ENTER_WFE
|
||||
* @retval none
|
||||
*/
|
||||
void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter)
|
||||
{
|
||||
SCB->SCR |= 0x04;
|
||||
if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFE)
|
||||
{
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
else if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFI)
|
||||
{
|
||||
__WFI();
|
||||
}
|
||||
SCB->SCR &= (uint32_t)~0x4;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enter pwc standby mode
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void pwc_standby_mode_enter(void)
|
||||
{
|
||||
PWC->ctrl_bit.clswef = TRUE;
|
||||
PWC->ctrl_bit.lpsel = TRUE;
|
||||
SCB->SCR |= 0x04;
|
||||
#if defined (__CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
while(1)
|
||||
{
|
||||
__WFI();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
1779
libraries/drivers/src/at32f413_tmr.c
Normal file
1779
libraries/drivers/src/at32f413_tmr.c
Normal file
File diff suppressed because it is too large
Load Diff
700
libraries/drivers/src/at32f413_usart.c
Normal file
700
libraries/drivers/src/at32f413_usart.c
Normal file
@@ -0,0 +1,700 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_usart.c
|
||||
* @brief contains all the functions for the usart firmware library
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f413_conf.h"
|
||||
|
||||
/** @addtogroup AT32F413_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USART
|
||||
* @brief USART driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef USART_MODULE_ENABLED
|
||||
|
||||
/** @defgroup USART_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief deinitialize the usart peripheral registers to their default reset values.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_reset(usart_type* usart_x)
|
||||
{
|
||||
if(usart_x == USART1)
|
||||
{
|
||||
crm_periph_reset(CRM_USART1_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_USART1_PERIPH_RESET, FALSE);
|
||||
}
|
||||
else if(usart_x == USART2)
|
||||
{
|
||||
crm_periph_reset(CRM_USART2_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_USART2_PERIPH_RESET, FALSE);
|
||||
}
|
||||
#if defined (AT32F413Rx) || defined (AT32F413Cx) || defined (AT32FEBKC8T7)
|
||||
else if(usart_x == USART3)
|
||||
{
|
||||
crm_periph_reset(CRM_USART3_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_USART3_PERIPH_RESET, FALSE);
|
||||
}
|
||||
#endif
|
||||
#if defined (AT32F413Rx)
|
||||
else if(usart_x == UART4)
|
||||
{
|
||||
crm_periph_reset(CRM_UART4_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_UART4_PERIPH_RESET, FALSE);
|
||||
}
|
||||
else if(usart_x == UART5)
|
||||
{
|
||||
crm_periph_reset(CRM_UART5_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_UART5_PERIPH_RESET, FALSE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief initialize the usart peripheral according to the specified parameters.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param baud_rate: configure the usart communication baud rate.
|
||||
* @param data_bit: data bits transmitted or received in a frame
|
||||
* this parameter can be one of the following values:
|
||||
* - USART_DATA_8BITS
|
||||
* - USART_DATA_9BITS.
|
||||
* note：
|
||||
* - when parity check is disabled, the data bit width is the actual data bit number.
|
||||
* - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit.
|
||||
* @param stop_bit: stop bits transmitted
|
||||
* this parameter can be one of the following values:
|
||||
* - USART_STOP_1_BIT
|
||||
* - USART_STOP_0_5_BIT.
|
||||
* - USART_STOP_2_BIT
|
||||
* - USART_STOP_1_5_BIT.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit)
|
||||
{
|
||||
crm_clocks_freq_type clocks_freq;
|
||||
uint32_t apb_clock, temp_val;
|
||||
crm_clocks_freq_get(&clocks_freq);
|
||||
if(usart_x == USART1)
|
||||
{
|
||||
apb_clock = clocks_freq.apb2_freq;
|
||||
}
|
||||
else
|
||||
{
|
||||
apb_clock = clocks_freq.apb1_freq;
|
||||
}
|
||||
temp_val = (apb_clock * 10 / baud_rate);
|
||||
if((temp_val % 10) < 5)
|
||||
{
|
||||
temp_val = (temp_val / 10);
|
||||
}
|
||||
else
|
||||
{
|
||||
temp_val = (temp_val / 10) + 1;
|
||||
}
|
||||
usart_x->baudr_bit.div = temp_val;
|
||||
usart_x->ctrl1_bit.dbn = data_bit;
|
||||
usart_x->ctrl2_bit.stopbn = stop_bit;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usart parity selection config.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param parity: select the none, odd or even parity.
|
||||
* this parameter can be one of the following values:
|
||||
* - USART_PARITY_NONE
|
||||
* - USART_PARITY_EVEN.
|
||||
* - USART_PARITY_ODD
|
||||
* @retval none
|
||||
*/
|
||||
void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity)
|
||||
{
|
||||
if(parity == USART_PARITY_NONE)
|
||||
{
|
||||
usart_x->ctrl1_bit.psel = FALSE;
|
||||
usart_x->ctrl1_bit.pen = FALSE;
|
||||
}
|
||||
else if(parity == USART_PARITY_EVEN)
|
||||
{
|
||||
usart_x->ctrl1_bit.psel = FALSE;
|
||||
usart_x->ctrl1_bit.pen = TRUE;
|
||||
}
|
||||
else if(parity == USART_PARITY_ODD)
|
||||
{
|
||||
usart_x->ctrl1_bit.psel = TRUE;
|
||||
usart_x->ctrl1_bit.pen = TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the specified usart peripheral.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param new_state: new state of the usart peripheral.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_enable(usart_type* usart_x, confirm_state new_state)
|
||||
{
|
||||
usart_x->ctrl1_bit.uen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usart transmitter enable.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param new_state: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state)
|
||||
{
|
||||
usart_x->ctrl1_bit.ten = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usart receiver enable.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param new_state: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_receiver_enable(usart_type* usart_x, confirm_state new_state)
|
||||
{
|
||||
usart_x->ctrl1_bit.ren = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usart clock config.
|
||||
* @note clock config are not available for UART4 and UART5.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2 or USART3.
|
||||
* @param clk_pol: polarity of the clock output on the ck pin.
|
||||
* this parameter can be one of the following values:
|
||||
* - USART_CLOCK_POLARITY_LOW
|
||||
* - USART_CLOCK_POLARITY_HIGH
|
||||
* @param clk_pha: phase of the clock output on the ck pin.
|
||||
* this parameter can be one of the following values:
|
||||
* - USART_CLOCK_PHASE_1EDGE
|
||||
* - USART_CLOCK_PHASE_2EDGE
|
||||
* @param clk_lb: whether the clock pulse of the last data bit transmitted (MSB) is outputted on the ck pin.
|
||||
* this parameter can be one of the following values:
|
||||
* - USART_CLOCK_LAST_BIT_NONE
|
||||
* - USART_CLOCK_LAST_BIT_OUTPUT
|
||||
* @retval none
|
||||
*/
|
||||
void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb)
|
||||
{
|
||||
usart_x->ctrl2_bit.clkpol = clk_pol;
|
||||
usart_x->ctrl2_bit.clkpha = clk_pha;
|
||||
usart_x->ctrl2_bit.lbcp = clk_lb;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usart enable the ck pin.
|
||||
* @note clock enable are not available for UART4 and UART5.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2 or USART3.
|
||||
* @param new_state: TRUE or FALSE
|
||||
* @retval none
|
||||
*/
|
||||
void usart_clock_enable(usart_type* usart_x, confirm_state new_state)
|
||||
{
|
||||
usart_x->ctrl2_bit.clken = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the specified usart interrupts.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param usart_int: specifies the USART interrupt sources to be enabled or disabled.
|
||||
* this parameter can be one of the following values:
|
||||
* - USART_IDLE_INT: idle interrupt
|
||||
* - USART_RDBF_INT: rdbf interrupt
|
||||
* - USART_TDC_INT: tdc interrupt
|
||||
* - USART_TDBE_INT: tdbe interrupt
|
||||
* - USART_PERR_INT: perr interrupt
|
||||
* - USART_BF_INT: break frame interrupt
|
||||
* - USART_ERR_INT: err interrupt
|
||||
* - USART_CTSCF_INT: ctscf interrupt
|
||||
* @param new_state: new state of the specified usart interrupts.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state)
|
||||
{
|
||||
if(new_state == TRUE)
|
||||
PERIPH_REG((uint32_t)usart_x, usart_int) |= PERIPH_REG_BIT(usart_int);
|
||||
else
|
||||
PERIPH_REG((uint32_t)usart_x, usart_int) &= ~PERIPH_REG_BIT(usart_int);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the usart's dma transmitter interface.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param new_state: new state of the dma request sources.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state)
|
||||
{
|
||||
usart_x->ctrl3_bit.dmaten = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the usart's dma receiver interface.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param new_state: new state of the dma request sources.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state)
|
||||
{
|
||||
usart_x->ctrl3_bit.dmaren = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set the wakeup id of the usart.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param usart_id: the matching id(0x0~0xF).
|
||||
* @retval none
|
||||
*/
|
||||
void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id)
|
||||
{
|
||||
usart_x->ctrl2_bit.id = usart_id;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief select the usart wakeup method in multi-processor communication.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param wakeup_mode: determines the way to wake up usart method.
|
||||
* this parameter can be one of the following values:
|
||||
* - USART_WAKEUP_BY_IDLE_FRAME
|
||||
* - USART_WAKEUP_BY_MATCHING_ID
|
||||
* @retval none
|
||||
*/
|
||||
void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode)
|
||||
{
|
||||
usart_x->ctrl1_bit.wum = wakeup_mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief config the usart in mute mode in multi-processor communication.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param new_state: new state of the usart mute mode.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state)
|
||||
{
|
||||
usart_x->ctrl1_bit.rm = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set the usart break frame bit num.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param break_bit: specifies the break bit num.
|
||||
* this parameter can be one of the following values:
|
||||
* - USART_BREAK_10BITS
|
||||
* - USART_BREAK_11BITS
|
||||
* @retval none
|
||||
*/
|
||||
void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit)
|
||||
{
|
||||
usart_x->ctrl2_bit.bfbn = break_bit;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the usart lin mode.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param new_state: new state of the usart lin mode.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state)
|
||||
{
|
||||
usart_x->ctrl2_bit.linen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief transmit single data through the usart peripheral.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param data: the data to transmit.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_data_transmit(usart_type* usart_x, uint16_t data)
|
||||
{
|
||||
usart_x->dt = (data & 0x01FF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return the most recent received data by the usart peripheral.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @retval the received data.
|
||||
*/
|
||||
uint16_t usart_data_receive(usart_type* usart_x)
|
||||
{
|
||||
return (uint16_t)(usart_x->dt);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief transmit break characters.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_break_send(usart_type* usart_x)
|
||||
{
|
||||
usart_x->ctrl1_bit.sbf = TRUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief config the specified usart smartcard guard time.
|
||||
* @note The guard time bits are not available for UART4 and UART5.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2 or USART3.
|
||||
* @param guard_time_val: specifies the guard time (0x00~0xFF).
|
||||
* @retval none
|
||||
*/
|
||||
void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val)
|
||||
{
|
||||
usart_x->gdiv_bit.scgt = guard_time_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief config the irda/smartcard division.
|
||||
* @note the division are not available for UART4 and UART5.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2 or USART3.
|
||||
* @param div_val: specifies the division.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val)
|
||||
{
|
||||
usart_x->gdiv_bit.isdiv = div_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the usart smart card mode.
|
||||
* @note the smart card mode are not available for UART4 and UART5.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2 or USART3.
|
||||
* @param new_state: new state of the smart card mode.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state)
|
||||
{
|
||||
usart_x->ctrl3_bit.scmen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable nack transmission in smartcard mode.
|
||||
* @note the smart card nack are not available for UART4 and UART5.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2 or USART3.
|
||||
* @param new_state: new state of the nack transmission.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state)
|
||||
{
|
||||
usart_x->ctrl3_bit.scnacken = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the usart single line bidirectional half-duplex communication.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param new_state: new state of the single line half-duplex select.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state)
|
||||
{
|
||||
usart_x->ctrl3_bit.slben = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the usart's irda interface.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param new_state: new state of the irda mode.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state)
|
||||
{
|
||||
usart_x->ctrl3_bit.irdaen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief configure the usart's irda low power.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param new_state: new state of the irda mode.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state)
|
||||
{
|
||||
usart_x->ctrl3_bit.irdalp = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief configure the usart's hardware flow control.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2 or USART3
|
||||
* @param flow_state: specifies the hardware flow control.
|
||||
* this parameter can be one of the following values:
|
||||
* - USART_HARDWARE_FLOW_NONE
|
||||
* - USART_HARDWARE_FLOW_RTS,
|
||||
* - USART_HARDWARE_FLOW_CTS,
|
||||
* - USART_HARDWARE_FLOW_RTS_CTS
|
||||
* @retval none
|
||||
*/
|
||||
void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state)
|
||||
{
|
||||
if(flow_state == USART_HARDWARE_FLOW_NONE)
|
||||
{
|
||||
usart_x->ctrl3_bit.rtsen = FALSE;
|
||||
usart_x->ctrl3_bit.ctsen = FALSE;
|
||||
}
|
||||
else if(flow_state == USART_HARDWARE_FLOW_RTS)
|
||||
{
|
||||
usart_x->ctrl3_bit.rtsen = TRUE;
|
||||
usart_x->ctrl3_bit.ctsen = FALSE;
|
||||
}
|
||||
else if(flow_state == USART_HARDWARE_FLOW_CTS)
|
||||
{
|
||||
usart_x->ctrl3_bit.rtsen = FALSE;
|
||||
usart_x->ctrl3_bit.ctsen = TRUE;
|
||||
}
|
||||
else if(flow_state == USART_HARDWARE_FLOW_RTS_CTS)
|
||||
{
|
||||
usart_x->ctrl3_bit.rtsen = TRUE;
|
||||
usart_x->ctrl3_bit.ctsen = TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief check whether the specified usart flag is set or not.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param flag: specifies the flag to check.
|
||||
* this parameter can be one of the following values:
|
||||
* - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5,USART6,UART7 and UART8)
|
||||
* - USART_BFF_FLAG: break frame flag
|
||||
* - USART_TDBE_FLAG: transmit data buffer empty flag
|
||||
* - USART_TDC_FLAG: transmit data complete flag
|
||||
* - USART_RDBF_FLAG: receive data buffer full flag
|
||||
* - USART_IDLEF_FLAG: idle flag
|
||||
* - USART_ROERR_FLAG: receiver overflow error flag
|
||||
* - USART_NERR_FLAG: noise error flag
|
||||
* - USART_FERR_FLAG: framing error flag
|
||||
* - USART_PERR_FLAG: parity error flag
|
||||
* @retval the new state of usart_flag (SET or RESET).
|
||||
*/
|
||||
flag_status usart_flag_get(usart_type* usart_x, uint32_t flag)
|
||||
{
|
||||
if(usart_x->sts & flag)
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief check whether the specified usart interrupt flag is set or not.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4, UART5.
|
||||
* @param flag: specifies the flag to check.
|
||||
* this parameter can be one of the following values:
|
||||
* - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5)
|
||||
* - USART_BFF_FLAG: break frame flag
|
||||
* - USART_TDBE_FLAG: transmit data buffer empty flag
|
||||
* - USART_TDC_FLAG: transmit data complete flag
|
||||
* - USART_RDBF_FLAG: receive data buffer full flag
|
||||
* - USART_IDLEF_FLAG: idle flag
|
||||
* - USART_ROERR_FLAG: receiver overflow error flag
|
||||
* - USART_NERR_FLAG: noise error flag
|
||||
* - USART_FERR_FLAG: framing error flag
|
||||
* - USART_PERR_FLAG: parity error flag
|
||||
* @retval the new state of usart_flag (SET or RESET).
|
||||
*/
|
||||
flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag)
|
||||
{
|
||||
flag_status int_status = RESET;
|
||||
|
||||
switch(flag)
|
||||
{
|
||||
case USART_CTSCF_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl3_bit.ctscfien;
|
||||
break;
|
||||
case USART_BFF_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl2_bit.bfien;
|
||||
break;
|
||||
case USART_TDBE_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl1_bit.tdbeien;
|
||||
break;
|
||||
case USART_TDC_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl1_bit.tdcien;
|
||||
break;
|
||||
case USART_RDBF_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl1_bit.rdbfien;
|
||||
break;
|
||||
case USART_ROERR_FLAG:
|
||||
int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien);
|
||||
break;
|
||||
case USART_IDLEF_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl1_bit.idleien;
|
||||
break;
|
||||
case USART_NERR_FLAG:
|
||||
case USART_FERR_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl3_bit.errien;
|
||||
break;
|
||||
case USART_PERR_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl1_bit.perrien;
|
||||
break;
|
||||
default:
|
||||
int_status = RESET;
|
||||
break;
|
||||
}
|
||||
|
||||
if(int_status != SET)
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
|
||||
if(usart_x->sts & flag)
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear the usart's pending flags.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, UART4 or UART5.
|
||||
* @param flag: specifies the flag to clear.
|
||||
* this parameter can be any combination of the following values:
|
||||
* - USART_CTSCF_FLAG: (not available for UART4 and UART5).
|
||||
* - USART_BFF_FLAG:
|
||||
* - USART_TDC_FLAG:
|
||||
* - USART_RDBF_FLAG:
|
||||
* - USART_PERR_FLAG:
|
||||
* - USART_FERR_FLAG:
|
||||
* - USART_NERR_FLAG:
|
||||
* - USART_ROERR_FLAG:
|
||||
* - USART_IDLEF_FLAG:
|
||||
* @note
|
||||
* - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software
|
||||
* sequence: a read operation to usart sts register (usart_flag_get())
|
||||
* followed by a read operation to usart dt register (usart_data_receive()).
|
||||
* - USART_RDBF_FLAG can be also cleared by a read to the usart dt register(usart_data_receive()).
|
||||
* - USART_TDC_FLAG can be also cleared by software sequence: a read operation to usart sts register (usart_flag_get())
|
||||
* followed by a write operation to usart dt register (usart_data_transmit()).
|
||||
* - USART_TDBE_FLAG is cleared only by a write to the usart dt register(usart_data_transmit()).
|
||||
* @retval none
|
||||
*/
|
||||
void usart_flag_clear(usart_type* usart_x, uint32_t flag)
|
||||
{
|
||||
if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG))
|
||||
{
|
||||
UNUSED(usart_x->sts);
|
||||
UNUSED(usart_x->dt);
|
||||
}
|
||||
else
|
||||
{
|
||||
usart_x->sts = ~flag;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
150
project/inc/at32f413_conf.h
Normal file
150
project/inc/at32f413_conf.h
Normal file
@@ -0,0 +1,150 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_conf.h
|
||||
* @brief at32f413 config header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F413_CONF_H
|
||||
#define __AT32F413_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief in the following line adjust the value of high speed exernal crystal (hext)
|
||||
* used in your application
|
||||
*
|
||||
* tip: to avoid modifying this file each time you need to use different hext, you
|
||||
* can define the hext value in your toolchain compiler preprocessor.
|
||||
*
|
||||
*/
|
||||
#if !defined HEXT_VALUE
|
||||
#define HEXT_VALUE ((uint32_t)16000000) /*!< value of the high speed exernal crystal in hz */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief in the following line adjust the high speed exernal crystal (hext) startup
|
||||
* timeout value
|
||||
*/
|
||||
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
|
||||
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
|
||||
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
|
||||
|
||||
/* module define -------------------------------------------------------------*/
|
||||
/*#define ACC_MODULE_ENABLED----------------------*/
|
||||
/*#define ADC_MODULE_ENABLED----------------------*/
|
||||
/*#define BPR_MODULE_ENABLED----------------------*/
|
||||
#define CAN_MODULE_ENABLED
|
||||
/*#define CRC_MODULE_ENABLED----------------------*/
|
||||
#define CRM_MODULE_ENABLED
|
||||
#define DEBUG_MODULE_ENABLED
|
||||
/*#define DMA_MODULE_ENABLED----------------------*/
|
||||
#define EXINT_MODULE_ENABLED
|
||||
#define FLASH_MODULE_ENABLED
|
||||
#define GPIO_MODULE_ENABLED
|
||||
/*#define I2C_MODULE_ENABLED----------------------*/
|
||||
#define MISC_MODULE_ENABLED
|
||||
#define PWC_MODULE_ENABLED
|
||||
/*#define RTC_MODULE_ENABLED----------------------*/
|
||||
/*#define SDIO_MODULE_ENABLED---------------------*/
|
||||
/*#define SPI_MODULE_ENABLED----------------------*/
|
||||
#define TMR_MODULE_ENABLED
|
||||
#define USART_MODULE_ENABLED
|
||||
/*#define USB_MODULE_ENABLED----------------------*/
|
||||
/*#define WDT_MODULE_ENABLED----------------------*/
|
||||
/*#define WWDT_MODULE_ENABLED---------------------*/
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#ifdef ACC_MODULE_ENABLED
|
||||
#include "at32f413_acc.h"
|
||||
#endif
|
||||
#ifdef ADC_MODULE_ENABLED
|
||||
#include "at32f413_adc.h"
|
||||
#endif
|
||||
#ifdef BPR_MODULE_ENABLED
|
||||
#include "at32f413_bpr.h"
|
||||
#endif
|
||||
#ifdef CAN_MODULE_ENABLED
|
||||
#include "at32f413_can.h"
|
||||
#endif
|
||||
#ifdef CRC_MODULE_ENABLED
|
||||
#include "at32f413_crc.h"
|
||||
#endif
|
||||
#ifdef CRM_MODULE_ENABLED
|
||||
#include "at32f413_crm.h"
|
||||
#endif
|
||||
#ifdef DEBUG_MODULE_ENABLED
|
||||
#include "at32f413_debug.h"
|
||||
#endif
|
||||
#ifdef DMA_MODULE_ENABLED
|
||||
#include "at32f413_dma.h"
|
||||
#endif
|
||||
#ifdef EXINT_MODULE_ENABLED
|
||||
#include "at32f413_exint.h"
|
||||
#endif
|
||||
#ifdef FLASH_MODULE_ENABLED
|
||||
#include "at32f413_flash.h"
|
||||
#endif
|
||||
#ifdef GPIO_MODULE_ENABLED
|
||||
#include "at32f413_gpio.h"
|
||||
#endif
|
||||
#ifdef I2C_MODULE_ENABLED
|
||||
#include "at32f413_i2c.h"
|
||||
#endif
|
||||
#ifdef MISC_MODULE_ENABLED
|
||||
#include "at32f413_misc.h"
|
||||
#endif
|
||||
#ifdef PWC_MODULE_ENABLED
|
||||
#include "at32f413_pwc.h"
|
||||
#endif
|
||||
#ifdef RTC_MODULE_ENABLED
|
||||
#include "at32f413_rtc.h"
|
||||
#include "rtc.h"
|
||||
#endif
|
||||
#ifdef SDIO_MODULE_ENABLED
|
||||
#include "at32f413_sdio.h"
|
||||
#endif
|
||||
#ifdef SPI_MODULE_ENABLED
|
||||
#include "at32f413_spi.h"
|
||||
#endif
|
||||
#ifdef TMR_MODULE_ENABLED
|
||||
#include "at32f413_tmr.h"
|
||||
#endif
|
||||
#ifdef USART_MODULE_ENABLED
|
||||
#include "at32f413_usart.h"
|
||||
#endif
|
||||
#ifdef USB_MODULE_ENABLED
|
||||
#include "at32f413_usb.h"
|
||||
#endif
|
||||
#ifdef WDT_MODULE_ENABLED
|
||||
#include "at32f413_wdt.h"
|
||||
#endif
|
||||
#ifdef WWDT_MODULE_ENABLED
|
||||
#include "at32f413_wwdt.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
77
project/inc/at32f413_int.h
Normal file
77
project/inc/at32f413_int.h
Normal file
@@ -0,0 +1,77 @@
|
||||
/* add user code begin Header */
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_int.h
|
||||
* @brief header file of main interrupt service routines.
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
/* add user code end Header */
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F413_INT_H
|
||||
#define __AT32F413_INT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f413.h"
|
||||
|
||||
/* private includes ----------------------------------------------------------*/
|
||||
/* add user code begin private includes */
|
||||
|
||||
/* add user code end private includes */
|
||||
|
||||
/* exported types ------------------------------------------------------------*/
|
||||
/* add user code begin exported types */
|
||||
|
||||
/* add user code end exported types */
|
||||
|
||||
/* exported constants --------------------------------------------------------*/
|
||||
/* add user code begin exported constants */
|
||||
|
||||
/* add user code end exported constants */
|
||||
|
||||
/* exported macro ------------------------------------------------------------*/
|
||||
/* add user code begin exported macro */
|
||||
|
||||
/* add user code end exported macro */
|
||||
|
||||
/* exported functions ------------------------------------------------------- */
|
||||
void NMI_Handler(void);
|
||||
void HardFault_Handler(void);
|
||||
void MemManage_Handler(void);
|
||||
void BusFault_Handler(void);
|
||||
void UsageFault_Handler(void);
|
||||
void SVC_Handler(void);
|
||||
void DebugMon_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
|
||||
void TMR4_GLOBAL_IRQHandler(void);
|
||||
/* add user code begin exported functions */
|
||||
|
||||
/* add user code end exported functions */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
103
project/inc/at32f413_wk_config.h
Normal file
103
project/inc/at32f413_wk_config.h
Normal file
@@ -0,0 +1,103 @@
|
||||
/* add user code begin Header */
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_wk_config.h
|
||||
* @brief header file of work bench config
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
/* add user code end Header */
|
||||
|
||||
/* define to prevent recursive inclusion -----------------------------------*/
|
||||
#ifndef __AT32F413_WK_CONFIG_H
|
||||
#define __AT32F413_WK_CONFIG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* includes -----------------------------------------------------------------------*/
|
||||
#include "at32f413.h"
|
||||
|
||||
/* private includes -------------------------------------------------------------*/
|
||||
/* add user code begin private includes */
|
||||
|
||||
/* add user code end private includes */
|
||||
|
||||
/* exported types -------------------------------------------------------------*/
|
||||
/* add user code begin exported types */
|
||||
|
||||
/* add user code end exported types */
|
||||
|
||||
/* exported constants --------------------------------------------------------*/
|
||||
/* add user code begin exported constants */
|
||||
|
||||
/* add user code end exported constants */
|
||||
|
||||
/* exported macro ------------------------------------------------------------*/
|
||||
/* add user code begin exported macro */
|
||||
|
||||
/* add user code end exported macro */
|
||||
|
||||
/* exported functions ------------------------------------------------------- */
|
||||
/* system clock config. */
|
||||
void wk_system_clock_config(void);
|
||||
|
||||
/* config periph clock. */
|
||||
void wk_periph_clock_config(void);
|
||||
|
||||
/* init debug function. */
|
||||
void wk_debug_config(void);
|
||||
|
||||
/* nvic config. */
|
||||
void wk_nvic_config(void);
|
||||
|
||||
/* init gpio function. */
|
||||
void wk_gpio_config(void);
|
||||
|
||||
/* init can1 function. */
|
||||
void wk_can1_init(void);
|
||||
|
||||
/* init pwc function. */
|
||||
void wk_pwc_init(void);
|
||||
|
||||
/* init usart2 function. */
|
||||
void wk_usart2_init(void);
|
||||
|
||||
/* init tmr1 function. */
|
||||
void wk_tmr1_init(void);
|
||||
|
||||
/* init tmr2 function. */
|
||||
void wk_tmr2_init(void);
|
||||
|
||||
/* init tmr3 function. */
|
||||
void wk_tmr3_init(void);
|
||||
|
||||
/* init tmr4 function. */
|
||||
void wk_tmr4_init(void);
|
||||
|
||||
/* add user code begin exported functions */
|
||||
|
||||
/* add user code end exported functions */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
224
project/src/at32f413_int.c
Normal file
224
project/src/at32f413_int.c
Normal file
@@ -0,0 +1,224 @@
|
||||
/* add user code begin Header */
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_int.c
|
||||
* @brief main interrupt service routines.
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
/* add user code end Header */
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f413_int.h"
|
||||
|
||||
/* private includes ----------------------------------------------------------*/
|
||||
/* add user code begin private includes */
|
||||
|
||||
/* add user code end private includes */
|
||||
|
||||
/* private typedef -----------------------------------------------------------*/
|
||||
/* add user code begin private typedef */
|
||||
|
||||
/* add user code end private typedef */
|
||||
|
||||
/* private define ------------------------------------------------------------*/
|
||||
/* add user code begin private define */
|
||||
|
||||
/* add user code end private define */
|
||||
|
||||
/* private macro -------------------------------------------------------------*/
|
||||
/* add user code begin private macro */
|
||||
|
||||
/* add user code end private macro */
|
||||
|
||||
/* private variables ---------------------------------------------------------*/
|
||||
/* add user code begin private variables */
|
||||
|
||||
/* add user code end private variables */
|
||||
|
||||
/* private function prototypes --------------------------------------------*/
|
||||
/* add user code begin function prototypes */
|
||||
|
||||
/* add user code end function prototypes */
|
||||
|
||||
/* private user code ---------------------------------------------------------*/
|
||||
/* add user code begin 0 */
|
||||
|
||||
/* add user code end 0 */
|
||||
|
||||
/* external variables ---------------------------------------------------------*/
|
||||
/* add user code begin external variables */
|
||||
|
||||
/* add user code end external variables */
|
||||
|
||||
/**
|
||||
* @brief this function handles nmi exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
/* add user code begin NonMaskableInt_IRQ 0 */
|
||||
|
||||
/* add user code end NonMaskableInt_IRQ 0 */
|
||||
|
||||
/* add user code begin NonMaskableInt_IRQ 1 */
|
||||
|
||||
/* add user code end NonMaskableInt_IRQ 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles hard fault exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
/* add user code begin HardFault_IRQ 0 */
|
||||
|
||||
/* add user code end HardFault_IRQ 0 */
|
||||
/* go to infinite loop when hard fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
/* add user code begin W1_HardFault_IRQ 0 */
|
||||
|
||||
/* add user code end W1_HardFault_IRQ 0 */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles memory manage exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void MemManage_Handler(void)
|
||||
{
|
||||
/* add user code begin MemoryManagement_IRQ 0 */
|
||||
|
||||
/* add user code end MemoryManagement_IRQ 0 */
|
||||
/* go to infinite loop when memory manage exception occurs */
|
||||
while (1)
|
||||
{
|
||||
/* add user code begin W1_MemoryManagement_IRQ 0 */
|
||||
|
||||
/* add user code end W1_MemoryManagement_IRQ 0 */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles bus fault exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void BusFault_Handler(void)
|
||||
{
|
||||
/* add user code begin BusFault_IRQ 0 */
|
||||
|
||||
/* add user code end BusFault_IRQ 0 */
|
||||
/* go to infinite loop when bus fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
/* add user code begin W1_BusFault_IRQ 0 */
|
||||
|
||||
/* add user code end W1_BusFault_IRQ 0 */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles usage fault exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void UsageFault_Handler(void)
|
||||
{
|
||||
/* add user code begin UsageFault_IRQ 0 */
|
||||
|
||||
/* add user code end UsageFault_IRQ 0 */
|
||||
/* go to infinite loop when usage fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
/* add user code begin W1_UsageFault_IRQ 0 */
|
||||
|
||||
/* add user code end W1_UsageFault_IRQ 0 */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles svcall exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void SVC_Handler(void)
|
||||
{
|
||||
/* add user code begin SVCall_IRQ 0 */
|
||||
|
||||
/* add user code end SVCall_IRQ 0 */
|
||||
/* add user code begin SVCall_IRQ 1 */
|
||||
|
||||
/* add user code end SVCall_IRQ 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles debug monitor exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void DebugMon_Handler(void)
|
||||
{
|
||||
/* add user code begin DebugMonitor_IRQ 0 */
|
||||
|
||||
/* add user code end DebugMonitor_IRQ 0 */
|
||||
/* add user code begin DebugMonitor_IRQ 1 */
|
||||
|
||||
/* add user code end DebugMonitor_IRQ 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles pendsv_handler exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void PendSV_Handler(void)
|
||||
{
|
||||
/* add user code begin PendSV_IRQ 0 */
|
||||
|
||||
/* add user code end PendSV_IRQ 0 */
|
||||
/* add user code begin PendSV_IRQ 1 */
|
||||
|
||||
/* add user code end PendSV_IRQ 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles TMR4 handler.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void TMR4_GLOBAL_IRQHandler(void)
|
||||
{
|
||||
/* add user code begin TMR4_GLOBAL_IRQ 0 */
|
||||
|
||||
/* add user code end TMR4_GLOBAL_IRQ 0 */
|
||||
/* add user code begin TMR4_GLOBAL_IRQ 1 */
|
||||
|
||||
/* add user code end TMR4_GLOBAL_IRQ 1 */
|
||||
}
|
||||
|
||||
/* add user code begin 1 */
|
||||
|
||||
/* add user code end 1 */
|
||||
693
project/src/at32f413_wk_config.c
Normal file
693
project/src/at32f413_wk_config.c
Normal file
@@ -0,0 +1,693 @@
|
||||
/* add user code begin Header */
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f413_wk_config.c
|
||||
* @brief work bench config program
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
/* add user code end Header */
|
||||
|
||||
#include "at32f413_wk_config.h"
|
||||
|
||||
/* private includes ----------------------------------------------------------*/
|
||||
/* add user code begin private includes */
|
||||
|
||||
/* add user code end private includes */
|
||||
|
||||
/* private typedef -----------------------------------------------------------*/
|
||||
/* add user code begin private typedef */
|
||||
|
||||
/* add user code end private typedef */
|
||||
|
||||
/* private define ------------------------------------------------------------*/
|
||||
/* add user code begin private define */
|
||||
|
||||
/* add user code end private define */
|
||||
|
||||
/* private macro -------------------------------------------------------------*/
|
||||
/* add user code begin private macro */
|
||||
|
||||
/* add user code end private macro */
|
||||
|
||||
/* private variables ---------------------------------------------------------*/
|
||||
/* add user code begin private variables */
|
||||
|
||||
/* add user code end private variables */
|
||||
|
||||
/* private function prototypes --------------------------------------------*/
|
||||
/* add user code begin function prototypes */
|
||||
|
||||
/* add user code end function prototypes */
|
||||
|
||||
/* private user code ---------------------------------------------------------*/
|
||||
/* add user code begin 0 */
|
||||
|
||||
/* add user code end 0 */
|
||||
|
||||
/**
|
||||
* @brief system clock config program
|
||||
* @note the system clock is configured as follow:
|
||||
* system clock (sclk) = hext / 2 * pll_mult
|
||||
* system clock source = pll (hext)
|
||||
* - hext = HEXT_VALUE
|
||||
* - sclk = 200000000
|
||||
* - ahbdiv = 1
|
||||
* - ahbclk = 200000000
|
||||
* - apb1div = 2
|
||||
* - apb1clk = 100000000
|
||||
* - apb2div = 2
|
||||
* - apb2clk = 100000000
|
||||
* - pll_mult = 25
|
||||
* - pll_range = GT72MHZ (greater than 72 mhz)
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void wk_system_clock_config(void)
|
||||
{
|
||||
/* reset crm */
|
||||
crm_reset();
|
||||
|
||||
/* enable lick */
|
||||
crm_clock_source_enable(CRM_CLOCK_SOURCE_LICK, TRUE);
|
||||
|
||||
/* wait till lick is ready */
|
||||
while(crm_flag_get(CRM_LICK_STABLE_FLAG) != SET)
|
||||
{
|
||||
}
|
||||
|
||||
/* enable hext */
|
||||
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
|
||||
|
||||
/* wait till hext is ready */
|
||||
while(crm_hext_stable_wait() == ERROR)
|
||||
{
|
||||
}
|
||||
|
||||
/* enable hick */
|
||||
crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE);
|
||||
|
||||
/* wait till hick is ready */
|
||||
while(crm_flag_get(CRM_HICK_STABLE_FLAG) != SET)
|
||||
{
|
||||
}
|
||||
|
||||
/* config pll clock resource */
|
||||
crm_pll_config(CRM_PLL_SOURCE_HEXT_DIV, CRM_PLL_MULT_25, CRM_PLL_OUTPUT_RANGE_GT72MHZ);
|
||||
|
||||
/* enable pll */
|
||||
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
|
||||
|
||||
/* wait till pll is ready */
|
||||
while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
|
||||
{
|
||||
}
|
||||
|
||||
/* config ahbclk */
|
||||
crm_ahb_div_set(CRM_AHB_DIV_1);
|
||||
|
||||
/* config apb2clk, the maximum frequency of APB2 clock is 100 MHz */
|
||||
crm_apb2_div_set(CRM_APB2_DIV_2);
|
||||
|
||||
/* config apb1clk, the maximum frequency of APB1 clock is 100 MHz */
|
||||
crm_apb1_div_set(CRM_APB1_DIV_2);
|
||||
|
||||
/* enable auto step mode */
|
||||
crm_auto_step_mode_enable(TRUE);
|
||||
|
||||
/* select pll as system clock source */
|
||||
crm_sysclk_switch(CRM_SCLK_PLL);
|
||||
|
||||
/* wait till pll is used as system clock source */
|
||||
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
|
||||
{
|
||||
}
|
||||
|
||||
/* disable auto step mode */
|
||||
crm_auto_step_mode_enable(FALSE);
|
||||
|
||||
/* update system_core_clock global variable */
|
||||
system_core_clock_update();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief config periph clock
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void wk_periph_clock_config(void)
|
||||
{
|
||||
/* enable iomux periph clock */
|
||||
crm_periph_clock_enable(CRM_IOMUX_PERIPH_CLOCK, TRUE);
|
||||
|
||||
/* enable gpioa periph clock */
|
||||
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
|
||||
|
||||
/* enable gpiob periph clock */
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
/* enable gpiod periph clock */
|
||||
crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE);
|
||||
|
||||
/* enable tmr1 periph clock */
|
||||
crm_periph_clock_enable(CRM_TMR1_PERIPH_CLOCK, TRUE);
|
||||
|
||||
/* enable tmr2 periph clock */
|
||||
crm_periph_clock_enable(CRM_TMR2_PERIPH_CLOCK, TRUE);
|
||||
|
||||
/* enable tmr3 periph clock */
|
||||
crm_periph_clock_enable(CRM_TMR3_PERIPH_CLOCK, TRUE);
|
||||
|
||||
/* enable tmr4 periph clock */
|
||||
crm_periph_clock_enable(CRM_TMR4_PERIPH_CLOCK, TRUE);
|
||||
|
||||
/* enable usart2 periph clock */
|
||||
crm_periph_clock_enable(CRM_USART2_PERIPH_CLOCK, TRUE);
|
||||
|
||||
/* enable can1 periph clock */
|
||||
crm_periph_clock_enable(CRM_CAN1_PERIPH_CLOCK, TRUE);
|
||||
|
||||
/* enable pwc periph clock */
|
||||
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief init debug function.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void wk_debug_config(void)
|
||||
{
|
||||
/* jtag-dp disabled and sw-dp enabled */
|
||||
gpio_pin_remap_config(SWJTAG_GMUX_010, TRUE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief nvic config
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void wk_nvic_config(void)
|
||||
{
|
||||
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
|
||||
|
||||
nvic_irq_enable(TMR4_GLOBAL_IRQn, 0, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief init gpio_input/gpio_output/gpio_analog/eventout function.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void wk_gpio_config(void)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
|
||||
/* gpio input config */
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_3 | GPIO_PINS_4 | GPIO_PINS_5 | GPIO_PINS_6;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
/* gpio output config */
|
||||
gpio_bits_reset(GPIOB, GPIO_PINS_15);
|
||||
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_15;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief init pwc function.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void wk_pwc_init(void)
|
||||
{
|
||||
/* add user code begin pwc_init 0 */
|
||||
|
||||
/* add user code end pwc_init 0 */
|
||||
|
||||
exint_init_type exint_init_struct;
|
||||
|
||||
/* add user code begin pwc_init 1 */
|
||||
|
||||
/* add user code end pwc_init 1 */
|
||||
|
||||
/* set the threshold voltage*/
|
||||
pwc_pvm_level_select(PWC_PVM_VOLTAGE_2V8);
|
||||
/* enable power voltage monitor */
|
||||
pwc_power_voltage_monitor_enable(TRUE);
|
||||
|
||||
exint_default_para_init(&exint_init_struct);
|
||||
exint_init_struct.line_enable = TRUE;
|
||||
exint_init_struct.line_mode = EXINT_LINE_INTERRUPUT;
|
||||
exint_init_struct.line_select = EXINT_LINE_16;
|
||||
exint_init_struct.line_polarity = EXINT_TRIGGER_RISING_EDGE;
|
||||
exint_init(&exint_init_struct);
|
||||
|
||||
/**
|
||||
* Users need to configure PWC interrupt functions according to the actual application.
|
||||
* 1. Add the user's interrupt handler code into the below function in the at32f413_int.c file.
|
||||
* --void PVM_IRQHandler (void)
|
||||
*/
|
||||
|
||||
/* add user code begin pwc_init 2 */
|
||||
|
||||
/* add user code end pwc_init 2 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief init usart2 function
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void wk_usart2_init(void)
|
||||
{
|
||||
/* add user code begin usart2_init 0 */
|
||||
|
||||
/* add user code end usart2_init 0 */
|
||||
|
||||
gpio_init_type gpio_init_struct;
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
|
||||
/* add user code begin usart2_init 1 */
|
||||
|
||||
/* add user code end usart2_init 1 */
|
||||
|
||||
/* configure the TX pin */
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_2;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
|
||||
/* configure the RX pin */
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_3;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
|
||||
/* configure param */
|
||||
usart_init(USART2, 115200, USART_DATA_8BITS, USART_STOP_1_BIT);
|
||||
usart_receiver_enable(USART2, TRUE);
|
||||
usart_parity_selection_config(USART2, USART_PARITY_NONE);
|
||||
|
||||
usart_hardware_flow_control_set(USART2, USART_HARDWARE_FLOW_NONE);
|
||||
|
||||
usart_enable(USART2, TRUE);
|
||||
|
||||
/* add user code begin usart2_init 2 */
|
||||
|
||||
/* add user code end usart2_init 2 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief init tmr1 function.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void wk_tmr1_init(void)
|
||||
{
|
||||
/* add user code begin tmr1_init 0 */
|
||||
|
||||
/* add user code end tmr1_init 0 */
|
||||
|
||||
gpio_init_type gpio_init_struct;
|
||||
tmr_output_config_type tmr_output_struct;
|
||||
tmr_brkdt_config_type tmr_brkdt_struct;
|
||||
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
|
||||
/* add user code begin tmr1_init 1 */
|
||||
|
||||
/* add user code end tmr1_init 1 */
|
||||
|
||||
/* configure the CH1C pin */
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_13;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
/* configure the CH2C pin */
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_14;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
/* configure the CH1 pin */
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_8;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
|
||||
/* configure the CH2 pin */
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_9;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
|
||||
/* configure counter settings */
|
||||
tmr_base_init(TMR1, 65535, 0);
|
||||
tmr_cnt_dir_set(TMR1, TMR_COUNT_UP);
|
||||
tmr_clock_source_div_set(TMR1, TMR_CLOCK_DIV1);
|
||||
tmr_repetition_counter_set(TMR1, 0);
|
||||
tmr_period_buffer_enable(TMR1, FALSE);
|
||||
|
||||
/* configure primary mode settings */
|
||||
tmr_sub_sync_mode_set(TMR1, FALSE);
|
||||
tmr_primary_mode_select(TMR1, TMR_PRIMARY_SEL_RESET);
|
||||
|
||||
/* configure channel 1 output settings */
|
||||
tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_OFF;
|
||||
tmr_output_struct.oc_output_state = TRUE;
|
||||
tmr_output_struct.occ_output_state = TRUE;
|
||||
tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
|
||||
tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
|
||||
tmr_output_struct.oc_idle_state = FALSE;
|
||||
tmr_output_struct.occ_idle_state = FALSE;
|
||||
tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_1, &tmr_output_struct);
|
||||
tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_1, 0);
|
||||
tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_1, FALSE);
|
||||
|
||||
/* configure channel 2 output settings */
|
||||
tmr_output_struct.oc_mode = TMR_OUTPUT_CONTROL_OFF;
|
||||
tmr_output_struct.oc_output_state = TRUE;
|
||||
tmr_output_struct.occ_output_state = TRUE;
|
||||
tmr_output_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
|
||||
tmr_output_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
|
||||
tmr_output_struct.oc_idle_state = FALSE;
|
||||
tmr_output_struct.occ_idle_state = FALSE;
|
||||
tmr_output_channel_config(TMR1, TMR_SELECT_CHANNEL_2, &tmr_output_struct);
|
||||
tmr_channel_value_set(TMR1, TMR_SELECT_CHANNEL_2, 0);
|
||||
tmr_output_channel_buffer_enable(TMR1, TMR_SELECT_CHANNEL_2, FALSE);
|
||||
|
||||
/* configure break and dead-time settings */
|
||||
tmr_brkdt_struct.brk_enable = FALSE;
|
||||
tmr_brkdt_struct.auto_output_enable = FALSE;
|
||||
tmr_brkdt_struct.brk_polarity = TMR_BRK_INPUT_ACTIVE_LOW;
|
||||
tmr_brkdt_struct.fcsoen_state = FALSE;
|
||||
tmr_brkdt_struct.fcsodis_state = FALSE;
|
||||
tmr_brkdt_struct.wp_level = TMR_WP_OFF;
|
||||
tmr_brkdt_struct.deadtime = 0;
|
||||
tmr_brkdt_config(TMR1, &tmr_brkdt_struct);
|
||||
|
||||
|
||||
tmr_output_enable(TMR1, TRUE);
|
||||
|
||||
tmr_counter_enable(TMR1, TRUE);
|
||||
|
||||
/* add user code begin tmr1_init 2 */
|
||||
|
||||
/* add user code end tmr1_init 2 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief init tmr2 function.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void wk_tmr2_init(void)
|
||||
{
|
||||
/* add user code begin tmr2_init 0 */
|
||||
|
||||
/* add user code end tmr2_init 0 */
|
||||
|
||||
gpio_init_type gpio_init_struct;
|
||||
tmr_input_config_type tmr_input_struct;
|
||||
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
|
||||
/* add user code begin tmr2_init 1 */
|
||||
|
||||
/* add user code end tmr2_init 1 */
|
||||
|
||||
/* configure the CH1 pin */
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_0;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
|
||||
/* configure the CH2 pin */
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_1;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
|
||||
/* configure counter settings */
|
||||
tmr_base_init(TMR2, 65535, 0);
|
||||
tmr_cnt_dir_set(TMR2, TMR_COUNT_UP);
|
||||
tmr_clock_source_div_set(TMR2, TMR_CLOCK_DIV1);
|
||||
tmr_period_buffer_enable(TMR2, FALSE);
|
||||
|
||||
/* configure primary mode settings */
|
||||
tmr_sub_sync_mode_set(TMR2, FALSE);
|
||||
tmr_primary_mode_select(TMR2, TMR_PRIMARY_SEL_RESET);
|
||||
|
||||
/* configure encoder mode */
|
||||
tmr_input_struct.input_channel_select = TMR_SELECT_CHANNEL_1;
|
||||
tmr_input_struct.input_mapped_select = TMR_CC_CHANNEL_MAPPED_DIRECT;
|
||||
tmr_input_struct.input_polarity_select = TMR_INPUT_RISING_EDGE;
|
||||
tmr_input_struct.input_filter_value = 0;
|
||||
tmr_input_channel_init(TMR2, &tmr_input_struct, TMR_CHANNEL_INPUT_DIV_1);
|
||||
|
||||
tmr_input_struct.input_channel_select = TMR_SELECT_CHANNEL_2;
|
||||
tmr_input_struct.input_mapped_select = TMR_CC_CHANNEL_MAPPED_DIRECT;
|
||||
tmr_input_struct.input_polarity_select = TMR_INPUT_RISING_EDGE;
|
||||
tmr_input_struct.input_filter_value = 0;
|
||||
tmr_input_channel_init(TMR2, &tmr_input_struct, TMR_CHANNEL_INPUT_DIV_1);
|
||||
|
||||
tmr_encoder_mode_config(TMR2, TMR_ENCODER_MODE_A, TMR_INPUT_RISING_EDGE, TMR_INPUT_RISING_EDGE);
|
||||
|
||||
tmr_counter_enable(TMR2, TRUE);
|
||||
|
||||
/* add user code begin tmr2_init 2 */
|
||||
|
||||
/* add user code end tmr2_init 2 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief init tmr3 function.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void wk_tmr3_init(void)
|
||||
{
|
||||
/* add user code begin tmr3_init 0 */
|
||||
|
||||
/* add user code end tmr3_init 0 */
|
||||
|
||||
gpio_init_type gpio_init_struct;
|
||||
tmr_input_config_type tmr_input_struct;
|
||||
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
|
||||
/* add user code begin tmr3_init 1 */
|
||||
|
||||
/* add user code end tmr3_init 1 */
|
||||
|
||||
/* configure the CH1 pin */
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_6;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
|
||||
/* configure the CH2 pin */
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_7;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
|
||||
/* configure counter settings */
|
||||
tmr_base_init(TMR3, 65535, 0);
|
||||
tmr_cnt_dir_set(TMR3, TMR_COUNT_UP);
|
||||
tmr_clock_source_div_set(TMR3, TMR_CLOCK_DIV1);
|
||||
tmr_period_buffer_enable(TMR3, FALSE);
|
||||
|
||||
/* configure primary mode settings */
|
||||
tmr_sub_sync_mode_set(TMR3, FALSE);
|
||||
tmr_primary_mode_select(TMR3, TMR_PRIMARY_SEL_RESET);
|
||||
|
||||
/* configure encoder mode */
|
||||
tmr_input_struct.input_channel_select = TMR_SELECT_CHANNEL_1;
|
||||
tmr_input_struct.input_mapped_select = TMR_CC_CHANNEL_MAPPED_DIRECT;
|
||||
tmr_input_struct.input_polarity_select = TMR_INPUT_RISING_EDGE;
|
||||
tmr_input_struct.input_filter_value = 0;
|
||||
tmr_input_channel_init(TMR3, &tmr_input_struct, TMR_CHANNEL_INPUT_DIV_1);
|
||||
|
||||
tmr_input_struct.input_channel_select = TMR_SELECT_CHANNEL_2;
|
||||
tmr_input_struct.input_mapped_select = TMR_CC_CHANNEL_MAPPED_DIRECT;
|
||||
tmr_input_struct.input_polarity_select = TMR_INPUT_RISING_EDGE;
|
||||
tmr_input_struct.input_filter_value = 0;
|
||||
tmr_input_channel_init(TMR3, &tmr_input_struct, TMR_CHANNEL_INPUT_DIV_1);
|
||||
|
||||
tmr_encoder_mode_config(TMR3, TMR_ENCODER_MODE_A, TMR_INPUT_RISING_EDGE, TMR_INPUT_RISING_EDGE);
|
||||
|
||||
tmr_counter_enable(TMR3, TRUE);
|
||||
|
||||
/* add user code begin tmr3_init 2 */
|
||||
|
||||
/* add user code end tmr3_init 2 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief init tmr4 function.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void wk_tmr4_init(void)
|
||||
{
|
||||
/* add user code begin tmr4_init 0 */
|
||||
|
||||
/* add user code end tmr4_init 0 */
|
||||
|
||||
|
||||
/* add user code begin tmr4_init 1 */
|
||||
|
||||
/* add user code end tmr4_init 1 */
|
||||
|
||||
/* configure counter settings */
|
||||
tmr_base_init(TMR4, 199, 999);
|
||||
tmr_cnt_dir_set(TMR4, TMR_COUNT_UP);
|
||||
tmr_clock_source_div_set(TMR4, TMR_CLOCK_DIV1);
|
||||
tmr_period_buffer_enable(TMR4, FALSE);
|
||||
|
||||
/* configure primary mode settings */
|
||||
tmr_sub_sync_mode_set(TMR4, FALSE);
|
||||
tmr_primary_mode_select(TMR4, TMR_PRIMARY_SEL_RESET);
|
||||
|
||||
tmr_counter_enable(TMR4, TRUE);
|
||||
|
||||
/**
|
||||
* Users need to configure TMR4 interrupt functions according to the actual application.
|
||||
* 1. Call the below function to enable the corresponding TMR4 interrupt.
|
||||
* --tmr_interrupt_enable(...)
|
||||
* 2. Add the user's interrupt handler code into the below function in the at32f413_int.c file.
|
||||
* --void TMR4_GLOBAL_IRQHandler(void)
|
||||
*/
|
||||
|
||||
/* add user code begin tmr4_init 2 */
|
||||
|
||||
/* add user code end tmr4_init 2 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief init can1 function.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void wk_can1_init(void)
|
||||
{
|
||||
/* add user code begin can1_init 0 */
|
||||
|
||||
/* add user code end can1_init 0 */
|
||||
|
||||
gpio_init_type gpio_init_struct;
|
||||
can_base_type can_base_struct;
|
||||
can_baudrate_type can_baudrate_struct;
|
||||
can_filter_init_type can_filter_init_struct;
|
||||
|
||||
/* add user code begin can1_init 1 */
|
||||
|
||||
/* add user code end can1_init 1 */
|
||||
|
||||
/*gpio-----------------------------------------------------------------------------*/
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
|
||||
/* configure the CAN1 TX pin */
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_12;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
|
||||
/* configure the CAN1 RX pin */
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_11;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
|
||||
/*can_base_init--------------------------------------------------------------------*/
|
||||
can_default_para_init(&can_base_struct);
|
||||
can_base_struct.mode_selection = CAN_MODE_COMMUNICATE;
|
||||
can_base_struct.ttc_enable = FALSE;
|
||||
can_base_struct.aebo_enable = TRUE;
|
||||
can_base_struct.aed_enable = TRUE;
|
||||
can_base_struct.prsf_enable = FALSE;
|
||||
can_base_struct.mdrsel_selection = CAN_DISCARDING_FIRST_RECEIVED;
|
||||
can_base_struct.mmssr_selection = CAN_SENDING_BY_ID;
|
||||
|
||||
can_base_init(CAN1, &can_base_struct);
|
||||
|
||||
/*can_baudrate_setting-------------------------------------------------------------*/
|
||||
/*set baudrate = pclk/(baudrate_div *(1 + bts1_size + bts2_size))------------------*/
|
||||
can_baudrate_struct.baudrate_div = 25; /*value: 1~0xFFF*/
|
||||
can_baudrate_struct.rsaw_size = CAN_RSAW_1TQ; /*value: 1~4*/
|
||||
can_baudrate_struct.bts1_size = CAN_BTS1_6TQ; /*value: 1~16*/
|
||||
can_baudrate_struct.bts2_size = CAN_BTS2_1TQ; /*value: 1~8*/
|
||||
can_baudrate_set(CAN1, &can_baudrate_struct);
|
||||
|
||||
/*can_filter_0_config--------------------------------------------------------------*/
|
||||
can_filter_init_struct.filter_activate_enable = TRUE;
|
||||
can_filter_init_struct.filter_number = 0;
|
||||
can_filter_init_struct.filter_fifo = CAN_FILTER_FIFO0;
|
||||
can_filter_init_struct.filter_bit = CAN_FILTER_16BIT;
|
||||
can_filter_init_struct.filter_mode = CAN_FILTER_MODE_ID_MASK;
|
||||
/*Standard identifier + Mask Mode + Data/Remote frame: id/mask 11bit --------------*/
|
||||
can_filter_init_struct.filter_id_high = 0x0 << 5;
|
||||
can_filter_init_struct.filter_id_low = 0x0 << 5;
|
||||
can_filter_init_struct.filter_mask_high = 0x0 << 5;
|
||||
can_filter_init_struct.filter_mask_low = 0x0 << 5;
|
||||
|
||||
can_filter_init(CAN1, &can_filter_init_struct);
|
||||
|
||||
/* add user code begin can1_init 2 */
|
||||
|
||||
/* add user code end can1_init 2 */
|
||||
}
|
||||
|
||||
/* add user code begin 1 */
|
||||
|
||||
/* add user code end 1 */
|
||||
125
project/src/main.c
Normal file
125
project/src/main.c
Normal file
@@ -0,0 +1,125 @@
|
||||
/* add user code begin Header */
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file main.c
|
||||
* @brief main program
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
/* add user code end Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f413_wk_config.h"
|
||||
|
||||
/* private includes ----------------------------------------------------------*/
|
||||
/* add user code begin private includes */
|
||||
#include "dwt_delay.h"
|
||||
/* add user code end private includes */
|
||||
|
||||
/* private typedef -----------------------------------------------------------*/
|
||||
/* add user code begin private typedef */
|
||||
|
||||
/* add user code end private typedef */
|
||||
|
||||
/* private define ------------------------------------------------------------*/
|
||||
/* add user code begin private define */
|
||||
|
||||
/* add user code end private define */
|
||||
|
||||
/* private macro -------------------------------------------------------------*/
|
||||
/* add user code begin private macro */
|
||||
|
||||
/* add user code end private macro */
|
||||
|
||||
/* private variables ---------------------------------------------------------*/
|
||||
/* add user code begin private variables */
|
||||
|
||||
/* add user code end private variables */
|
||||
|
||||
/* private function prototypes --------------------------------------------*/
|
||||
/* add user code begin function prototypes */
|
||||
|
||||
/* add user code end function prototypes */
|
||||
|
||||
/* private user code ---------------------------------------------------------*/
|
||||
/* add user code begin 0 */
|
||||
|
||||
/* add user code end 0 */
|
||||
|
||||
/**
|
||||
* @brief main function.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
/* add user code begin 1 */
|
||||
|
||||
/* add user code end 1 */
|
||||
|
||||
/* system clock config. */
|
||||
wk_system_clock_config();
|
||||
|
||||
/* config periph clock. */
|
||||
wk_periph_clock_config();
|
||||
|
||||
/* init debug function. */
|
||||
wk_debug_config();
|
||||
|
||||
/* init pwc function. */
|
||||
wk_pwc_init();
|
||||
|
||||
/* nvic config. */
|
||||
wk_nvic_config();
|
||||
|
||||
/* init usart2 function. */
|
||||
wk_usart2_init();
|
||||
|
||||
/* init tmr1 function. */
|
||||
wk_tmr1_init();
|
||||
|
||||
/* init tmr2 function. */
|
||||
wk_tmr2_init();
|
||||
|
||||
/* init tmr3 function. */
|
||||
wk_tmr3_init();
|
||||
|
||||
/* init tmr4 function. */
|
||||
wk_tmr4_init();
|
||||
|
||||
/* init can1 function. */
|
||||
wk_can1_init();
|
||||
|
||||
/* init gpio function. */
|
||||
wk_gpio_config();
|
||||
|
||||
/* add user code begin 2 */
|
||||
DWT_Init();
|
||||
/* add user code end 2 */
|
||||
|
||||
while(1)
|
||||
{
|
||||
/* add user code begin 3 */
|
||||
gpio_bits_reset(GPIOB, GPIO_PINS_15);
|
||||
DWT_Delay(500000);
|
||||
gpio_bits_set(GPIOB, GPIO_PINS_15);
|
||||
DWT_Delay(500000);
|
||||
/* add user code end 3 */
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user