[BC2D-POS] initial commit

This commit is contained in:
bmy
2024-05-10 10:54:06 +08:00
parent c9da340c46
commit 1c83cbc70a
12 changed files with 155 additions and 50 deletions

View File

@@ -55,6 +55,65 @@ extern "C" {
/* add user code end exported macro */
/* add user code begin dma define */
/* user can only modify the dma define value */
//#define DMA1_CHANNEL1_BUFFER_SIZE 0
//#define DMA1_CHANNEL1_MEMORY_BASE_ADDR 0
//#define DMA1_CHANNEL1_PERIPHERAL_BASE_ADDR 0
//#define DMA1_CHANNEL2_BUFFER_SIZE 0
//#define DMA1_CHANNEL2_MEMORY_BASE_ADDR 0
//#define DMA1_CHANNEL2_PERIPHERAL_BASE_ADDR 0
//#define DMA1_CHANNEL3_BUFFER_SIZE 0
//#define DMA1_CHANNEL3_MEMORY_BASE_ADDR 0
//#define DMA1_CHANNEL3_PERIPHERAL_BASE_ADDR 0
//#define DMA1_CHANNEL4_BUFFER_SIZE 0
//#define DMA1_CHANNEL4_MEMORY_BASE_ADDR 0
//#define DMA1_CHANNEL4_PERIPHERAL_BASE_ADDR 0
//#define DMA1_CHANNEL5_BUFFER_SIZE 0
//#define DMA1_CHANNEL5_MEMORY_BASE_ADDR 0
//#define DMA1_CHANNEL5_PERIPHERAL_BASE_ADDR 0
//#define DMA1_CHANNEL6_BUFFER_SIZE 0
//#define DMA1_CHANNEL6_MEMORY_BASE_ADDR 0
//#define DMA1_CHANNEL6_PERIPHERAL_BASE_ADDR 0
//#define DMA1_CHANNEL7_BUFFER_SIZE 0
//#define DMA1_CHANNEL7_MEMORY_BASE_ADDR 0
//#define DMA1_CHANNEL7_PERIPHERAL_BASE_ADDR 0
//#define DMA2_CHANNEL1_BUFFER_SIZE 0
//#define DMA2_CHANNEL1_MEMORY_BASE_ADDR 0
//#define DMA2_CHANNEL1_PERIPHERAL_BASE_ADDR 0
//#define DMA2_CHANNEL2_BUFFER_SIZE 0
//#define DMA2_CHANNEL2_MEMORY_BASE_ADDR 0
//#define DMA2_CHANNEL2_PERIPHERAL_BASE_ADDR 0
//#define DMA2_CHANNEL3_BUFFER_SIZE 0
//#define DMA2_CHANNEL3_MEMORY_BASE_ADDR 0
//#define DMA2_CHANNEL3_PERIPHERAL_BASE_ADDR 0
//#define DMA2_CHANNEL4_BUFFER_SIZE 0
//#define DMA2_CHANNEL4_MEMORY_BASE_ADDR 0
//#define DMA2_CHANNEL4_PERIPHERAL_BASE_ADDR 0
//#define DMA2_CHANNEL5_BUFFER_SIZE 0
//#define DMA2_CHANNEL5_MEMORY_BASE_ADDR 0
//#define DMA2_CHANNEL5_PERIPHERAL_BASE_ADDR 0
//#define DMA2_CHANNEL6_BUFFER_SIZE 0
//#define DMA2_CHANNEL6_MEMORY_BASE_ADDR 0
//#define DMA2_CHANNEL6_PERIPHERAL_BASE_ADDR 0
//#define DMA2_CHANNEL7_BUFFER_SIZE 0
//#define DMA2_CHANNEL7_MEMORY_BASE_ADDR 0
//#define DMA2_CHANNEL7_PERIPHERAL_BASE_ADDR 0
/* add user code end dma define */
/* exported functions ------------------------------------------------------- */
/* system clock config. */
void wk_system_clock_config(void);

View File

@@ -461,16 +461,16 @@ void wk_tmr2_init(void)
tmr_input_struct.input_channel_select = TMR_SELECT_CHANNEL_1;
tmr_input_struct.input_mapped_select = TMR_CC_CHANNEL_MAPPED_DIRECT;
tmr_input_struct.input_polarity_select = TMR_INPUT_RISING_EDGE;
tmr_input_struct.input_filter_value = 0;
tmr_input_struct.input_filter_value = 7;
tmr_input_channel_init(TMR2, &tmr_input_struct, TMR_CHANNEL_INPUT_DIV_1);
tmr_input_struct.input_channel_select = TMR_SELECT_CHANNEL_2;
tmr_input_struct.input_mapped_select = TMR_CC_CHANNEL_MAPPED_DIRECT;
tmr_input_struct.input_polarity_select = TMR_INPUT_RISING_EDGE;
tmr_input_struct.input_filter_value = 0;
tmr_input_struct.input_filter_value = 7;
tmr_input_channel_init(TMR2, &tmr_input_struct, TMR_CHANNEL_INPUT_DIV_1);
tmr_encoder_mode_config(TMR2, TMR_ENCODER_MODE_A, TMR_INPUT_RISING_EDGE, TMR_INPUT_RISING_EDGE);
tmr_encoder_mode_config(TMR2, TMR_ENCODER_MODE_B, TMR_INPUT_RISING_EDGE, TMR_INPUT_RISING_EDGE);
tmr_counter_enable(TMR2, TRUE);
@@ -564,7 +564,7 @@ void wk_tmr4_init(void)
/* add user code end tmr4_init 1 */
/* configure counter settings */
tmr_base_init(TMR4, 1999, 999);
tmr_base_init(TMR4, 1999, 1999);
tmr_cnt_dir_set(TMR4, TMR_COUNT_UP);
tmr_clock_source_div_set(TMR4, TMR_CLOCK_DIV1);
tmr_period_buffer_enable(TMR4, FALSE);

View File

@@ -68,10 +68,10 @@
/* add user code end 0 */
/**
* @brief main function.
* @param none
* @retval none
*/
* @brief main function.
* @param none
* @retval none
*/
int main(void)
{
/* add user code begin 1 */
@@ -124,8 +124,12 @@ int main(void)
LOGI("init done");
/* add user code end 2 */
while (1) {
while(1)
{
/* add user code begin 3 */
// lwprintf("pwm value: %f\r\n", param_m1.out_pwm);
// lwprintf("mot speed: %f\r\n", param_m1.real_speed);
lwprintf("%f,%f,%f\r\n", param_m1.real_speed, param_m1.target_speed, param_m1.out_pwm);
/* add user code end 3 */
}
}