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feat: 增加CRC-16校验(顺便添加了缺少的厂家设备驱动)

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feat: 增加第三方模块 lwrb
feat: 增加麦轮逆解部分
feat: 增加LOG输出格式
This commit is contained in:
bmy
2024-04-22 11:34:39 +08:00
parent af1b9dc867
commit 838c8bb81e
44 changed files with 15100 additions and 516 deletions
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232
libraries/drivers/src/at32f403a_407_acc.c Normal file
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/**
**************************************************************************
* @file at32f403a_407_acc.c
* @brief contains all the functions for the acc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f403a_407_conf.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @defgroup ACC
* @brief ACC driver modules
* @{
*/
#ifdef ACC_MODULE_ENABLED
/** @defgroup ACC_private_functions
* @{
*/
/**
* @brief enable or disable the acc calibration mode.
* @param acc_trim: specifies the acc calibration type.
* this parameter can be one of the following values:
* - ACC_CAL_HICKCAL
* - ACC_CAL_HICKTRIM
* @param new_state: specifies the acc calibration to be enabled or disabled.(TRUE or FALSE)
* @retval none
*/
void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state)
{
if(acc_trim == ACC_CAL_HICKCAL)
{
ACC->ctrl1_bit.entrim = FALSE;
}
else
{
ACC->ctrl1_bit.entrim = TRUE;
}
ACC->ctrl1_bit.calon = new_state;
}
/**
* @brief store calibration step data in acc's ctrl1 register.
* @param step_value: value to be stored in the acc's ctrl1 register
* @retval none
*/
void acc_step_set(uint8_t step_value)
{
ACC->ctrl1_bit.step = step_value;
}
/**
* @brief enable or disable the specified acc interrupts.
* @param acc_int: specifies the acc interrupt sources to be enabled or disabled.
* this parameter can be one of the following values:
* - ACC_CALRDYIEN_INT
* - ACC_EIEN_INT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state)
{
if(acc_int == ACC_CALRDYIEN_INT)
{
ACC->ctrl1_bit.calrdyien = new_state;
}
else
{
ACC->ctrl1_bit.eien = new_state;
}
}
/**
* @brief return the current acc hicktrim value.
* @param none
* @retval 8-bit hicktrim value.
*/
uint8_t acc_hicktrim_get(void)
{
return ((uint8_t)(ACC->ctrl2_bit.hicktrim));
}
/**
* @brief return the current acc hickcal value.
* @param none
* @retval 8-bit hicktrim value.
*/
uint8_t acc_hickcal_get(void)
{
return ((uint8_t)(ACC->ctrl2_bit.hickcal));
}
/**
* @brief wtire the value to acc c1 register.
* @param acc_c1_value
* @retval none.
*/
void acc_write_c1(uint16_t acc_c1_value)
{
ACC->c1 = acc_c1_value;
}
/**
* @brief wtire the value to acc c2 register.
* @param acc_c2_value
* @retval none.
*/
void acc_write_c2(uint16_t acc_c2_value)
{
ACC->c2 = acc_c2_value;
}
/**
* @brief wtire the value to acc c3 register.
* @param acc_c3_value
* @retval none.
*/
void acc_write_c3(uint16_t acc_c3_value)
{
ACC->c3 = acc_c3_value;
}
/**
* @brief return the current acc c1 value.
* @param none
* @retval 16-bit c1 value.
*/
uint16_t acc_read_c1(void)
{
return ((uint16_t)(ACC->c1));
}
/**
* @brief return the current acc c2 value.
* @param none
* @retval 16-bit c2 value.
*/
uint16_t acc_read_c2(void)
{
return ((uint16_t)(ACC->c2));
}
/**
* @brief return the current acc c3 value.
* @param none
* @retval 16-bit c3 value.
*/
uint16_t acc_read_c3(void)
{
return ((uint16_t)(ACC->c3));
}
/**
* @brief check whether the specified acc flag is set or not.
* @param acc_flag: specifies the flag to check.
* this parameter can be one of the following values:
* - ACC_RSLOST_FLAG
* - ACC_CALRDY_FLAG
* @retval flag_status (SET or RESET)
*/
flag_status acc_flag_get(uint16_t acc_flag)
{
if(acc_flag == ACC_CALRDY_FLAG)
return (flag_status)(ACC->sts_bit.calrdy);
else
return (flag_status)(ACC->sts_bit.rslost);
}
/**
* @brief check whether the specified acc interrupt flag is set or not.
* @param acc_flag: specifies the flag to check.
* this parameter can be one of the following values:
* - ACC_RSLOST_FLAG
* - ACC_CALRDY_FLAG
* @retval flag_status (SET or RESET)
*/
flag_status acc_interrupt_flag_get(uint16_t acc_flag)
{
if(acc_flag == ACC_CALRDY_FLAG)
return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien);
else
return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien);
}
/**
* @brief clear the specified acc flag is set or not.
* @param acc_flag: specifies the flag to check.
* this parameter can be any combination of the following values:
* - ACC_RSLOST_FLAG
* - ACC_CALRDY_FLAG
* @retval none
*/
void acc_flag_clear(uint16_t acc_flag)
{
ACC->sts = ~acc_flag;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

224
libraries/drivers/src/at32f403a_407_bpr.c Normal file
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/**
**************************************************************************
* @file at32f403a_407_bpr.c
* @brief contains all the functions for the bpr firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f403a_407_conf.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @defgroup BPR
* @brief BPR driver modules
* @{
*/
#ifdef BPR_MODULE_ENABLED
/** @defgroup BPR_private_functions
* @{
*/
/**
* @brief bpr reset by crm reset register
* @param none
* @retval none
*/
void bpr_reset(void)
{
crm_battery_powered_domain_reset(TRUE);
crm_battery_powered_domain_reset(FALSE);
}
/**
* @brief bpr event flag get, for tamper event flag
* @param flag: specifies the flag to check.
* this parameter can be one of the following values:
* - BPR_TAMPER_INTERRUPT_FLAG: tamper interrupt flag
* - BPR_TAMPER_EVENT_FLAG: tamper event flag
* @retval state of tamper event flag
*/
flag_status bpr_flag_get(uint32_t flag)
{
if(flag == BPR_TAMPER_INTERRUPT_FLAG)
{
return (flag_status)(BPR->ctrlsts_bit.tpif);
}
else
{
return (flag_status)(BPR->ctrlsts_bit.tpef);
}
}
/**
* @brief bpr interrupt flag get
* @param flag: specifies the flag to check.
* this parameter can be one of the following values:
* - BPR_TAMPER_INTERRUPT_FLAG: tamper interrupt flag
* - BPR_TAMPER_EVENT_FLAG: tamper event flag
* @retval state of tamper event flag
*/
flag_status bpr_interrupt_flag_get(uint32_t flag)
{
if(flag == BPR_TAMPER_INTERRUPT_FLAG)
{
return (flag_status)(BPR->ctrlsts_bit.tpif && BPR->ctrlsts_bit.tpien);
}
else
{
return (flag_status)(BPR->ctrlsts_bit.tpef && BPR->ctrlsts_bit.tpien);
}
}
/**
* @brief clear bpr tamper flag
* @param flag: specifies the flag to clear.
* this parameter can be one of the following values:
* - BPR_TAMPER_INTERRUPT_FLAG: tamper interrupt flag
* - BPR_TAMPER_EVENT_FLAG: tamper event flag
* @retval none
*/
void bpr_flag_clear(uint32_t flag)
{
if(flag == BPR_TAMPER_INTERRUPT_FLAG)
{
BPR->ctrlsts_bit.tpifclr = TRUE;
}
else
{
BPR->ctrlsts_bit.tpefclr = TRUE;
}
}
/**
* @brief enable or disable bpr tamper interrupt
* @param new_state (TRUE or FALSE)
* @retval none
*/
void bpr_interrupt_enable(confirm_state new_state)
{
BPR->ctrlsts_bit.tpien = new_state;
}
/**
* @brief read bpr bpr data
* @param bpr_data
* this parameter can be one of the following values:
* - BPR_DATA1
* - BPR_DATA2
* ...
* - BPR_DATA41
* - BPR_DATA42
* @retval none
*/
uint16_t bpr_data_read(bpr_data_type bpr_data)
{
return (*(__IO uint16_t *)(BPR_BASE + bpr_data));
}
/**
* @brief write bpr data
* @param bpr_data
* this parameter can be one of the following values:
* - BPR_DATA1
* - BPR_DATA2
* ...
* - BPR_DATA41
* - BPR_DATA42
* @param data_value (0x0000~0xFFFF)
* @retval none
*/
void bpr_data_write(bpr_data_type bpr_data, uint16_t data_value)
{
(*(__IO uint32_t *)(BPR_BASE + bpr_data)) = data_value;
}
/**
* @brief select bpr rtc output
* @param output_source
* this parameter can be one of the following values:
* - BPR_RTC_OUTPUT_NONE: output disable.
* - BPR_RTC_OUTPUT_CLOCK_CAL_BEFORE: output clock before calibration.
* - BPR_RTC_OUTPUT_ALARM: output alarm event with pluse mode.
* - BPR_RTC_OUTPUT_SECOND: output second event with pluse mode.
* - BPR_RTC_OUTPUT_CLOCK_CAL_AFTER: output clock after calibration.
* - BPR_RTC_OUTPUT_ALARM_TOGGLE: output alarm event with toggle mode.
* - BPR_RTC_OUTPUT_SECOND_TOGGLE: output second event with toggle mode.
* @retval none
*/
void bpr_rtc_output_select(bpr_rtc_output_type output_source)
{
/* clear cco,asoe,asos,ccos,togen bits */
BPR->rtccal &= (uint32_t)~0x0F80;
/* set output_source value */
BPR->rtccal |= output_source;
}
/**
* @brief set rtc clock calibration value
* @param calibration_value (0x00~0x7f)
* @retval none
*/
void bpr_rtc_clock_calibration_value_set(uint8_t calibration_value)
{
/* set rtc clock calibration value */
BPR->rtccal_bit.calval= calibration_value;
}
/**
* @brief enable or disable bpr tamper pin
* @param new_state (TRUE or FALSE)
* @retval none
*/
void bpr_tamper_pin_enable(confirm_state new_state)
{
BPR->ctrl_bit.tpen = new_state;
}
/**
* @brief set bpr tamper pin active level
* @param active_level
* this parameter can be one of the following values:
* - BPR_TAMPER_PIN_ACTIVE_HIGH: tamper pin input active level is high.
* - BPR_TAMPER_PIN_ACTIVE_LOW: tamper pin input active level is low.
* @retval none
*/
void bpr_tamper_pin_active_level_set(bpr_tamper_pin_active_level_type active_level)
{
BPR->ctrl_bit.tpp = active_level;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

208
libraries/drivers/src/at32f403a_407_crc.c Normal file
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/**
**************************************************************************
* @file at32f403a_407_crc.c
* @brief contains all the functions for the crc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f403a_407_conf.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @defgroup CRC
* @brief CRC driver modules
* @{
*/
#ifdef CRC_MODULE_ENABLED
/** @defgroup CRC_private_functions
* @{
*/
/**
* @brief reset the crc data register.
* @param none
* @retval none
*/
void crc_data_reset(void)
{
/* reset crc generator */
CRC->ctrl_bit.rst = 0x1;
}
/**
* @brief compute the 32-bit crc of a given data word(32-bit).
* @param data: data word(32-bit) to compute its crc
* @retval 32-bit crc
*/
uint32_t crc_one_word_calculate(uint32_t data)
{
CRC->dt = data;
return (CRC->dt);
}
/**
* @brief compute the 32-bit crc of a given buffer of data word(32-bit).
* @param pbuffer: pointer to the buffer containing the data to be computed
* @param length: length of the buffer to be computed
* @retval 32-bit crc
*/
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length)
{
uint32_t index = 0;
for(index = 0; index < length; index++)
{
CRC->dt = pbuffer[index];
}
return (CRC->dt);
}
/**
* @brief return the current crc value.
* @param none
* @retval 32-bit crc
*/
uint32_t crc_data_get(void)
{
return (CRC->dt);
}
/**
* @brief store a 8-bit data in the common data register.
* @param cdt_value: 8-bit value to be stored in the common data register
* @retval none
*/
void crc_common_data_set(uint8_t cdt_value)
{
CRC->cdt_bit.cdt = cdt_value;
}
/**
* @brief return the 8-bit data stored in the common data register
* @param none
* @retval 8-bit value of the common data register
*/
uint8_t crc_common_data_get(void)
{
return (CRC->cdt_bit.cdt);
}
/**
* @brief set the 32-bit initial data of crc
* @param value: initial data
* @retval none
*/
void crc_init_data_set(uint32_t value)
{
CRC->idt = value;
}
/**
* @brief control the reversal of the bit order in the input data
* @param value
* this parameter can be one of the following values:
* - CRC_REVERSE_INPUT_NO_AFFECTE
* - CRC_REVERSE_INPUT_BY_BYTE
* - CRC_REVERSE_INPUT_BY_HALFWORD
* - CRC_REVERSE_INPUT_BY_WORD
* @retval none.
*/
void crc_reverse_input_data_set(crc_reverse_input_type value)
{
CRC->ctrl_bit.revid = value;
}
/**
* @brief control the reversal of the bit order in the output data
* @param value
* this parameter can be one of the following values:
* - CRC_REVERSE_OUTPUT_NO_AFFECTE
* - CRC_REVERSE_OUTPUT_DATA
* @retval none.
*/
void crc_reverse_output_data_set(crc_reverse_output_type value)
{
CRC->ctrl_bit.revod = value;
}
/**
* @brief config crc polynomial value
* @param value
* 32-bit new data of crc poly value
* @retval none.
*/
void crc_poly_value_set(uint32_t value)
{
CRC->poly = value;
}
/**
* @brief return crc polynomial value
* @param none
* @retval 32-bit value of the polynomial value.
*/
uint32_t crc_poly_value_get(void)
{
return (CRC->poly);
}
/**
* @brief config crc polynomial data size
* @param size
* this parameter can be one of the following values:
* - CRC_POLY_SIZE_32B
* - CRC_POLY_SIZE_16B
* - CRC_POLY_SIZE_8B
* - CRC_POLY_SIZE_7B
* @retval none.
*/
void crc_poly_size_set(crc_poly_size_type size)
{
CRC->ctrl_bit.poly_size = size;
}
/**
* @brief return crc polynomial data size
* @param none
* @retval polynomial data size.
*/
crc_poly_size_type crc_poly_size_get(void)
{
return (crc_poly_size_type)(CRC->ctrl_bit.poly_size);
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

378
libraries/drivers/src/at32f403a_407_dac.c Normal file
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/**
**************************************************************************
* @file at32f403a_407_dac.c
* @brief contains all the functions for the dac firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f403a_407_conf.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @defgroup DAC
* @brief DAC driver modules
* @{
*/
#ifdef DAC_MODULE_ENABLED
/** @defgroup DAC_private_functions
* @{
*/
/**
* @brief dac reset
* @param none
* @retval none
*/
void dac_reset(void)
{
crm_periph_reset(CRM_DAC_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_DAC_PERIPH_RESET, FALSE);
}
/**
* @brief enable or disable dac
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dac_enable(dac_select_type dac_select, confirm_state new_state)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1en = new_state;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2en = new_state;
break;
default:
break;
}
}
/**
* @brief enable or disable dac output buffer
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state)
{
new_state = (confirm_state)!new_state;
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1obdis = new_state;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2obdis = new_state;
break;
default:
break;
}
}
/**
* @brief enable or disable dac trigger
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1trgen = new_state;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2trgen = new_state;
break;
default:
break;
}
}
/**
* @brief select dac trigger
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param dac_trigger_source
* this parameter can be one of the following values:
* - DAC_TMR6_TRGOUT_EVENT
* - DAC_TMR8_TRGOUT_EVENT
* - DAC_TMR7_TRGOUT_EVENT
* - DAC_TMR5_TRGOUT_EVENT
* - DAC_TMR2_TRGOUT_EVENT
* - DAC_TMR4_TRGOUT_EVENT
* - DAC_EXTERNAL_INTERRUPT_LINE_9
* - DAC_SOFTWARE_TRIGGER
* @retval none
*/
void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_source)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1trgsel = dac_trigger_source;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2trgsel = dac_trigger_source;
break;
default:
break;
}
}
/**
* @brief generate dac software trigger
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @retval none
*/
void dac_software_trigger_generate(dac_select_type dac_select)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->swtrg_bit.d1swtrg = TRUE;
break;
case DAC2_SELECT:
DAC->swtrg_bit.d2swtrg = TRUE;
break;
default:
break;
}
}
/**
* @brief generate dac dual software trigger synchronously
* @param none
* @retval none
*/
void dac_dual_software_trigger_generate(void)
{
DAC->swtrg |= 0x03;
}
/**
* @brief generate dac wave
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param dac_wave
* this parameter can be one of the following values:
* - DAC_WAVE_GENERATE_NONE
* - DAC_WAVE_GENERATE_NOISE
* - DAC_WAVE_GENERATE_TRIANGLE
* @retval none
*/
void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1nm = dac_wave;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2nm = dac_wave;
break;
default:
break;
}
}
/**
* @brief select dac mask amplitude
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param dac_mask_amplitude
* this parameter can be one of the following values:
* - DAC_LSFR_BIT0_AMPLITUDE_1
* - DAC_LSFR_BIT10_AMPLITUDE_3
* - DAC_LSFR_BIT20_AMPLITUDE_7
* - DAC_LSFR_BIT30_AMPLITUDE_15
* - DAC_LSFR_BIT40_AMPLITUDE_31
* - DAC_LSFR_BIT50_AMPLITUDE_63
* - DAC_LSFR_BIT60_AMPLITUDE_127
* - DAC_LSFR_BIT70_AMPLITUDE_255
* - DAC_LSFR_BIT80_AMPLITUDE_511
* - DAC_LSFR_BIT90_AMPLITUDE_1023
* - DAC_LSFR_BITA0_AMPLITUDE_2047
* - DAC_LSFR_BITB0_AMPLITUDE_4095
* @retval none
*/
void dac_mask_amplitude_select(dac_select_type dac_select, dac_mask_amplitude_type dac_mask_amplitude)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1nbsel = dac_mask_amplitude;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2nbsel = dac_mask_amplitude;
break;
default:
break;
}
}
/**
* @brief enable or disable dac dma
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dac_dma_enable(dac_select_type dac_select, confirm_state new_state)
{
switch(dac_select)
{
case DAC1_SELECT:
DAC->ctrl_bit.d1dmaen = new_state;
break;
case DAC2_SELECT:
DAC->ctrl_bit.d2dmaen = new_state;
break;
default:
break;
}
}
/**
* @brief get dac data output
* @param dac_select
* this parameter can be one of the following values:
* - DAC1_SELECT
* - DAC2_SELECT
* @retval dac channel data output
*/
uint16_t dac_data_output_get(dac_select_type dac_select)
{
uint16_t data_output =0 ;
switch(dac_select)
{
case DAC1_SELECT:
data_output = DAC->d1odt_bit.d1odt;
break;
case DAC2_SELECT:
data_output = DAC->d2odt_bit.d2odt;
break;
default:
break;
}
return data_output;
}
/**
* @brief set dac1 data
* @param dac1_aligned
* this parameter can be one of the following values:
* DAC1_12BIT_RIGHT
* DAC1_12BIT_LEFT
* DAC1_8BIT_RIGHT
* @param dac1_data :indecate from selected data holding register
* @retval none
*/
void dac_1_data_set(dac1_aligned_data_type dac1_aligned, uint16_t dac1_data)
{
*(__IO uint32_t *) dac1_aligned = dac1_data;
}
/**
* @brief set dac2 data
* @param dac2_aligned
* this parameter can be one of the following values:
* DAC2_12BIT_RIGHT
* DAC2_12BIT_LEFT
* DAC2_8BIT_RIGHT
* @param dac2_data :indecate from selected data holding register
* @retval none
*/
void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data)
{
*(__IO uint32_t *) dac2_aligned = dac2_data;
}
/**
* @brief set dac dual data
* @param dac_dual
* this parameter can be one of the following values:
* DAC_DUAL_12BIT_RIGHT
* DAC_DUAL_12BIT_LEFT
* DAC_DUAL_8BIT_RIGHT
* @param data1 :dac1 channel indecate from selected data holding register
* @param data2 :dac1 channel indecate from selected data holding register
* @retval none
*/
void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2)
{
switch(dac_dual)
{
case DAC_DUAL_12BIT_RIGHT:
*(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 16));
break;
case DAC_DUAL_12BIT_LEFT:
*(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 16));
break;
case DAC_DUAL_8BIT_RIGHT:
*(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 8));
break;
default:
break;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f403a_407_dma.c
* @brief contains all the functions for the dma firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f403a_407_conf.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @defgroup DMA
* @brief DMA driver modules
* @{
*/
#ifdef DMA_MODULE_ENABLED
/** @defgroup DMA_private_functions
* @{
*/
/**
* @brief reset the dmax channely registers.
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* - DMA1_CHANNEL6
* - DMA1_CHANNEL7
* - DMA2_CHANNEL1
* - DMA2_CHANNEL2
* - DMA2_CHANNEL3
* - DMA2_CHANNEL4
* - DMA2_CHANNEL5
* - DMA2_CHANNEL6
* - DMA2_CHANNEL7
* @retval none
*/
void dma_reset(dma_channel_type* dmax_channely)
{
uint32_t temp = 0;
dmax_channely->ctrl_bit.chen = FALSE;
dmax_channely->ctrl = 0;
dmax_channely->dtcnt = 0;
dmax_channely->paddr = 0;
dmax_channely->maddr = 0;
temp = (uint32_t)dmax_channely;
if((temp & 0x4ff) < 0x408)
{
/* dma1 channel */
DMA1->clr |= (uint32_t)(0x0f << ((((temp & 0xff) - 0x08) / 0x14) * 4));
}
else if((temp & 0x4ff) < 0x488)
{
/* dma2 channel */
DMA2->clr |= (uint32_t)(0x0f << ((((temp & 0xff) - 0x08) / 0x14) * 4));
}
}
/**
* @brief set the number of data to be transferred
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* - DMA1_CHANNEL6
* - DMA1_CHANNEL7
* - DMA2_CHANNEL1
* - DMA2_CHANNEL2
* - DMA2_CHANNEL3
* - DMA2_CHANNEL4
* - DMA2_CHANNEL5
* - DMA2_CHANNEL6
* - DMA2_CHANNEL7
* @param data_number: the number of data to be transferred(0x0000~0xFFFF)
* transfer.
* @retval none.
*/
void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number)
{
dmax_channely->dtcnt = data_number;
}
/**
* @brief get number of data from dtcnt register
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* - DMA1_CHANNEL6
* - DMA1_CHANNEL7
* - DMA2_CHANNEL1
* - DMA2_CHANNEL2
* - DMA2_CHANNEL3
* - DMA2_CHANNEL4
* - DMA2_CHANNEL5
* - DMA2_CHANNEL6
* - DMA2_CHANNEL7
* @retval the number of data.
*/
uint16_t dma_data_number_get(dma_channel_type* dmax_channely)
{
return (uint16_t)dmax_channely->dtcnt;
}
/**
* @brief enable or disable dma interrupt
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* - DMA1_CHANNEL6
* - DMA1_CHANNEL7
* - DMA2_CHANNEL1
* - DMA2_CHANNEL2
* - DMA2_CHANNEL3
* - DMA2_CHANNEL4
* - DMA2_CHANNEL5
* - DMA2_CHANNEL6
* - DMA2_CHANNEL7
* @param dma_int:
* this parameter can be any combination of the following values:
* - DMA_FDT_INT
* - DMA_HDT_INT
* - DMA_DTERR_INT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state)
{
if (new_state != FALSE)
{
dmax_channely->ctrl |= dma_int;
}
else
{
dmax_channely->ctrl &= ~dma_int;
}
}
/**
* @brief enable or disable dma channely
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* - DMA1_CHANNEL6
* - DMA1_CHANNEL7
* - DMA2_CHANNEL1
* - DMA2_CHANNEL2
* - DMA2_CHANNEL3
* - DMA2_CHANNEL4
* - DMA2_CHANNEL5
* - DMA2_CHANNEL6
* - DMA2_CHANNEL7
* @param new_state (TRUE or FALSE)
* @retval None
*/
void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state)
{
dmax_channely->ctrl_bit.chen = new_state;
}
/**
* @brief initialize the dma_x flexible function according to the specified parameters.
* @param dma_x:
* this parameter can be one of the following values:
* - DMA1
* - DMA2
* @param flex_channelx:
* this parameter can be one of the following values:
* - FLEX_CHANNEL1
* - FLEX_CHANNEL2
* - FLEX_CHANNEL3
* - FLEX_CHANNEL4
* - FLEX_CHANNEL5
* - FLEX_CHANNEL6
* - FLEX_CHANNEL7
* @param flexible_request: every peripheral have specified hardware_id.
* this parameter can be one of the following values:
* - DMA_FLEXIBLE_ADC1 - DMA_FLEXIBLE_ADC3 - DMA_FLEXIBLE_DAC1 - DMA_FLEXIBLE_DAC2
* - DMA_FLEXIBLE_SPI1_RX - DMA_FLEXIBLE_SPI1_TX - DMA_FLEXIBLE_SPI2_RX - DMA_FLEXIBLE_SPI2_TX
* - DMA_FLEXIBLE_SPI3_RX - DMA_FLEXIBLE_SPI3_TX - DMA_FLEXIBLE_SPI4_RX - DMA_FLEXIBLE_SPI4_TX
* - DMA_FLEXIBLE_I2S2EXT_RX - DMA_FLEXIBLE_I2S2EXT_TX - DMA_FLEXIBLE_I2S3EXT_RX - DMA_FLEXIBLE_I2S3EXT_TX
* - DMA_FLEXIBLE_UART1_RX - DMA_FLEXIBLE_UART1_TX - DMA_FLEXIBLE_UART2_RX - DMA_FLEXIBLE_UART2_TX
* - DMA_FLEXIBLE_UART3_RX - DMA_FLEXIBLE_UART3_TX - DMA_FLEXIBLE_UART4_RX - DMA_FLEXIBLE_UART4_TX
* - DMA_FLEXIBLE_UART5_RX - DMA_FLEXIBLE_UART5_TX - DMA_FLEXIBLE_UART6_RX - DMA_FLEXIBLE_UART6_TX
* - DMA_FLEXIBLE_UART7_RX - DMA_FLEXIBLE_UART7_TX - DMA_FLEXIBLE_UART8_RX - DMA_FLEXIBLE_UART8_TX
* - DMA_FLEXIBLE_I2C1_RX - DMA_FLEXIBLE_I2C1_TX - DMA_FLEXIBLE_I2C2_RX - DMA_FLEXIBLE_I2C2_TX
* - DMA_FLEXIBLE_I2C3_RX - DMA_FLEXIBLE_I2C3_TX - DMA_FLEXIBLE_SDIO1 - DMA_FLEXIBLE_SDIO2
* - DMA_FLEXIBLE_TMR1_TRIG - DMA_FLEXIBLE_TMR1_HALL - DMA_FLEXIBLE_TMR1_OVERFLOW- DMA_FLEXIBLE_TMR1_CH1
* - DMA_FLEXIBLE_TMR1_CH2 - DMA_FLEXIBLE_TMR1_CH3 - DMA_FLEXIBLE_TMR1_CH4 - DMA_FLEXIBLE_TMR2_TRIG
* - DMA_FLEXIBLE_TMR2_OVERFLOW- DMA_FLEXIBLE_TMR2_CH1 - DMA_FLEXIBLE_TMR2_CH2 - DMA_FLEXIBLE_TMR2_CH3
* - DMA_FLEXIBLE_TMR2_CH4 - DMA_FLEXIBLE_TMR3_TRIG - DMA_FLEXIBLE_TMR3_OVERFLOW- DMA_FLEXIBLE_TMR3_CH1
* - DMA_FLEXIBLE_TMR3_CH2 - DMA_FLEXIBLE_TMR3_CH3 - DMA_FLEXIBLE_TMR3_CH4 - DMA_FLEXIBLE_TMR4_TRIG
* - DMA_FLEXIBLE_TMR4_OVERFLOW- DMA_FLEXIBLE_TMR4_CH1 - DMA_FLEXIBLE_TMR4_CH2 - DMA_FLEXIBLE_TMR4_CH3
* - DMA_FLEXIBLE_TMR4_CH4 - DMA_FLEXIBLE_TMR5_TRIG - DMA_FLEXIBLE_TMR5_OVERFLOW- DMA_FLEXIBLE_TMR5_CH1
* - DMA_FLEXIBLE_TMR5_CH2 - DMA_FLEXIBLE_TMR5_CH3 - DMA_FLEXIBLE_TMR5_CH4 - DMA_FLEXIBLE_TMR6_OVERFLOW
* - DMA_FLEXIBLE_TMR7_OVERFLOW- DMA_FLEXIBLE_TMR8_TRIG - DMA_FLEXIBLE_TMR8_HALL - DMA_FLEXIBLE_TMR8_OVERFLOW
* - DMA_FLEXIBLE_TMR8_CH1 - DMA_FLEXIBLE_TMR8_CH2 - DMA_FLEXIBLE_TMR8_CH3 - DMA_FLEXIBLE_TMR8_CH4
* @retval none
*/
void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request)
{
if(dma_x->src_sel1_bit.dma_flex_en == RESET)
{
dma_x->src_sel1_bit.dma_flex_en = TRUE;
}
if(flex_channelx == FLEX_CHANNEL1)
{
dma_x->src_sel0_bit.ch1_src = flexible_request;
}
else if(flex_channelx == FLEX_CHANNEL2)
{
dma_x->src_sel0_bit.ch2_src = flexible_request;
}
else if(flex_channelx == FLEX_CHANNEL3)
{
dma_x->src_sel0_bit.ch3_src = flexible_request;
}
else if(flex_channelx == FLEX_CHANNEL4)
{
dma_x->src_sel0_bit.ch4_src = flexible_request;
}
else if(flex_channelx == FLEX_CHANNEL5)
{
dma_x->src_sel1_bit.ch5_src = flexible_request;
}
else if(flex_channelx == FLEX_CHANNEL6)
{
dma_x->src_sel1_bit.ch6_src = flexible_request;
}
else
{
if(flex_channelx == FLEX_CHANNEL7)
{
dma_x->src_sel1_bit.ch7_src = flexible_request;
}
}
}
/**
* @brief get dma interrupt flag
* @param dmax_flag
* this parameter can be one of the following values:
* - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
* - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
* - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
* - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
* - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
* - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
* - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
* - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
* - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
* - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
* - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
* - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
* - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
* - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
* @retval state of dma flag
*/
flag_status dma_interrupt_flag_get(uint32_t dmax_flag)
{
flag_status status = RESET;
uint32_t temp = 0;
if(dmax_flag > 0x10000000)
{
temp = DMA2->sts;
}
else
{
temp = DMA1->sts;
}
if ((temp & dmax_flag) != (uint16_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief get dma flag
* @param dmax_flag
* this parameter can be one of the following values:
* - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
* - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
* - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
* - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
* - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
* - DMA1_GL6_FLAG - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
* - DMA1_GL7_FLAG - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
* - DMA2_GL1_FLAG - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
* - DMA2_GL2_FLAG - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
* - DMA2_GL3_FLAG - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
* - DMA2_GL4_FLAG - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
* - DMA2_GL5_FLAG - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
* - DMA2_GL6_FLAG - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
* - DMA2_GL7_FLAG - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
* @retval state of dma flag
*/
flag_status dma_flag_get(uint32_t dmax_flag)
{
flag_status status = RESET;
uint32_t temp = 0;
if(dmax_flag > 0x10000000)
{
temp = DMA2->sts;
}
else
{
temp = DMA1->sts;
}
if ((temp & dmax_flag) != (uint16_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief clear dma flag
* @param dmax_flag
* this parameter can be one of the following values:
* - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
* - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
* - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
* - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
* - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
* - DMA1_GL6_FLAG - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
* - DMA1_GL7_FLAG - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
* - DMA2_GL1_FLAG - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
* - DMA2_GL2_FLAG - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
* - DMA2_GL3_FLAG - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
* - DMA2_GL4_FLAG - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
* - DMA2_GL5_FLAG - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
* - DMA2_GL6_FLAG - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
* - DMA2_GL7_FLAG - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
* @retval none
*/
void dma_flag_clear(uint32_t dmax_flag)
{
if(dmax_flag > 0x10000000)
{
DMA2->clr = (uint32_t)(dmax_flag & 0x0FFFFFFF);
}
else
{
DMA1->clr = dmax_flag;
}
}
/**
* @brief dma init config with its default value.
* @param dma_init_struct : pointer to a dma_init_type structure which will
* be initialized.
* @retval none
*/
void dma_default_para_init(dma_init_type* dma_init_struct)
{
dma_init_struct->peripheral_base_addr = 0x0;
dma_init_struct->memory_base_addr = 0x0;
dma_init_struct->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dma_init_struct->buffer_size = 0x0;
dma_init_struct->peripheral_inc_enable = FALSE;
dma_init_struct->memory_inc_enable = FALSE;
dma_init_struct->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct->loop_mode_enable = FALSE;
dma_init_struct->priority = DMA_PRIORITY_LOW;
}
/**
* @brief dma init
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* - DMA1_CHANNEL6
* - DMA1_CHANNEL7
* - DMA2_CHANNEL1
* - DMA2_CHANNEL2
* - DMA2_CHANNEL3
* - DMA2_CHANNEL4
* - DMA2_CHANNEL5
* - DMA2_CHANNEL6
* - DMA2_CHANNEL7
* @param dma_initstruct : pointer to a dma_init_type structure.
* @retval none
*/
void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct)
{
/* clear ctrl register dtd bit and m2m bit */
dmax_channely->ctrl &= 0xbfef;
dmax_channely->ctrl |= dma_init_struct->direction;
dmax_channely->ctrl_bit.chpl = dma_init_struct->priority;
dmax_channely->ctrl_bit.mwidth = dma_init_struct->memory_data_width;
dmax_channely->ctrl_bit.pwidth = dma_init_struct->peripheral_data_width;
dmax_channely->ctrl_bit.mincm = dma_init_struct->memory_inc_enable;
dmax_channely->ctrl_bit.pincm = dma_init_struct->peripheral_inc_enable;
dmax_channely->ctrl_bit.lm = dma_init_struct->loop_mode_enable;
dmax_channely->dtcnt = dma_init_struct->buffer_size;
dmax_channely->paddr = dma_init_struct->peripheral_base_addr;
dmax_channely->maddr = dma_init_struct->memory_base_addr;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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libraries/drivers/src/at32f403a_407_emac.c Normal file
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libraries/drivers/src/at32f403a_407_rtc.c Normal file
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/**
**************************************************************************
* @file at32f403a_407_rtc.c
* @brief contains all the functions for the rtc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f403a_407_conf.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @defgroup RTC
* @brief RTC driver modules
* @{
*/
#ifdef RTC_MODULE_ENABLED
/** @defgroup RTC_private_functions
* @{
*/
/**
* @brief rtc counter set
* @param counter_value (0x0000_0000 ~ 0xFFFF_FFFF)
* @retval none
*/
void rtc_counter_set(uint32_t counter_value)
{
/* enter rtc config mode */
RTC->ctrll = 0x003F;
/* set rtc counter */
RTC->cnth_bit.cnt = (uint16_t)(counter_value >> 16);
RTC->cntl_bit.cnt = (uint16_t)(counter_value & 0x0000FFFF);
/* exit rtc config mode */
RTC->ctrll = 0x000F;
}
/**
* @brief rtc counter get
* @param none
* @retval rtc counter
*/
uint32_t rtc_counter_get(void)
{
uint32_t cnt = 0;
cnt = RTC->cnth;
cnt = (cnt << 16) | RTC->cntl;
return cnt;
}
/**
* @brief rtc divider set
* @param div_value (0x0000_0000 ~ 0x000F_FFFF)
* @retval none
*/
void rtc_divider_set(uint32_t div_value)
{
/* enter rtc config mode */
RTC->ctrll = 0x003F;
/* set rtc divider */
RTC->divh_bit.div = (uint16_t)(div_value >> 16);
RTC->divl_bit.div = (uint16_t)(div_value & 0x0000FFFF);
/* exit rtc config mode */
RTC->ctrll = 0x000F;
}
/**
* @brief rtc divider get
* @param none
* @retval rtc counter
*/
uint32_t rtc_divider_get(void)
{
uint32_t div = 0;
div = RTC->divcnth;
div = (div << 16) | RTC->divcntl;
return div;
}
/**
* @brief rtc alarm value set
* @param alarm_value (0x0000_0000 ~ 0xFFFF_FFFF)
* @retval none
*/
void rtc_alarm_set(uint32_t alarm_value)
{
/* enter rtc config mode */
RTC->ctrll = 0x003F;
/* set rtc alarm value */
RTC->tah_bit.ta = (uint16_t)(alarm_value >> 16);
RTC->tal_bit.ta = (uint16_t)(alarm_value & 0x0000FFFF);
/* exit rtc config mode */
RTC->ctrll = 0x000F;
}
/**
* @brief rtc interrupt enable
* @param source
* this parameter can be any combination of the following values:
* - RTC_TS_INT: time second interrupt.
* - RTC_TA_INT: time alarm interrupt.
* - RTC_OVF_INT: overflow interrupt.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void rtc_interrupt_enable(uint16_t source, confirm_state new_state)
{
if(new_state == FALSE)
{
RTC->ctrlh &= ~source;
}
else
{
RTC->ctrlh |= source;
}
}
/**
* @brief rtc flag get
* @param flag
* this parameter can be one of the following values:
* - RTC_TS_FLAG: time second flag.
* - RTC_TA_FLAG: time alarm flag.
* - RTC_OVF_FLAG: overflow flag.
* - RTC_UPDF_FLAG: rtc update finish flag.
* - RTC_CFGF_FLAG: rtc configuration finish flag.
* @retval state of rtc flag
*/
flag_status rtc_flag_get(uint16_t flag)
{
flag_status status = RESET;
if ((RTC->ctrll & flag) != (uint16_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief rtc interrupt flag get
* @param flag
* this parameter can be one of the following values:
* - RTC_TS_FLAG: time second flag.
* - RTC_TA_FLAG: time alarm flag.
* - RTC_OVF_FLAG: overflow flag.
* @retval state of rtc flag
*/
flag_status rtc_interrupt_flag_get(uint16_t flag)
{
flag_status status = RESET;
if (((RTC->ctrll & flag) != (uint16_t)RESET) && ((RTC->ctrlh & flag) != (uint16_t)RESET))
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief rtc flag clear
* @param interrupt_flag
* this parameter can be any combination of the following values:
* - RTC_TS_FLAG: time second flag.
* - RTC_TA_FLAG: time alarm flag.
* - RTC_OVF_FLAG: overflow flag.
* - RTC_UPDF_FLAG: rtc update finish flag.
* @retval none
*/
void rtc_flag_clear(uint16_t flag)
{
RTC->ctrll = ~(flag | 0x10) | (RTC->ctrll_bit.cfgen << 4);
}
/**
* @brief rtc wait configuration finish
* @param none
* @retval none
*/
void rtc_wait_config_finish(void)
{
while (RTC->ctrll_bit.cfgf == 0);
}
/**
* @brief rtc wait update finish
* @param none
* @retval none
*/
void rtc_wait_update_finish(void)
{
while (RTC->ctrll_bit.updf == 0);
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

617
libraries/drivers/src/at32f403a_407_sdio.c Normal file
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@@ -0,0 +1,617 @@
/**
**************************************************************************
* @file at32f403a_407_sdio.c
* @brief contains all the functions for the sdio firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f403a_407_conf.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @defgroup SDIO
* @brief SDIO driver modules
* @{
*/
#ifdef SDIO_MODULE_ENABLED
/** @defgroup SDIO_private_functions
* @{
*/
/**
* @brief reset the sdio register
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @retval none
*/
void sdio_reset(sdio_type *sdio_x)
{
sdio_x->pwrctrl = 0x0;
sdio_x->clkctrl = 0x0;
sdio_x->argu = 0x0;
sdio_x->cmdctrl = 0x0;
sdio_x->dttmr = 0x0;
sdio_x->dtlen = 0x0;
sdio_x->dtctrl = 0x0;
sdio_x->inten = 0x0;
sdio_x->intclr = 0x004007FF;
}
/**
* @brief set the power status of the controller
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param power_state
* this parameter can be one of the following values:
* - SDIO_POWER_OFF
* - SDIO_POWER_ON
* @retval none
*/
void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state)
{
sdio_x->pwrctrl_bit.ps = power_state;
}
/**
* @brief get power status.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @retval sdio_power_state_type (SDIO_POWER_ON or SDIO_POWER_OFF)
*/
sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x)
{
return (sdio_power_state_type)(sdio_x->pwrctrl_bit.ps);
}
/**
* @brief config sdio clock
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param clk_div: sdio clock divide factor(frequency = sdio_clk / [clk_psc + 2]).
* @param clk_edg
* this parameter can be one of the following values:
* - SDIO_CLOCK_EDGE_RISING
* - SDIO_CLOCK_EDGE_FALLING
* @retval none
*/
void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg)
{
/* config clock edge */
sdio_x->clkctrl_bit.clkegs = clk_edg;
/* config clock divide [7:0] */
sdio_x->clkctrl_bit.clkdiv_l = (clk_div & 0xFF);
/* config clock divide [9:8] */
sdio_x->clkctrl_bit.clkdiv_h = ((clk_div & 0x300) >> 8);
}
/**
* @brief config sdio bus width
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param width
* this parameter can be one of the following values:
* - SDIO_BUS_WIDTH_D1
* - SDIO_BUS_WIDTH_D4
* - SDIO_BUS_WIDTH_D8
* @retval none
*/
void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width)
{
sdio_x->clkctrl_bit.busws = width;
}
/**
* @brief enable or disable clock divider bypss
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->clkctrl_bit.bypsen = new_state;
}
/**
* @brief enable or disable power saving mode, config sdio_ck clock output
* when the bus is idle.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->clkctrl_bit.pwrsven = new_state;
}
/**
* @brief enable or disable hardware flow control.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->clkctrl_bit.hfcen = new_state;
}
/**
* @brief enable or disable sdio_ck output.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->clkctrl_bit.clkoen = new_state;
}
/**
* @brief enable or disable dma.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->dtctrl_bit.dmaen = new_state;
}
/**
* @brief config corresponding interrupt.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param int_opt
* this parameter can be one of the following values:
* - SDIO_CMDFAIL_INT
* - SDIO_DTFAIL_INT
* - SDIO_CMDTIMEOUT_INT
* - SDIO_DTTIMEOUT_INT
* - SDIO_TXERRU_INT
* - SDIO_RXERRO_INT
* - SDIO_CMDRSPCMPL_INT
* - SDIO_CMDCMPL_INT
* - SDIO_DTCMP_INT
* - SDIO_SBITERR_INT
* - SDIO_DTBLKCMPL_INT
* - SDIO_DOCMD_INT
* - SDIO_DOTX_INT
* - SDIO_DORX_INT
* - SDIO_TXBUFH_INT
* - SDIO_RXBUFH_INT
* - SDIO_TXBUFF_INT
* - SDIO_RXBUFF_INT
* - SDIO_TXBUFE_INT
* - SDIO_RXBUFE_INT
* - SDIO_TXBUF_INT
* - SDIO_RXBUF_INT
* - SDIO_SDIOIF_INT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state)
{
/* enable interrupt */
if(TRUE == new_state)
{
sdio_x->inten |= int_opt;
}
/* disable interrupt */
else
{
sdio_x->inten &= ~(int_opt);
}
}
/**
* @brief get sdio interrupt flag.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param flag
* this parameter can be one of the following values:
* - SDIO_CMDFAIL_FLAG
* - SDIO_DTFAIL_FLAG
* - SDIO_CMDTIMEOUT_FLAG
* - SDIO_DTTIMEOUT_FLAG
* - SDIO_TXERRU_FLAG
* - SDIO_RXERRO_FLAG
* - SDIO_CMDRSPCMPL_FLAG
* - SDIO_CMDCMPL_FLAG
* - SDIO_DTCMPL_FLAG
* - SDIO_SBITERR_FLAG
* - SDIO_DTBLKCMPL_FLAG
* - SDIO_DOCMD_FLAG
* - SDIO_DOTX_FLAG
* - SDIO_DORX_FLAG
* - SDIO_TXBUFH_FLAG
* - SDIO_RXBUFH_FLAG
* - SDIO_TXBUFF_FLAG
* - SDIO_RXBUFF_FLAG
* - SDIO_TXBUFE_FLAG
* - SDIO_RXBUFE_FLAG
* - SDIO_TXBUF_FLAG
* - SDIO_RXBUF_FLAG
* - SDIO_SDIOIF_FLAG
* @retval flag_status (SET or RESET)
*/
flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag)
{
flag_status status = RESET;
if((sdio_x->inten & flag) && (sdio_x->sts & flag))
{
status = SET;
}
return status;
}
/**
* @brief get sdio flag.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param flag
* this parameter can be one of the following values:
* - SDIO_CMDFAIL_FLAG
* - SDIO_DTFAIL_FLAG
* - SDIO_CMDTIMEOUT_FLAG
* - SDIO_DTTIMEOUT_FLAG
* - SDIO_TXERRU_FLAG
* - SDIO_RXERRO_FLAG
* - SDIO_CMDRSPCMPL_FLAG
* - SDIO_CMDCMPL_FLAG
* - SDIO_DTCMPL_FLAG
* - SDIO_SBITERR_FLAG
* - SDIO_DTBLKCMPL_FLAG
* - SDIO_DOCMD_FLAG
* - SDIO_DOTX_FLAG
* - SDIO_DORX_FLAG
* - SDIO_TXBUFH_FLAG
* - SDIO_RXBUFH_FLAG
* - SDIO_TXBUFF_FLAG
* - SDIO_RXBUFF_FLAG
* - SDIO_TXBUFE_FLAG
* - SDIO_RXBUFE_FLAG
* - SDIO_TXBUF_FLAG
* - SDIO_RXBUF_FLAG
* - SDIO_SDIOIF_FLAG
* @retval flag_status (SET or RESET)
*/
flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag)
{
flag_status status = RESET;
if((sdio_x->sts & flag) == flag)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief clear sdio flag.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param int_opt
* this parameter can be any combination of the following values:
* - SDIO_CMDFAIL_FLAG
* - SDIO_DTFAIL_FLAG
* - SDIO_CMDTIMEOUT_FLAG
* - SDIO_DTTIMEOUT_FLAG
* - SDIO_TXERRU_FLAG
* - SDIO_RXERRO_FLAG
* - SDIO_CMDRSPCMPL_FLAG
* - SDIO_CMDCMPL_FLAG
* - SDIO_DTCMPL_FLAG
* - SDIO_SBITERR_FLAG
* - SDIO_DTBLKCMPL_FLAG
* - SDIO_SDIOIF_FLAG
* @retval none
*/
void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag)
{
sdio_x->intclr = flag;
}
/**
* @brief config sdio command.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param command_struct : pointer to a sdio_command_struct_type structure
* that contains the configuration information for the sdio command.
* @retval none
*/
void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct)
{
/* disable command path state machine */
sdio_x->cmdctrl_bit.ccsmen = FALSE;
/* config command argument */
sdio_x->argu = command_struct->argument;
/* config command register */
sdio_x->cmdctrl_bit.cmdidx = command_struct->cmd_index;
sdio_x->cmdctrl_bit.rspwt = command_struct->rsp_type;
sdio_x->cmdctrl_bit.intwt = (command_struct->wait_type & 0x1); /* [1:0] -> [0] */
sdio_x->cmdctrl_bit.pndwt = (command_struct->wait_type & 0x2)>>1; /* [1:0] -> [1] */
}
/**
* @brief enable or disable command path state machine(CPSM).
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->cmdctrl_bit.ccsmen = new_state;
}
/**
* @brief get command index of last command for which response received.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval uint8_t: command index
*/
uint8_t sdio_command_response_get(sdio_type *sdio_x)
{
return sdio_x->rspcmd_bit.rspcmd;
}
/**
* @brief get response received from the card for the last command.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param reg_index
* this parameter can be one of the following values:
* - SDIO_RSP1_INDEX
* - SDIO_RSP2_INDEX
* - SDIO_RSP3_INDEX
* - SDIO_RSP4_INDEX
* @retval uint32_t: response register value
*/
uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index)
{
uint32_t response_value = 0;
switch(reg_index)
{
case SDIO_RSP1_INDEX:
response_value = sdio_x->rsp1;
break;
case SDIO_RSP2_INDEX:
response_value = sdio_x->rsp2;
break;
case SDIO_RSP3_INDEX:
response_value = sdio_x->rsp3;
break;
case SDIO_RSP4_INDEX:
response_value = sdio_x->rsp4;
break;
default: break;
}
return response_value;
}
/**
* @brief config sdio data.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param data_struct : pointer to a sdio_data_struct_type structure
* that contains the configuration information for the sdio data.
* @retval none
*/
void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct)
{
/* disable data path state machine */
sdio_x->dtctrl_bit.tfren = FALSE;
/* config data block, transfer mode and transfer direction */
sdio_x->dtctrl_bit.blksize = data_struct->block_size;
sdio_x->dtctrl_bit.tfrdir = data_struct->transfer_direction;
sdio_x->dtctrl_bit.tfrmode = data_struct->transfer_mode;
/* config data length */
sdio_x->dtlen_bit.dtlen = data_struct->data_length;
/* config data transfer timeout */
sdio_x->dttmr_bit.timeout = data_struct->timeout;
}
/**
* @brief enable or disable data path state machine(DPSM).
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->dtctrl_bit.tfren = new_state;
}
/**
* @brief get the number of remaining data bytes to be transferred.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @retval uint32_t: number of bytes
*/
uint32_t sdio_data_counter_get(sdio_type *sdio_x)
{
return sdio_x->dtcnt;
}
/**
* @brief read a word data from sdio fifo.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @retval uint32_t: data received
*/
uint32_t sdio_data_read(sdio_type *sdio_x)
{
return sdio_x->buf;
}
/**
* @brief get the number of words left to be written to or read from fifo..
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @retval uint32_t: number of words
*/
uint32_t sdio_buffer_counter_get(sdio_type *sdio_x)
{
return sdio_x->bufcnt;
}
/**
* @brief write one word data to fifo.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param data: data to be transferred.
* @retval none
*/
void sdio_data_write(sdio_type *sdio_x, uint32_t data)
{
sdio_x->buf = data;
}
/**
* @brief set the read wait mode.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param mode
* this parameter can be one of the following values:
* - SDIO_READ_WAIT_CONTROLLED_BY_D2
* - SDIO_READ_WAIT_CONTROLLED_BY_CK
* @retval none
*/
void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode)
{
sdio_x->dtctrl_bit.rdwtmode = mode;
}
/**
* @brief enable or disable to start sd i/o read wait operation.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->dtctrl_bit.rdwtstart = new_state;
}
/**
* @brief enable or disable to stop sd i/o read wait operation.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->dtctrl_bit.rdwtstop = new_state;
}
/**
* @brief enable or disable the sd i/o function.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->dtctrl_bit.ioen = new_state;
}
/**
* @brief enable or disable sd i/o suspend command sending.
* @param sdio_x: to select the sdio peripheral.
* this parameter can be one of the following values:
* SDIO1, SDIO2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state)
{
sdio_x->cmdctrl_bit.iosusp = new_state;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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libraries/drivers/src/at32f403a_407_spi.c Normal file
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@@ -0,0 +1,677 @@
/**
**************************************************************************
* @file at32f403a_407_spi.c
* @brief contains all the functions for the spi firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f403a_407_conf.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @defgroup SPI
* @brief SPI driver modules
* @{
*/
#ifdef SPI_MODULE_ENABLED
/** @defgroup SPI_private_functions
* @{
*/
/**
* @brief spi reset by crm reset register
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @retval none
*/
void spi_i2s_reset(spi_type *spi_x)
{
if(spi_x == SPI1)
{
crm_periph_reset(CRM_SPI1_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SPI1_PERIPH_RESET, FALSE);
}
else if(spi_x == SPI2)
{
crm_periph_reset(CRM_SPI2_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SPI2_PERIPH_RESET, FALSE);
}
else if(spi_x == SPI3)
{
crm_periph_reset(CRM_SPI3_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SPI3_PERIPH_RESET, FALSE);
}
else if(spi_x == SPI4)
{
crm_periph_reset(CRM_SPI4_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SPI4_PERIPH_RESET, FALSE);
}
}
/**
* @brief spi init config with its default value.
* @param spi_init_struct : pointer to a spi_init_type structure which will
* be initialized.
* @retval none
*/
void spi_default_para_init(spi_init_type* spi_init_struct)
{
spi_init_struct->transmission_mode = SPI_TRANSMIT_FULL_DUPLEX;
spi_init_struct->master_slave_mode = SPI_MODE_SLAVE;
spi_init_struct->mclk_freq_division = SPI_MCLK_DIV_2;
spi_init_struct->first_bit_transmission = SPI_FIRST_BIT_MSB;
spi_init_struct->frame_bit_num = SPI_FRAME_8BIT;
spi_init_struct->clock_polarity = SPI_CLOCK_POLARITY_LOW;
spi_init_struct->clock_phase = SPI_CLOCK_PHASE_1EDGE;
spi_init_struct->cs_mode_selection = SPI_CS_SOFTWARE_MODE;
}
/**
* @brief spi init config with its setting value.
* @param spi_init_struct : pointer to a spi_init_type structure which will be initialized.
* @retval none
*/
void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct)
{
spi_x->i2sctrl_bit.i2smsel = FALSE;
if(spi_init_struct->transmission_mode == SPI_TRANSMIT_FULL_DUPLEX)
{
spi_x->ctrl1_bit.slben = FALSE;
spi_x->ctrl1_bit.slbtd = FALSE;
spi_x->ctrl1_bit.ora = FALSE;
}
else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_SIMPLEX_RX)
{
spi_x->ctrl1_bit.slben = FALSE;
spi_x->ctrl1_bit.slbtd = FALSE;
spi_x->ctrl1_bit.ora = TRUE;
}
else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_RX)
{
spi_x->ctrl1_bit.slben = TRUE;
spi_x->ctrl1_bit.slbtd = FALSE;
spi_x->ctrl1_bit.ora = FALSE;
}
else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_TX)
{
spi_x->ctrl1_bit.slben = TRUE;
spi_x->ctrl1_bit.slbtd = TRUE;
spi_x->ctrl1_bit.ora = FALSE;
}
spi_x->ctrl1_bit.swcsen = spi_init_struct->cs_mode_selection;
if((spi_init_struct->master_slave_mode == SPI_MODE_MASTER) && (spi_init_struct->cs_mode_selection == SPI_CS_SOFTWARE_MODE))
{
spi_x->ctrl1_bit.swcsil = TRUE;
}
else
{
spi_x->ctrl1_bit.swcsil = FALSE;
}
spi_x->ctrl1_bit.msten = spi_init_struct->master_slave_mode;
if(spi_init_struct->mclk_freq_division > SPI_MCLK_DIV_256)
{
spi_x->ctrl2_bit.mdiv_h = 1;
spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division & 0x7;
}
else
{
spi_x->ctrl2_bit.mdiv_h = 0;
spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division;
}
spi_x->ctrl1_bit.ltf = spi_init_struct->first_bit_transmission;
spi_x->ctrl1_bit.fbn = spi_init_struct->frame_bit_num;
spi_x->ctrl1_bit.clkpol = spi_init_struct->clock_polarity;
spi_x->ctrl1_bit.clkpha = spi_init_struct->clock_phase;
}
/**
* @brief spi next transmit crc for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @retval none
*/
void spi_crc_next_transmit(spi_type* spi_x)
{
spi_x->ctrl1_bit.ntc = TRUE;
}
/**
* @brief set the crc polynomial value for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param crc_poly: crc polynomial value.
* @retval none
*/
void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly)
{
spi_x->cpoly_bit.cpoly = crc_poly;
}
/**
* @brief return the crc polynomial register value for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @retval the select crc polynomial register value
*/
uint16_t spi_crc_polynomial_get(spi_type* spi_x)
{
return spi_x->cpoly_bit.cpoly;
}
/**
* @brief enable or disable the hardware crc calculation for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param new_state: new state of crc calculation.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_crc_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl1_bit.ccen = new_state;
}
/**
* @brief return the transmit or the receive crc value for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param crc_direction: select transmit or receive crc value to be read
* - SPI_CRC_RX
* - SPI_CRC_TX
* @retval the select crc register value
*/
uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction)
{
if(crc_direction == SPI_CRC_RX)
return spi_x->rcrc_bit.rcrc;
else
return spi_x->tcrc_bit.tcrc;
}
/**
* @brief enable or disable the hardware cs output for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param new_state: new state of spi master cs output.
* this parameter can be: TRUE or FALSE.
* note:the bit only use in spi master mode
* @retval none
*/
void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl2_bit.hwcsoe = new_state;
}
/**
* @brief set the software cs internal level for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param level: set the state of spi cs level.
* this parameter can be one of the following values:
* - SPI_SWCS_INTERNAL_LEVEL_LOW
* - SPI_SWCS_INTERNAL_LEVEL_HIGHT
* note:the bit only use when swcsen bit is set.
* note:when use this bit,io operation on the cs pin are invalid.
* @retval none
*/
void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level)
{
spi_x->ctrl1_bit.swcsil = level;
}
/**
* @brief set the data frame bit num for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param bit_num: set the data frame size
* - SPI_FRAME_8BIT
* - SPI_FRAME_16BIT
* @retval none
*/
void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num)
{
spi_x->ctrl1_bit.fbn = bit_num;
}
/**
* @brief set the data transmission direction in single line bidirectiona half duplex mode of the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param direction: data transfer direction
* this parameter can be one of the following values:
* - SPI_HALF_DUPLEX_DIRECTION_RX
* - SPI_HALF_DUPLEX_DIRECTION_TX
* @retval none
*/
void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction)
{
spi_x->ctrl1_bit.slbtd = direction;
}
/**
* @brief enable or disable spi.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4
* @param new_state: new state of spi.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl1_bit.spien = new_state;
}
/**
* @brief i2s init config with its default value.
* @param i2s_init_struct : pointer to a i2s_init_type structure which will
* be initialized.
* @retval none
*/
void i2s_default_para_init(i2s_init_type* i2s_init_struct)
{
i2s_init_struct->operation_mode = I2S_MODE_SLAVE_TX;
i2s_init_struct->audio_protocol = I2S_AUDIO_PROTOCOL_PHILLIPS;
i2s_init_struct->audio_sampling_freq = I2S_AUDIO_FREQUENCY_DEFAULT;
i2s_init_struct->data_channel_format = I2S_DATA_16BIT_CHANNEL_16BIT;
i2s_init_struct->clock_polarity = I2S_CLOCK_POLARITY_LOW;
i2s_init_struct->mclk_output_enable = FALSE;
}
/**
* @brief i2s init config with its setting value.
* @param i2s_init_struct : pointer to a i2s_init_type structure which will be initialized.
* @retval none
*/
void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct)
{
crm_clocks_freq_type clocks_freq;
uint32_t i2s_sclk_index = 0;
uint32_t i2sdiv_index = 2, i2sodd_index = 0, frequency_index = 0;
/* i2s audio frequency config */
if(i2s_init_struct->audio_sampling_freq == I2S_AUDIO_FREQUENCY_DEFAULT)
{
i2sodd_index = 0;
i2sdiv_index = 2;
}
else
{
crm_clocks_freq_get(&clocks_freq);
i2s_sclk_index = clocks_freq.sclk_freq;
if((i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT) || (i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG))
{
if(i2s_init_struct->mclk_output_enable == TRUE)
{
frequency_index = (((i2s_sclk_index / 128) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
else
{
if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
frequency_index = (((i2s_sclk_index / 16) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
else
frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
}
else
{
if(i2s_init_struct->mclk_output_enable == TRUE)
{
frequency_index = (((i2s_sclk_index / 256) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
else
{
if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
else
frequency_index = (((i2s_sclk_index / 64) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
}
}
frequency_index = frequency_index / 10;
i2sodd_index = frequency_index & (uint16_t)0x0001;
i2sdiv_index = (frequency_index - i2sodd_index) / 2;
if((i2sdiv_index < 2) || (i2sdiv_index > 0x03FF))
{
i2sodd_index = 0;
i2sdiv_index = 2;
}
spi_x->i2sclk_bit.i2sodd = i2sodd_index;
if(i2sdiv_index > 0x00FF)
{
spi_x->i2sclk_bit.i2sdiv_h = (i2sdiv_index >> 8) & 0x0003;
spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index & 0x00FF;
}
else
{
spi_x->i2sclk_bit.i2sdiv_h = 0;
spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index;
}
/* i2s audio_protocol set*/
if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG)
{
spi_x->i2sctrl_bit.pcmfssel = 1;
spi_x->i2sctrl_bit.stdsel = 3;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 3;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_LSB)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 2;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_MSB)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 1;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PHILLIPS)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 0;
}
/* i2s data_channel_format set*/
if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
{
spi_x->i2sctrl_bit.i2scbn = 0;
spi_x->i2sctrl_bit.i2sdbn = 0;
}
else if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_32BIT)
{
spi_x->i2sctrl_bit.i2scbn = 1;
spi_x->i2sctrl_bit.i2sdbn = 0;
}
else if(i2s_init_struct->data_channel_format == I2S_DATA_24BIT_CHANNEL_32BIT)
{
spi_x->i2sctrl_bit.i2scbn = 1;
spi_x->i2sctrl_bit.i2sdbn = 1;
}
else if(i2s_init_struct->data_channel_format == I2S_DATA_32BIT_CHANNEL_32BIT)
{
spi_x->i2sctrl_bit.i2scbn = 1;
spi_x->i2sctrl_bit.i2sdbn = 2;
}
spi_x->i2sctrl_bit.i2sclkpol = i2s_init_struct->clock_polarity;
spi_x->i2sclk_bit.i2smclkoe = i2s_init_struct->mclk_output_enable;
spi_x->i2sctrl_bit.opersel = i2s_init_struct->operation_mode;
spi_x->i2sctrl_bit.i2smsel = TRUE;
}
/**
* @brief enable or disable i2s.
* @param spi_x: select the i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT
* @param new_state: new state of i2s.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void i2s_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->i2sctrl_bit.i2sen = new_state;
}
/**
* @brief enable or disable the specified spi/i2s interrupts.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT
* @param spi_i2s_int: specifies the spi/i2s interrupt sources to be enabled or disabled.
* this parameter can be one of the following values:
* - SPI_I2S_ERROR_INT
* - SPI_I2S_RDBF_INT
* - SPI_I2S_TDBE_INT
* @param new_state: new state of the specified spi/i2s interrupts.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state)
{
if(new_state != FALSE)
{
spi_x->ctrl2 |= spi_i2s_int;
}
else
{
spi_x->ctrl2 &= ~spi_i2s_int;
}
}
/**
* @brief enable or disable the spi/i2s dma transmitter mode.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT
* @param new_state: new state of the dma request.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl2_bit.dmaten = new_state;
}
/**
* @brief enable or disable the spi/i2s dma receiver mode.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT
* @param new_state: new state of the dma request.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl2_bit.dmaren = new_state;
}
/**
* @brief spi/i2s data transmit
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT
* @param tx_data: the data to be transmit.
* this parameter can be:
* - (0x0000~0xFFFF)
* @retval none
*/
void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data)
{
spi_x->dt = tx_data;
}
/**
* @brief spi/i2s data receive
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT
* @retval the received data value
*/
uint16_t spi_i2s_data_receive(spi_type* spi_x)
{
return (uint16_t)spi_x->dt;
}
/**
* @brief get flag of the specified spi/i2s peripheral.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT
* @param spi_i2s_flag: select the spi/i2s flag
* this parameter can be one of the following values:
* - SPI_I2S_RDBF_FLAG
* - SPI_I2S_TDBE_FLAG
* - I2S_ACS_FLAG (this flag only use in i2s mode)
* - I2S_TUERR_FLAG (this flag only use in i2s mode)
* - SPI_CCERR_FLAG (this flag only use in spi mode)
* - SPI_MMERR_FLAG (this flag only use in spi mode)
* - SPI_I2S_ROERR_FLAG
* - SPI_I2S_BF_FLAG
* @retval the new state of spi/i2s flag
*/
flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
{
flag_status status = RESET;
if ((spi_x->sts & spi_i2s_flag) == RESET)
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief get interrupt flag of the specified spi/i2s peripheral.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT
* @param spi_i2s_flag: select the spi/i2s flag
* this parameter can be one of the following values:
* - SPI_I2S_RDBF_FLAG
* - SPI_I2S_TDBE_FLAG
* - I2S_TUERR_FLAG (this flag only use in i2s mode)
* - SPI_CCERR_FLAG (this flag only use in spi mode)
* - SPI_MMERR_FLAG (this flag only use in spi mode)
* - SPI_I2S_ROERR_FLAG
* @retval the new state of spi/i2s flag
*/
flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
{
flag_status status = RESET;
switch(spi_i2s_flag)
{
case SPI_I2S_RDBF_FLAG:
if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie)
{
status = SET;
}
break;
case SPI_I2S_TDBE_FLAG:
if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie)
{
status = SET;
}
break;
case I2S_TUERR_FLAG:
if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
case SPI_CCERR_FLAG:
if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
case SPI_MMERR_FLAG:
if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
case SPI_I2S_ROERR_FLAG:
if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
default:
break;
};
return status;
}
/**
* @brief clear flag of the specified spi/i2s peripheral.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT
* @param spi_i2s_flag: select the spi/i2s flag
* this parameter can be one of the following values:
* - SPI_CCERR_FLAG
* - SPI_I2S_RDBF_FLAG
* - I2S_TUERR_FLAG
* - SPI_MMERR_FLAG
* - SPI_I2S_ROERR_FLAG
* @note
* SPI_I2S_TDBE_FLAG this flag is cleared when the tx buffer already contain data to be transmit.
* I2S_ACS_FLAG this flag cann't cleared by software,the flag indicate the channel side(not use in pcm standard mode).
* SPI_I2S_BF_FLAG this flag cann't cleared by software, it's set and cleared by hardware.
* @retval none
*/
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag)
{
if(spi_i2s_flag == SPI_CCERR_FLAG)
spi_x->sts = ~SPI_CCERR_FLAG;
else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG)
UNUSED(spi_x->dt);
else if(spi_i2s_flag == I2S_TUERR_FLAG)
UNUSED(spi_x->sts);
else if(spi_i2s_flag == SPI_MMERR_FLAG)
{
UNUSED(spi_x->sts);
spi_x->ctrl1 = spi_x->ctrl1;
}
else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG)
{
UNUSED(spi_x->dt);
UNUSED(spi_x->sts);
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

597
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/**
**************************************************************************
* @file at32f403a_407_usb.c
* @brief contains the functions for the usb firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @defgroup USB
* @brief USB driver modules
* @{
*/
#include "at32f403a_407_conf.h"
#ifdef USB_MODULE_ENABLED
/** @defgroup USB_private_functions
* @{
*/
/**
* @brief usb packet buffer start address
*/
#define USB_ENDP_DESC_TABLE_OFFSET 0x40
uint32_t g_usb_packet_address = USB_PACKET_BUFFER_ADDRESS;
static uint16_t g_usb_offset_addr = USB_ENDP_DESC_TABLE_OFFSET;
/**
* @brief initialize usb peripheral controller register
* @param usbx: to select the usb peripheral.
* parameter as following values: USB
* @retval none
*/
void usb_dev_init(usbd_type *usbx)
{
/* clear usb core reset */
usbx->ctrl_bit.csrst = 0;
/* clear usb interrupt status */
usbx->intsts = 0;
/* set usb packet buffer descirption table address */
usbx->buftbl = USB_BUFFER_TABLE_ADDRESS;
/* enable usb core and set device address to 0 */
usbx->devaddr = 0x80;
usb_interrupt_enable(usbx, USB_SOF_INT | USB_RST_INT | USB_SP_INT | USB_WK_INT | USB_TC_INT, TRUE);
}
/**
* @brief connect usb device
* @param usbx: to select the usb peripheral.
* parameter as following values: USB
* @retval none
*/
void usb_connect(usbd_type *usbx)
{
/* enable usb phy */
usbx->ctrl_bit.disusb = 0;
/* Dp 1.5k pull-up enable */
usbx->cfg_bit.puo = 0;
}
/**
* @brief disconnect usb device
* @param usbx: to select the usb peripheral.
* parameter as following values: USB
* @retval none
*/
void usb_disconnect(usbd_type *usbx)
{
/* disable usb phy */
usbx->ctrl_bit.disusb = TRUE;
/* D+ 1.5k pull-up disable */
usbx->cfg_bit.puo = TRUE;
}
/**
* @brief mapping usb packet buffer area
* two mapping intervals are available for packet buffer area,
* and are select by the usbbufs in the crm misc1 register.
* when usbbufs is 0,sram size is 512 bytes, packet buffer start
* address is 0x40006000.when usbbufs is 1, sram size is fixed to
* 768~1280 bytes, and the packet buffer start address is fixed to
* 0x40007800,packet buffer size decided by whether can1 and can2 are
* enabled;when both can1 and can2 are disabled, usb packet buffer can be set to the
* maximum of 1280 bytes; when either can1 or can2 is enabled, usb packet buffer can be set to the
* maximum of 1024 bytes; when both CAN1 and CAN2 are enabled, usb packet buffer can be set to the
* maximum of 768 bytes.
* @param usbx: to select the usb peripheral.
* parameter as following values: USB
* @retval none
*/
void usb_usbbufs_enable(usbd_type *usbx, confirm_state state)
{
if(state == TRUE)
{
/* enable usbbufs */
g_usb_packet_address = USB_PACKET_BUFFER_ADDRESS_EX;
CRM->misc1_bit.usbbufs = TRUE;
}
else
{
/* disable usbbufs */
g_usb_packet_address = USB_PACKET_BUFFER_ADDRESS;
CRM->misc1_bit.usbbufs = FALSE;
}
UNUSED(usbx);
}
/**
* @brief open usb endpoint
* @param usbx: to select the usb peripheral.
* parameter as following values: USB
* @param ept_info: endpoint information structure
* @retval none
*/
void usb_ept_open(usbd_type *usbx, usb_ept_info *ept_info)
{
uint16_t type = 0;
/* set endpoint address */
USB_SET_EPT_ADDRESS(ept_info->eptn, ept_info->ept_address);
/* select endpoint transfer type */
if(ept_info->trans_type == EPT_CONTROL_TYPE)
{
type = USB_EPT_CONTROL;
}
else if(ept_info->trans_type == EPT_BULK_TYPE)
{
type = USB_EPT_BULK;
}
else if(ept_info->trans_type == EPT_INT_TYPE)
{
type = USB_EPT_INT;
}
else if(ept_info->trans_type == EPT_ISO_TYPE)
{
type = USB_EPT_ISO;
ept_info->is_double_buffer = TRUE;
}
/* configure endpoint transfer type (control, bulk, interrupt, isochronous) */
USB_SET_TRANS_TYPE(ept_info->eptn, type);
/* endpoint is in transfer */
if(ept_info->inout == DATA_TRANS_IN)
{
if(ept_info->is_double_buffer == 0)
{
/* set in endpoint tx offset address */
USB_SET_TX_ADDRESS(ept_info->eptn, ept_info->tx_addr);
/* clear in endpoint data toggle */
USB_CLEAR_TXDTS(ept_info->eptn);
/* set endpoint transmission status: nak */
USB_SET_TXSTS(ept_info->eptn, USB_TX_NAK);
}
else
{
/* set double buffer endpoint*/
USB_SET_EPT_DOUBLE_BUFFER(ept_info->eptn);
/* set in endpoint offset address0 and address1 */
USB_SET_DOUBLE_BUFF0_ADDRESS(ept_info->eptn, ept_info->tx_addr);
USB_SET_DOUBLE_BUFF1_ADDRESS(ept_info->eptn, ept_info->rx_addr);
/* clear in and out data toggle */
USB_CLEAR_TXDTS(ept_info->eptn);
USB_CLEAR_RXDTS(ept_info->eptn);
/* toggle rx data toggle flag */
USB_TOGGLE_RXDTS(ept_info->eptn);
/* set endpoint reception status: disable */
USB_SET_RXSTS(ept_info->eptn, USB_RX_DISABLE);
/* set endpoint transmision status: nak */
USB_SET_TXSTS(ept_info->eptn, USB_TX_NAK);
}
}
else
{
if(ept_info->is_double_buffer == 0)
{
/* set out endpoint rx offset address */
USB_SET_RX_ADDRESS(ept_info->eptn, ept_info->rx_addr);
/* clear out endpoint data toggle */
USB_CLEAR_RXDTS(ept_info->eptn);
/* set out endpoint max reception buffer size */
USB_SET_RXLEN(ept_info->eptn, ept_info->maxpacket);
/* set endpoint reception status: valid */
USB_SET_RXSTS(ept_info->eptn, USB_RX_VALID);
}
else
{
/* set double buffer endpoint */
USB_SET_EPT_DOUBLE_BUFFER(ept_info->eptn);
/* set out endpoint offset address0 and address1 */
USB_SET_DOUBLE_BUFF0_ADDRESS(ept_info->eptn, ept_info->tx_addr);
USB_SET_DOUBLE_BUFF1_ADDRESS(ept_info->eptn, ept_info->rx_addr);
/* set out endpoint max reception buffer size */
USB_SET_EPT_DOUBLE_BUF0_LEN(ept_info->eptn, ept_info->maxpacket, DATA_TRANS_OUT);
USB_SET_EPT_DOUBLE_BUF1_LEN(ept_info->eptn, ept_info->maxpacket, DATA_TRANS_OUT);
/* clear in and out data toggle */
USB_CLEAR_TXDTS(ept_info->eptn);
USB_CLEAR_RXDTS(ept_info->eptn);
/* toggle tx data toggle flag */
USB_TOGGLE_TXDTS(ept_info->eptn);
/* set endpoint reception status: valid */
USB_SET_RXSTS(ept_info->eptn, USB_RX_VALID);
/* set endpoint transmision status: disable */
USB_SET_TXSTS(ept_info->eptn, USB_TX_DISABLE);
}
}
UNUSED(usbx);
}
/**
* @brief close usb endpoint
* @param usbx: to select the usb peripheral.
* parameter as following values: USB
* @param ept_info: endpoint information structure
* @retval none
*/
void usb_ept_close(usbd_type *usbx, usb_ept_info *ept_info)
{
if(ept_info->is_double_buffer == 0)
{
if(ept_info->inout == DATA_TRANS_IN)
{
/*clear tx data toggle */
USB_CLEAR_TXDTS(ept_info->eptn);
/* set tx status: disable */
USB_SET_TXSTS(ept_info->eptn, USB_TX_DISABLE);
}
else
{
/*clear rx data toggle */
USB_CLEAR_RXDTS(ept_info->eptn);
/* set rx status: disable */
USB_SET_RXSTS(ept_info->eptn, USB_RX_DISABLE);
}
}
else
{
/* double buffer */
/*clear rx and tx data toggle */
USB_CLEAR_TXDTS(ept_info->eptn);
USB_CLEAR_RXDTS(ept_info->eptn);
if(ept_info->inout == DATA_TRANS_IN)
{
/* toggle tx */
USB_TOGGLE_TXDTS(ept_info->eptn);
/* set tx and rx status: disable */
USB_SET_TXSTS(ept_info->eptn, USB_TX_DISABLE);
USB_SET_RXSTS(ept_info->eptn, USB_RX_DISABLE);
}
else
{
/* toggle rx */
USB_TOGGLE_RXDTS(ept_info->eptn);
/* set tx and rx status: disable */
USB_SET_TXSTS(ept_info->eptn, USB_TX_DISABLE);
USB_SET_RXSTS(ept_info->eptn, USB_RX_DISABLE);
}
}
UNUSED(usbx);
}
/**
* @brief write data from user memory to usb buffer
* @param pusr_buf: point to user buffer
* @param offset_addr: endpoint tx offset address
* @param nbytes: number of bytes data write to usb buffer
* @retval none
*/
void usb_write_packet(uint8_t *pusr_buf, uint16_t offset_addr, uint16_t nbytes)
{
/* endpoint tx buffer address */
__IO uint16_t *d_addr = (__IO uint16_t *)(offset_addr * 2 + g_usb_packet_address);
uint32_t nhbytes = (nbytes + 1) >> 1;
uint32_t n_index;
uint16_t *pbuf = (uint16_t *)pusr_buf;
for(n_index = 0; n_index < nhbytes; n_index ++)
{
#if defined (__ICCARM__) && (__VER__ < 7000000)
*d_addr++ = *(__packed uint16_t *)pbuf;
#else
*d_addr++ = __UNALIGNED_UINT16_READ(pbuf);
#endif
d_addr ++;
pbuf ++;
}
}
/**
* @brief read data from usb buffer to user buffer
* @param pusr_buf: point to user buffer
* @param offset_addr: endpoint rx offset address
* @param nbytes: number of bytes data write to usb buffer
* @retval none
*/
void usb_read_packet(uint8_t *pusr_buf, uint16_t offset_addr, uint16_t nbytes)
{
__IO uint16_t *s_addr = (__IO uint16_t *)(offset_addr * 2 + g_usb_packet_address);
uint32_t nhbytes = (nbytes + 1) >> 1;
uint32_t n_index;
uint16_t *pbuf = (uint16_t *)pusr_buf;
for(n_index = 0; n_index < nhbytes; n_index ++)
{
#if defined (__ICCARM__) && (__VER__ < 7000000)
*(__packed uint16_t *)pbuf = *(__IO uint16_t *)s_addr ++;
#else
__UNALIGNED_UINT16_WRITE(pbuf, *(__IO uint16_t *)s_addr ++);
#endif
s_addr ++;
pbuf ++;
}
}
/**
* @brief usb interrupt enable
* @param usbx: to select the usb peripheral.
* parameter as following values: USB
* @param interrupt:
* this parameter can be any combination of the following values:
* - USB_LSOF_INT
* - USB_SOF_INT
* - USB_RST_INT
* - USB_SP_INT
* - USB_WK_INT
* - USB_BE_INT
* - USB_UCFOR_INT
* - USB_TC_INT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void usb_interrupt_enable(usbd_type *usbx, uint16_t interrupt, confirm_state new_state)
{
if(new_state == TRUE)
{
usbx->ctrl |= interrupt;
}
else
{
usbx->ctrl &= ~interrupt;
}
}
/**
* @brief set the host assignment address
* @param usbx: to select the usb peripheral.
* parameter as following values: USB
* @param address: host assignment address
* @retval none
*/
void usb_set_address(usbd_type *usbx, uint8_t address)
{
usbx->devaddr_bit.addr = address;
usbx->devaddr_bit.cen = TRUE;
}
/**
* @brief set endpoint tx or rx status to stall
* @param usbx: to select the usb peripheral.
* parameter as following values: USB
* @param ept_info: endpoint information structure
* @retval none
*/
void usb_ept_stall(usbd_type *usbx, usb_ept_info *ept_info)
{
if(ept_info->inout == DATA_TRANS_IN)
{
USB_SET_TXSTS(ept_info->eptn, USB_TX_STALL)
}
else
{
USB_SET_RXSTS(ept_info->eptn, USB_RX_STALL)
}
UNUSED(usbx);
}
/**
* @brief usb device enter suspend mode
* @param usbx: to select the usb peripheral.
* parameter as following values: USB
* @retval none
*/
void usb_enter_suspend(usbd_type *usbx)
{
usbx->ctrl_bit.ssp = TRUE;
usbx->ctrl_bit.lpm = TRUE;
}
/**
* @brief usb device exit suspend mode
* @param usbx: to select the usb peripheral.
* parameter as following values: USB
* @retval none
*/
void usb_exit_suspend(usbd_type *usbx)
{
usbx->ctrl_bit.ssp = FALSE;
usbx->ctrl_bit.lpm = FALSE;
}
/**
* @brief usb remote wakeup set
* @param usbx: to select the usb peripheral.
* parameter as following values: USB
* @retval none
*/
void usb_remote_wkup_set(usbd_type *usbx)
{
usbx->ctrl_bit.gresume = TRUE;
}
/**
* @brief usb remote wakeup clear
* @param usbx: to select the usb peripheral.
* parameter as following values: USB
* @retval none
*/
void usb_remote_wkup_clear(usbd_type *usbx)
{
usbx->ctrl_bit.gresume = FALSE;
}
/**
* @brief usb auto malloc endpoint buffer
* @param mapacket: endpoint support max packet size
* @retval none
*/
uint16_t usb_buffer_malloc(uint16_t maxpacket)
{
uint16_t offset = g_usb_offset_addr;
g_usb_offset_addr += maxpacket;
return offset;
}
/**
* @brief free usb endpoint buffer
* @param none
* @retval none
*/
void usb_buffer_free(void)
{
g_usb_offset_addr = USB_ENDP_DESC_TABLE_OFFSET;
}
/**
* @brief get flag of usb.
* @param usbx: select the usb peripheral
* @param flag: select the usb flag
* this parameter can be one of the following values:
* - USB_INOUT_FLAG
* - USB_LSOF_FLAG
* - USB_SOF_FLAG
* - USB_RST_FLAG
* - USB_SP_FLAG
* - USB_WK_FLAG
* - USB_BE_FLAG
* - USB_UCFOR_FLAG
* - USB_TC_FLAG
* @retval none
*/
flag_status usb_flag_get(usbd_type *usbx, uint16_t flag)
{
flag_status status = RESET;
if((usbx->intsts & flag) == RESET)
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief get interrupt flag of usb.
* @param usbx: select the usb peripheral
* @param flag: select the usb flag
* this parameter can be one of the following values:
* - USB_LSOF_FLAG
* - USB_SOF_FLAG
* - USB_RST_FLAG
* - USB_SP_FLAG
* - USB_WK_FLAG
* - USB_BE_FLAG
* - USB_UCFOR_FLAG
* - USB_TC_FLAG
* @retval none
*/
flag_status usb_interrupt_flag_get(usbd_type *usbx, uint16_t flag)
{
flag_status status = RESET;
if(flag == USB_TC_FLAG)
{
if(usbx->intsts & USB_TC_FLAG)
status = SET;
}
else
{
if((usbx->intsts & flag) && (usbx->ctrl & flag))
{
status = SET;
}
}
return status;
}
/**
* @brief clear flag of usb.
* @param usbx: select the usb peripheral
* @param flag: select the usb flag
* this parameter can be one of the following values:
* - USB_INOUT_FLAG
* - USB_LSOF_FLAG
* - USB_SOF_FLAG
* - USB_RST_FLAG
* - USB_SP_FLAG
* - USB_WK_FLAG
* - USB_BE_FLAG
* - USB_UCFOR_FLAG
* - USB_TC_FLAG
* @retval none
*/
void usb_flag_clear(usbd_type *usbx, uint16_t flag)
{
usbx->intsts = ~flag;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f403a_407_wdt.c
* @brief contains all the functions for the wdt firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f403a_407_conf.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @defgroup WDT
* @brief WDT driver modules
* @{
*/
#ifdef WDT_MODULE_ENABLED
/** @defgroup WDT_private_functions
* @{
*/
/**
* @brief wdt enable ,the reload value will be sent to the counter
* @param none
* @retval none
*/
void wdt_enable(void)
{
WDT->cmd = WDT_CMD_ENABLE;
}
/**
* @brief reload wdt counter
* @param none
* @retval none
*/
void wdt_counter_reload(void)
{
WDT->cmd = WDT_CMD_RELOAD;
}
/**
* @brief set wdt counter reload value
* @param reload_value (0x0000~0x0FFF)
* @retval none
*/
void wdt_reload_value_set(uint16_t reload_value)
{
WDT->rld = reload_value;
}
/**
* @brief set wdt division divider
* @param division
* this parameter can be one of the following values:
* - WDT_CLK_DIV_4
* - WDT_CLK_DIV_8
* - WDT_CLK_DIV_16
* - WDT_CLK_DIV_32
* - WDT_CLK_DIV_64
* - WDT_CLK_DIV_128
* - WDT_CLK_DIV_256
* @retval none
*/
void wdt_divider_set(wdt_division_type division)
{
WDT->div_bit.div = division;
}
/**
* @brief enable or disable wdt cmd register write
* @param new_state (TRUE or FALSE)
* @retval none
*/
void wdt_register_write_enable( confirm_state new_state)
{
if(new_state == FALSE)
{
WDT->cmd = WDT_CMD_LOCK;
}
else
{
WDT->cmd = WDT_CMD_UNLOCK;
}
}
/**
* @brief get wdt flag
* @param wdt_flag
* this parameter can be one of the following values:
* - WDT_DIVF_UPDATE_FLAG: division value update complete flag.
* - WDT_RLDF_UPDATE_FLAG: reload value update complete flag.
* @retval state of wdt flag
*/
flag_status wdt_flag_get(uint16_t wdt_flag)
{
flag_status status = RESET;
if ((WDT->sts & wdt_flag) != (uint16_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

149
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/**
**************************************************************************
* @file at32f403a_407_wwdt.c
* @brief contains all the functions for the wwdt firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f403a_407_conf.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @defgroup WWDT
* @brief WWDT driver modules
* @{
*/
#ifdef WWDT_MODULE_ENABLED
/** @defgroup WWDT_private_functions
* @{
*/
/**
* @brief wwdt reset by crm reset register
* @retval none
*/
void wwdt_reset(void)
{
crm_periph_reset(CRM_WWDT_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_WWDT_PERIPH_RESET, FALSE);
}
/**
* @brief wwdt division set
* @param division
* this parameter can be one of the following values:
* - WWDT_PCLK1_DIV_4096 (wwdt counter clock = (pclk1/4096)/1)
* - WWDT_PCLK1_DIV_8192 (wwdt counter clock = (pclk1/4096)/2)
* - WWDT_PCLK1_DIV_16384 (wwdt counter clock = (pclk1/4096)/4)
* - WWDT_PCLK1_DIV_32768 (wwdt counter clock = (pclk1/4096)/8)
* @retval none
*/
void wwdt_divider_set(wwdt_division_type division)
{
WWDT->cfg_bit.div = division;
}
/**
* @brief wwdt reload counter interrupt flag clear
* @param none
* @retval none
*/
void wwdt_flag_clear(void)
{
WWDT->sts = 0;
}
/**
* @brief wwdt enable and the counter value load
* @param wwdt_cnt (0x40~0x7f)
* @retval none
*/
void wwdt_enable(uint8_t wwdt_cnt)
{
WWDT->ctrl = wwdt_cnt | WWDT_EN_BIT;
}
/**
* @brief wwdt reload counter interrupt enable
* @param none
* @retval none
*/
void wwdt_interrupt_enable(void)
{
WWDT->cfg_bit.rldien = TRUE;
}
/**
* @brief wwdt reload counter interrupt flag get
* @param none
* @retval state of reload counter interrupt flag
*/
flag_status wwdt_flag_get(void)
{
return (flag_status)WWDT->sts_bit.rldf;
}
/**
* @brief wwdt reload counter interrupt flag get
* @param none
* @retval state of reload counter interrupt flag
*/
flag_status wwdt_interrupt_flag_get(void)
{
return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien);
}
/**
* @brief wwdt counter value set
* @param wwdt_cnt (0x40~0x7f)
* @retval none
*/
void wwdt_counter_set(uint8_t wwdt_cnt)
{
WWDT->ctrl_bit.cnt = wwdt_cnt;
}
/**
* @brief wwdt window counter value set
* @param window_cnt (0x40~0x7f)
* @retval none
*/
void wwdt_window_counter_set(uint8_t window_cnt)
{
WWDT->cfg_bit.win = window_cnt;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

547
libraries/drivers/src/at32f403a_407_xmc.c Normal file
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@@ -0,0 +1,547 @@
/**
**************************************************************************
* @file at32f403a_407_xmc.c
* @brief contains all the functions for the xmc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f403a_407_conf.h"
/** @addtogroup AT32F403A_407_periph_driver
* @{
*/
/** @defgroup XMC
* @brief XMC driver modules
* @{
*/
#ifdef XMC_MODULE_ENABLED
/** @defgroup XMC_private_functions
* @{
*/
/**
* @brief xmc nor or sram registers reset
* @param xmc_subbank
* this parameter can be one of the following values:
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM4
* @retval none
*/
void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank)
{
/* XMC_BANK1_NORSRAM1 */
if(xmc_subbank == XMC_BANK1_NOR_SRAM1)
{
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030DB;
}
/* XMC_BANK1_NORSRAM2, XMC_BANK1_NORSRAM3 or XMC_BANK1_NORSRAM4 */
else
{
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030D2;
}
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1tmg = 0x0FFFFFFF;
XMC_BANK1->tmgwr_group[xmc_subbank].bk1tmgwr = 0x0FFFFFFF;
}
/**
* @brief initialize the xmc nor/sram banks according to the specified
* parameters in the xmc_norsraminitstruct.
* @param xmc_norsram_init_struct : pointer to a xmc_norsram_init_type
* structure that contains the configuration information for
* the xmc nor/sram specified banks.
* @retval none
*/
void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct)
{
/* bank1 nor/sram control register configuration */
XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl =
(uint32_t)xmc_norsram_init_struct->data_addr_multiplex |
xmc_norsram_init_struct->device |
xmc_norsram_init_struct->bus_type |
xmc_norsram_init_struct->burst_mode_enable |
xmc_norsram_init_struct->asynwait_enable |
xmc_norsram_init_struct->wait_signal_lv |
xmc_norsram_init_struct->wrapped_mode_enable |
xmc_norsram_init_struct->wait_signal_config |
xmc_norsram_init_struct->write_enable |
xmc_norsram_init_struct->wait_signal_enable |
xmc_norsram_init_struct->write_timing_enable |
xmc_norsram_init_struct->write_burst_syn;
/* if nor flash device */
if(xmc_norsram_init_struct->device == XMC_DEVICE_NOR)
{
XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl_bit.noren = 0x1;
}
}
/**
* @brief initialize the xmc nor/sram banks according to the specified
* parameters in the xmc_rw_timing_struct and xmc_w_timing_struct.
* @param xmc_rw_timing_struct : pointer to a xmc_norsram_timing_init_type
* structure that contains the configuration information for
* the xmc nor/sram specified banks.
* @param xmc_w_timing_struct : pointer to a xmc_norsram_timing_init_type
* structure that contains the configuration information for
* the xmc nor/sram specified banks.
* @retval none
*/
void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
xmc_norsram_timing_init_type* xmc_w_timing_struct)
{
/* bank1 nor/sram timing register configuration */
XMC_BANK1->ctrl_tmg_group[xmc_rw_timing_struct->subbank].bk1tmg =
(uint32_t)xmc_rw_timing_struct->addr_setup_time |
(xmc_rw_timing_struct->addr_hold_time << 4) |
(xmc_rw_timing_struct->data_setup_time << 8) |
(xmc_rw_timing_struct->bus_latency_time <<16) |
(xmc_rw_timing_struct->clk_psc << 20) |
(xmc_rw_timing_struct->data_latency_time << 24) |
xmc_rw_timing_struct->mode;
/* bank1 nor/sram timing register for write configuration, if extended mode is used */
if(xmc_rw_timing_struct->write_timing_enable == XMC_WRITE_TIMING_ENABLE)
{
XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr =
(uint32_t)xmc_w_timing_struct->addr_setup_time |
(xmc_w_timing_struct->addr_hold_time << 4) |
(xmc_w_timing_struct->data_setup_time << 8) |
(xmc_w_timing_struct->bus_latency_time << 16) |
(xmc_w_timing_struct->clk_psc << 20) |
(xmc_w_timing_struct->data_latency_time << 24) |
xmc_w_timing_struct->mode;
}
else
{
XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr = 0x0FFFFFFF;
}
}
/**
* @brief fill each xmc_nor_sram_init_struct member with its default value.
* @param xmc_nor_sram_init_struct: pointer to a xmc_norsram_init_type
* structure which will be initialized.
* @retval none
*/
void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct)
{
/* reset nor/sram init structure parameters values */
xmc_nor_sram_init_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_nor_sram_init_struct->data_addr_multiplex = XMC_DATA_ADDR_MUX_ENABLE;
xmc_nor_sram_init_struct->device = XMC_DEVICE_SRAM;
xmc_nor_sram_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
xmc_nor_sram_init_struct->burst_mode_enable = XMC_BURST_MODE_DISABLE;
xmc_nor_sram_init_struct->asynwait_enable = XMC_ASYN_WAIT_DISABLE;
xmc_nor_sram_init_struct->wait_signal_lv = XMC_WAIT_SIGNAL_LEVEL_LOW;
xmc_nor_sram_init_struct->wrapped_mode_enable = XMC_WRAPPED_MODE_DISABLE;
xmc_nor_sram_init_struct->wait_signal_config = XMC_WAIT_SIGNAL_SYN_BEFORE;
xmc_nor_sram_init_struct->write_enable = XMC_WRITE_OPERATION_ENABLE;
xmc_nor_sram_init_struct->wait_signal_enable = XMC_WAIT_SIGNAL_ENABLE;
xmc_nor_sram_init_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
xmc_nor_sram_init_struct->write_burst_syn = XMC_WRITE_BURST_SYN_DISABLE;
}
/**
* @brief fill each xmc_rw_timing_struct and xmc_w_timing_struct member with its default value.
* @param xmc_rw_timing_struct: pointer to a xmc_norsram_timing_init_type
* structure which will be initialized.
* @param xmc_w_timing_struct: pointer to a xmc_norsram_timing_init_type
* structure which will be initialized.
* @retval none
*/
void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
xmc_norsram_timing_init_type* xmc_w_timing_struct)
{
xmc_rw_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_rw_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
xmc_rw_timing_struct->addr_setup_time = 0xF;
xmc_rw_timing_struct->addr_hold_time = 0xF;
xmc_rw_timing_struct->data_setup_time = 0xFF;
xmc_rw_timing_struct->bus_latency_time = 0xF;
xmc_rw_timing_struct->clk_psc = 0xF;
xmc_rw_timing_struct->data_latency_time = 0xF;
xmc_rw_timing_struct->mode = XMC_ACCESS_MODE_A;
xmc_w_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
xmc_w_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
xmc_w_timing_struct->addr_setup_time = 0xF;
xmc_w_timing_struct->addr_hold_time = 0xF;
xmc_w_timing_struct->data_setup_time = 0xFF;
xmc_w_timing_struct->bus_latency_time = 0xF;
xmc_w_timing_struct->clk_psc = 0xF;
xmc_w_timing_struct->data_latency_time = 0xF;
xmc_w_timing_struct->mode = XMC_ACCESS_MODE_A;
}
/**
* @brief enable or disable the specified nor/sram memory bank.
* @param xmc_subbank
* this parameter can be one of the following values:
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM4
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state)
{
XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl_bit.en = new_state;
}
/**
* @brief config the bus turnaround phase.
* @param xmc_sub_bank
* this parameter can be one of the following values:
* - XMC_BANK1_NOR_SRAM1
* - XMC_BANK1_NOR_SRAM4
* @param w2w_timing :write timing
* @param r2r_timing :read timing
* @retval none
*/
void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
{
XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing;
XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing;
}
/**
* @brief xmc nand flash registers reset
* @param xmc_bank
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* @retval none
*/
void xmc_nand_reset(xmc_class_bank_type xmc_bank)
{
/* set the XMC_BANK2_NAND registers to their reset values */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl = 0x00000018;
XMC_BANK2->bk2is = 0x00000040;
XMC_BANK2->bk2tmgatt = 0xFCFCFCFC;
XMC_BANK2->bk2tmgmem = 0xFCFCFCFC;
}
}
/**
* @brief initialize the xmc nand banks according to the specified
* parameters in the xmc_nandinitstruct.
* @param xmc_nand_init_struct : pointer to a xmc_nand_init_type
* structure that contains the configuration information for the xmc
* nand specified banks.
* @retval none
*/
void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct)
{
uint32_t tempctrl = 0x0;
/* Set the tempctrl value according to xmc_nand_init_struct parameters */
tempctrl = (uint32_t)xmc_nand_init_struct->wait_enable |
xmc_nand_init_struct->bus_type |
xmc_nand_init_struct->ecc_enable |
xmc_nand_init_struct->ecc_pagesize |
(xmc_nand_init_struct->delay_time_cycle << 9) |
(xmc_nand_init_struct->delay_time_ar << 13) |
0x00000008;
/* xmc_bank2_nand registers configuration */
if(xmc_nand_init_struct->nand_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl = tempctrl;
}
}
/**
* @brief initialize the xmc nand banks according to the specified
* parameters in the xmc_nandinitstruct.
* @param xmc_regular_spacetiming_struct : pointer to a xmc_nand_timinginit_type
* structure that contains the configuration information for the xmc
* nand specified banks.
* @param xmc_special_spacetiming_struct : pointer to a xmc_nand_timinginit_type
* structure that contains the configuration information for the xmc
* nand specified banks.
* @retval none
*/
void xmc_nand_timing_config(xmc_nand_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_timinginit_type* xmc_special_spacetiming_struct)
{
uint32_t tempmem = 0x0, tempatt = 0x0;
/* set the tempmem value according to xmc_nand_init_struct parameters */
tempmem = (uint32_t)xmc_regular_spacetiming_struct->mem_setup_time |
(xmc_regular_spacetiming_struct->mem_waite_time << 8) |
(xmc_regular_spacetiming_struct->mem_hold_time << 16) |
(xmc_regular_spacetiming_struct->mem_hiz_time << 24);
/* set the tempatt value according to xmc_nand_init_struct parameters */
tempatt = (uint32_t)xmc_special_spacetiming_struct->mem_setup_time |
(xmc_special_spacetiming_struct->mem_waite_time << 8) |
(xmc_special_spacetiming_struct->mem_hold_time << 16) |
(xmc_special_spacetiming_struct->mem_hiz_time << 24);
/* xmc_bank2_nand registers configuration */
if(xmc_regular_spacetiming_struct->class_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2tmgatt = tempatt;
XMC_BANK2->bk2tmgmem = tempmem;
}
}
/**
* @brief fill each xmc_nand_init_struct member with its default value.
* @param xmc_nand_init_struct: pointer to a xmc_nand_init_type
* structure which will be initialized.
* @retval none
*/
void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct)
{
/* reset nand init structure parameters values */
xmc_nand_init_struct->nand_bank = XMC_BANK2_NAND;
xmc_nand_init_struct->wait_enable = XMC_WAIT_OPERATION_DISABLE;
xmc_nand_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
xmc_nand_init_struct->ecc_enable = XMC_ECC_OPERATION_DISABLE;
xmc_nand_init_struct->ecc_pagesize = XMC_ECC_PAGESIZE_256_BYTES;
xmc_nand_init_struct->delay_time_cycle = 0x0;
xmc_nand_init_struct->delay_time_ar = 0x0;
}
/**
* @brief fill each xmc_common_spacetiming_struct and xmc_attribute_spacetiming_struct member with its default value.
* @param xmc_common_spacetiming_struct: pointer to a xmc_nand_timinginit_type
* structure which will be initialized.
* @param xmc_special_spacetiming_struct: pointer to a xmc_nand_timinginit_type
* structure which will be initialized.
* @retval none
*/
void xmc_nand_timing_default_para_init(xmc_nand_timinginit_type* xmc_regular_spacetiming_struct,
xmc_nand_timinginit_type* xmc_special_spacetiming_struct)
{
xmc_regular_spacetiming_struct->class_bank = XMC_BANK2_NAND;
xmc_regular_spacetiming_struct->mem_hold_time = 0xFC;
xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
xmc_special_spacetiming_struct->class_bank = XMC_BANK2_NAND;
xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
xmc_special_spacetiming_struct->mem_hiz_time = 0xFC;
}
/**
* @brief enable or disable the specified nand memory bank.
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
{
/* enable or disable the nand bank2 by setting the en bit in the bk2ctrl register */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl_bit.en = new_state;
}
}
/**
* @brief enable or disable the xmc nand ecc feature.
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
{
/* enable the selected nand bank2 ecc function by setting the eccen bit in the bk2ctrl register */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2ctrl_bit.eccen = new_state;
}
}
/**
* @brief return the error correction code register value.
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* @retval the error correction code (ecc) value.
*/
uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank)
{
uint32_t eccvaule = 0x0;
/* get the bk2ecc register value */
if(xmc_bank == XMC_BANK2_NAND)
{
eccvaule = XMC_BANK2->bk2ecc;
}
/* return the error correction code value */
return eccvaule;
}
/**
* @brief enable or disable the specified xmc interrupts.
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* @param xmc_int: specifies the xmc interrupt sources to be enabled or disabled.
* this parameter can be any combination of the following values:
* - XMC_INT_RISING_EDGE
* - XMC_INT_LEVEL
* - XMC_INT_FALLING_EDGE
* @param new_state (TRUE or FALSE)
* @retval none
*/
void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state)
{
if(new_state != FALSE)
{
/* enable the selected xmc_bank2 interrupts */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2is |= xmc_int;
}
}
else
{
/* disable the selected xmc_bank2 interrupts */
if(xmc_bank == XMC_BANK2_NAND)
{
XMC_BANK2->bk2is &= ~xmc_int;
}
}
}
/**
* @brief check whether the specified xmc flag is set or not.
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* @param xmc_flag: specifies the flag to check.
* this parameter can be any combination of the following values:
* - XMC_RISINGEDGE_FLAG
* - XMC_LEVEL_FLAG
* - XMC_FALLINGEDGE_FLAG
* - XMC_FEMPT_FLAG
* @retval none
*/
flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
{
flag_status status = RESET;
uint32_t temp = 0;
if(xmc_bank == XMC_BANK2_NAND)
{
temp = XMC_BANK2->bk2is;
}
/* get the flag status */
if((temp & xmc_flag) == RESET)
{
status = RESET;
}
else
{
status = SET;
}
/* return the flag status */
return status;
}
/**
* @brief check whether the specified xmc interrupt flag is set or not.
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* @param xmc_flag: specifies the flag to check.
* this parameter can be any combination of the following values:
* - XMC_RISINGEDGE_FLAG
* - XMC_LEVEL_FLAG
* - XMC_FALLINGEDGE_FLAG
* @retval none
*/
flag_status xmc_interrupt_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
{
flag_status status = RESET;
switch(xmc_flag)
{
case XMC_RISINGEDGE_FLAG:
if(XMC_BANK2->bk2is_bit.reien && XMC_BANK2->bk2is_bit.res)
status = SET;
break;
case XMC_LEVEL_FLAG:
if(XMC_BANK2->bk2is_bit.feien && XMC_BANK2->bk2is_bit.fes)
status = SET;
break;
case XMC_FALLINGEDGE_FLAG:
if(XMC_BANK2->bk2is_bit.hlien && XMC_BANK2->bk2is_bit.hls)
status = SET;
break;
default:
break;
}
/* return the flag status */
return status;
}
/**
* @brief clear the xmc's pending flags.
* @param xmc_bank: specifies the xmc bank to be used
* this parameter can be one of the following values:
* - XMC_BANK2_NAND
* @param xmc_flag: specifies the flag to check.
* this parameter can be any combination of the following values:
* - XMC_RISINGEDGE_FLAG
* - XMC_LEVEL_FLAG
* - XMC_FALLINGEDGE_FLAG
* - XMC_FEMPT_FLAG
* @retval none
*/
void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
{
__IO uint32_t int_state;
if(xmc_bank == XMC_BANK2_NAND)
{
int_state = XMC_BANK2->bk2is & 0x38; /* keep interrupt state */
XMC_BANK2->bk2is = (~(xmc_flag | 0x38) | int_state);
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/